122 lines
4.1 KiB
VHDL
122 lines
4.1 KiB
VHDL
-- altera vhdl_input_version vhdl_2008
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-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.rtps_package.all;
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use work.ros_package.all;
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entity AddTwoInts is
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port (
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-- SYSTEM
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clk : in std_logic;
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reset : in std_logic;
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-- SERVICE SERVER
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start : out std_logic;
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ack : in std_logic;
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opcode : out ROS_SERVICE_OPCODE_TYPE;
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service_info : in SERVICE_INFO_TYPE;
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request_id : out REQUEST_ID_TYPE;
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taken : in std_logic;
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data_available : in std_logic;
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a : in std_logic_vector(CDR_LONG_LONG_WIDTH-1 downto 0);
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b : in std_logic_vector(CDR_LONG_LONG_WIDTH-1 downto 0);
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sum : out std_logic_vector(CDR_LONG_LONG_WIDTH-1 downto 0);
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done : in std_logic;
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return_code : in std_logic_vector(ROS_RETCODE_WIDTH-1 downto 0)
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);
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end entity;
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architecture arch of AddTwoInts is
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--*****TYPE DECLARATION*****
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type STAGE_TYPE is (IDLE,A1,B2,C3,D4);
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--*****SIGNAL DECLARATION*****
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signal stage, stage_next : STAGE_TYPE;
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signal sum_sig, sum_sig_next : std_logic_vector(CDR_LONG_LONG_WIDTH-1 downto 0);
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signal request_id_sig, request_id_sig_next : REQUEST_ID_TYPE;
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begin
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sum <= sum_sig;
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request_id <= request_id_sig;
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main_prc : process(all)
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begin
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-- DEFAULT
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stage_next <= stage;
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sum_sig_next <= sum_sig;
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request_id_sig_next <= request_id_sig;
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-- DEFAULT Unregistered
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start <= '0';
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opcode <= NOP;
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case (stage) is
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when IDLE =>
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-- Reader has Available Data
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if (data_available = '1') then
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stage_next <= A1;
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end if;
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when A1 =>
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start <= '1';
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opcode <= TAKE_REQUEST;
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if (ack = '1') then
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stage_next <= B2;
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end if;
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when B2 =>
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if (done = '1') then
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case (return_code) is
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when ROS_RET_OK =>
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if (taken = '1') then
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sum_sig_next <= std_logic_vector(unsigned(a) + unsigned(b));
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request_id_sig_next <= service_info.request_id;
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stage_next <= C3;
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else
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stage_next <= IDLE;
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end if;
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when others =>
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report "AddTwoInts: Error taking request" severity FAILURE;
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stage_next <= IDLE;
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end case;
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end if;
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when C3 =>
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start <= '1';
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opcode <= SEND_RESPONSE;
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if (ack = '1') then
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stage_next <= D4;
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end if;
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when D4 =>
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if (done = '1') then
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case (return_code) is
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when ROS_RET_OK =>
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-- DONE
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stage_next <= IDLE;
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when others =>
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report "AddTwoInts: Error sending response" severity FAILURE;
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stage_next <= IDLE;
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end case;
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end if;
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end case;
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end process;
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sync_prc : process(clk)
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begin
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if rising_edge(clk) then
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if (reset = '1') then
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stage <= IDLE;
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request_id_sig <= EMPTY_REQUEST_ID;
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sum_sig <= (others => '0');
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else
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stage <= stage_next;
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request_id_sig <= request_id_sig_next;
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sum_sig <= sum_sig_next;
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end if;
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end if;
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end process;
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end architecture;
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