Greek64
5d9acb6f41
QSYS does not allow to change the VHDL version of processed files. All respective files have to have a comment directive forcing the VHDL version.
41 lines
1.0 KiB
VHDL
41 lines
1.0 KiB
VHDL
-- altera vhdl_input_version vhdl_2008
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-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.math_pkg.all;
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use work.rtps_package.all;
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-- Test synthesis of SLV bit counter
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entity test is
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port (
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clk : in std_logic;
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reset : in std_logic;
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input : in std_logic_vector(31 downto 0);
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output : out std_logic_vector(31 downto 0)
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);
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end entity;
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architecture arch of test is
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function bitmap_converter(input : std_logic_vector) return natural is
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variable ret : natural := 0;
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begin
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for i in 0 to input'length-1 loop
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ret := ret + 1;
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if (input(i) = '1') then
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exit;
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end if;
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end loop;
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return ret;
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end function;
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begin
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output <= std_logic_vector(to_unsigned(bitmap_converter(input), output'length));
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end architecture;
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