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Day 2 Labor Fixes

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This commit is contained in:
John Ring 2021-03-24 10:52:36 +01:00
parent b6357a993e
commit 3f111508c1
1 changed files with 127 additions and 30 deletions
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157
src/feedback_loop.vhd
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@ -136,13 +136,18 @@ architecture arch of feedback_loop is
); );
end component; end component;
--*****CONSTANT DECLARATION*****
constant CONST_MAX : unsigned(DAC_DATA_WIDTH-1 downto 0) := (others => '1');
constant CONST_HALF : unsigned(DAC_DATA_WIDTH-1 downto 0) := (DAC_DATA_WIDTH-1 => '1', others => '0');
--*****SIGNAL DECLARATION***** --*****SIGNAL DECLARATION*****
signal delay_out : std_logic_vector(ADC_DATA_WIDTH downto 0) := (others => '0'); signal delay_out : std_logic_vector(ADC_DATA_WIDTH downto 0) := (others => '0');
signal latch_out : std_logic_vector(ADC_DATA_WIDTH-1 downto 0) := (others => '0'); signal latch_out : std_logic_vector(ADC_DATA_WIDTH-1 downto 0) := (others => '0');
signal inputA_wide, inputB_wide : std_logic_vector(DAC_DATA_WIDTH downto 0) := (others => '0');
signal addsub_out, inputA, inputB : std_logic_vector(DAC_DATA_WIDTH-1 downto 0) := (others => '0'); signal addsub_out, inputA, inputB : std_logic_vector(DAC_DATA_WIDTH-1 downto 0) := (others => '0');
signal scaler_out, scaler_offset : std_logic_vector(DAC_DATA_WIDTH downto 0) := (others => '0'); signal scaler_1_out, scaler_2_out, scaler_offset_1, scaler_offset_2 : std_logic_vector(DAC_DATA_WIDTH downto 0) := (others => '0');
signal scaler_done, addsub_done : std_logic := '0'; signal scaler_done, addsub_done : std_logic := '0';
signal offset_factor : std_logic_vector(FACTOR_WIDTH-1 downto 0) := (others => '0'); signal offset_factor, tmp : std_logic_vector(FACTOR_WIDTH-1 downto 0) := (others => '0');
begin begin
@ -183,7 +188,7 @@ begin
addsub_offset_inst : addsub addsub_offset_inst : addsub
generic map( generic map(
PIPELINE_STAGES => 1, PIPELINE_STAGES => 0,
DATA_WIDTH => FACTOR_WIDTH DATA_WIDTH => FACTOR_WIDTH
) )
port map( port map(
@ -193,11 +198,14 @@ begin
cap => '0', cap => '0',
A => (FACTOR_WIDTH-1 => '1', others => '0'), A => (FACTOR_WIDTH-1 => '1', others => '0'),
B => factor, B => factor,
RES => offset_factor RES => tmp
); );
--TODO: Fix me
offset_factor <= tmp when (factor(FACTOR_WIDTH-1) = '0') else ("0" & factor(FACTOR_WIDTH-2 downto 0));
--*****STAGE III***** --*****STAGE III*****
scaler_A_inst : scaler scaler_1_inst : scaler
generic map( generic map(
DATA_WIDTH => ADC_DATA_WIDTH, DATA_WIDTH => ADC_DATA_WIDTH,
FACTOR_WIDTH => FACTOR_WIDTH, FACTOR_WIDTH => FACTOR_WIDTH,
@ -207,10 +215,23 @@ begin
clk => clk, clk => clk,
data_in => delay_out(ADC_DATA_WIDTH-1 downto 0), data_in => delay_out(ADC_DATA_WIDTH-1 downto 0),
factor => factor, factor => factor,
data_out => scaler_out data_out => scaler_1_out
); );
scaler_offset_inst : scaler scaler_2_inst : scaler
generic map(
DATA_WIDTH => ADC_DATA_WIDTH,
FACTOR_WIDTH => FACTOR_WIDTH,
PIPELINE_STAGES => 1
)
port map(
clk => clk,
data_in => adc_data2,
factor => "10101", --1.32
data_out => scaler_2_out
);
scaler_offset_1_inst : scaler
generic map( generic map(
DATA_WIDTH => ADC_DATA_WIDTH, DATA_WIDTH => ADC_DATA_WIDTH,
FACTOR_WIDTH => FACTOR_WIDTH, FACTOR_WIDTH => FACTOR_WIDTH,
@ -220,7 +241,20 @@ begin
clk => clk, clk => clk,
data_in => (ADC_DATA_WIDTH-1 => '0', others => '1'), data_in => (ADC_DATA_WIDTH-1 => '0', others => '1'),
factor => offset_factor, factor => offset_factor,
data_out => scaler_offset data_out => scaler_offset_1
);
scaler_offset_2_inst : scaler
generic map(
DATA_WIDTH => ADC_DATA_WIDTH,
FACTOR_WIDTH => FACTOR_WIDTH,
PIPELINE_STAGES => 1
)
port map(
clk => clk,
data_in => (ADC_DATA_WIDTH-1 => '0', others => '1'),
factor => "00101", --0.32
data_out => scaler_offset_2
); );
process(clk) process(clk)
@ -245,7 +279,7 @@ begin
end if; end if;
end process; end process;
addsub_instB : addsub addsub_1_inst : addsub
generic map( generic map(
PIPELINE_STAGES => 0, PIPELINE_STAGES => 0,
DATA_WIDTH => DAC_DATA_WIDTH+1 DATA_WIDTH => DAC_DATA_WIDTH+1
@ -255,18 +289,50 @@ begin
reset => reset, reset => reset,
mode => not factor(FACTOR_WIDTH-1), mode => not factor(FACTOR_WIDTH-1),
cap => '0', cap => '0',
A => scaler_out, A => scaler_1_out,
B => scaler_offset, B => scaler_offset_1,
RES(DAC_DATA_WIDTH) => open, --Truncate Carry Bit RES => inputB_wide
RES(DAC_DATA_WIDTH-1 downto 0) => inputB
); );
addsub_2_inst : addsub
generic map(
PIPELINE_STAGES => 0,
DATA_WIDTH => DAC_DATA_WIDTH+1
)
port map(
clk => clk,
reset => reset,
mode => '0',
cap => '0',
A => scaler_2_out,
B => scaler_offset_2,
RES => inputA_wide
);
cap_B_prc : process(all)
begin
if (inputB_wide(DAC_DATA_WIDTH) = '1') then
if (factor(FACTOR_WIDTH-1) = '1') then
inputB <= (others => '0');
else
inputB <= (others => '1');
end if;
else
inputB <= inputB_wide(DAC_DATA_WIDTH-1 downto 0);
end if;
end process;
--*****STAGE IV***** --*****STAGE IV*****
mux: process(all) mux: process(all)
begin begin
if (add_input_mux = '1') then if (add_input_mux = '1') then
inputA <= latch_out & "0000"; if (inputA_wide(DAC_DATA_WIDTH) = '1') then
--TODO: CAP Needed?
inputA <= (others => '0');
else
inputA <= inputA_wide(DAC_DATA_WIDTH-1 downto 0);
end if;
else else
if (addsub_mode = '1') then if (addsub_mode = '1') then
inputA <= (others => '0'); inputA <= (others => '0');
@ -276,20 +342,51 @@ begin
end if; end if;
end process; end process;
addsub_instA : addsub add_sub_prc : process (all)
generic map( variable tmp_res : unsigned(inputB'length-1 downto 0) := (others => '0');
PIPELINE_STAGES => 1, begin
DATA_WIDTH => DAC_DATA_WIDTH if rising_edge(clk) then
) if (reset = '1') then
port map( addsub_out <= (others => '0');
clk => clk, else
reset => reset, -- Both Inputs
mode => addsub_mode, if (add_input_mux = '1') then
cap => add_input_mux, -- ADD
A => inputA, if (addsub_mode = '1') then
B => inputB, tmp_res := unsigned(inputB) + unsigned(inputA);
RES => addsub_out -- SUB
); else
tmp_res := unsigned(inputB) - unsigned(inputA);
end if;
addsub_out <= std_logic_vector(tmp_res + CONST_HALF);
-- Single Input
else
-- ADD
if (addsub_mode = '1') then
addsub_out <= inputB;
-- SUB
else
addsub_out <= std_logic_vector(CONST_MAX - unsigned(inputB));
end if;
end if;
end if;
end if;
end process;
-- addsub_instA : addsub
-- generic map(
-- PIPELINE_STAGES => 1,
-- DATA_WIDTH => DAC_DATA_WIDTH
-- )
-- port map(
-- clk => clk,
-- reset => reset,
-- mode => addsub_mode,
-- cap => add_input_mux,
-- A => inputA,
-- B => inputB,
-- RES => addsub_out
-- );
process(clk) process(clk)
begin begin
@ -343,8 +440,8 @@ begin
end if; end if;
-- SCALER MAX VALUES -- SCALER MAX VALUES
elsif (scaler_done = '1') then elsif (scaler_done = '1') then
if (to_integer(unsigned(scaler_out)) >= to_integer(unsigned(scaler_max))) then if (to_integer(unsigned(scaler_1_out)) >= to_integer(unsigned(scaler_max))) then
scaler_max <= scaler_out; scaler_max <= scaler_1_out(DAC_DATA_WIDTH-1 downto 0);
end if; end if;
end if; end if;
end if; end if;