* Update docs

- Download correct 7-series reference
* Add design top entity
* Add synchronizer
* Fix syntax, synth errors

src/addsub.vhd

@@ -31,7 +31,7 @@ end entity;
 architecture arch of addsub is
     
     --*****SIGNAl DECLARATION
-    signal result std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
+    signal result : std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
     signal carry : std_logic := '0';
     
 begin

src/async_fifo.vhd

@@ -11,8 +11,8 @@ entity async_fifo is
         generic (
             DATA_WIDTH          : integer := 32;
             FIFO_DEPTH          : integer := 16;    -- (16 - 4194304)
-            PROG_EMPTY  : integer := 3;     -- MIN:3    MAX:(FIFO_DEPTH-3)
+            PROG_EMPTY_THRESH   : integer := 3;     -- MIN:3    MAX:(FIFO_DEPTH-3)
-            PROG_FULL   : integer := 13     -- MIN:3+CDC_SYNC_STAGES    MAX:(FIFO_DEPTH-3)
+            PROG_FULL_THRESH    : integer := 13     -- MIN:3+CDC_SYNC_STAGES    MAX:(FIFO_DEPTH-3)
         );
         port (
             wr_clk      : in std_logic;
@@ -47,8 +47,8 @@ begin
             FIFO_READ_LATENCY   => 1,
             FIFO_WRITE_DEPTH    => FIFO_DEPTH,
             FULL_RESET_VALUE    => 1,
-            PROG_EMPTY_THRESH   => PROG_EMPTY,
+            PROG_EMPTY_THRESH   => PROG_EMPTY_THRESH,
-            PROG_FULL_THRESH    => PROG_FULL,
+            PROG_FULL_THRESH    => PROG_FULL_THRESH,
             RD_DATA_COUNT_WIDTH => 1,
             READ_DATA_WIDTH     => DATA_WIDTH,
             READ_MODE           => "std",
@@ -84,7 +84,7 @@ begin
             rst             => reset,
             sleep           => '0',
             wr_clk          => wr_clk,
-            wr_en           => wr_en and (not wr_busy)
+            wr_en           => wen and (not wr_busy)
         );
 
 end architecture;

src/delay_line.vhd

@@ -19,6 +19,7 @@ entity delay_line is
         );
         port (
             clk         : in std_logic;
+            reset       : in std_logic;
             delay       : in std_logic_vector(DELAY_WIDTH-1 downto 0);
             data_in     : in std_logic_vector(DATA_WIDTH-1 downto 0);
             data_out    : out std_logic_vector(DATA_WIDTH-1 downto 0)
@@ -54,7 +55,7 @@ begin
         generic map (
             ADDR_WIDTH      => DELAY_WIDTH,
             DATA_WIDTH      => DATA_WIDTH
-        );
+        )
         port map(
             clk         => clk,
             addr        => std_logic_vector(to_unsigned(cnt,DELAY_WIDTH)),
@@ -84,15 +85,17 @@ begin
         end if;
     end process;
     
-    sync : process(clk, reset)
+    sync : process(clk)
     begin
+        if rising_edge(clk) then
             if (reset = '1') then
                 cnt     <= 0;
                 cnt_max <= 0;
-        elsif(rising_edge(clk)) then
+            else
                 cnt     <= cnt_next;
                 cnt_max <= cnt_max_next;
             end if;
+        end if;
     end process;
     
 end architecture;

src/dual_port_ram.vhd

@@ -5,6 +5,7 @@ use ieee.numeric_std.all;
 Library xpm;
 use xpm.vcomponents.all;
 
+-- NOTE: This entity instantiates Block RAM.
 -- NOTE: Simutanous reads and writes to the same addresses have to be prevented by external means!
 
 entity dual_port_ram is
@@ -39,7 +40,7 @@ begin
             MEMORY_INIT_FILE        => "none",
             MEMORY_INIT_PARAM       => "0",
             MEMORY_OPTIMIZATION     => "true",
-            MEMORY_PRIMITIVE        => "auto",
+            MEMORY_PRIMITIVE        => "block",
             MEMORY_SIZE             => DATA_WIDTH*(2**ADDR_WIDTH),
             MESSAGE_CONTROL         => 0,
             READ_DATA_WIDTH_B       => DATA_WIDTH,
@@ -47,7 +48,7 @@ begin
             READ_RESET_VALUE_B      => "0",
             RST_MODE_A              => "SYNC",
             RST_MODE_B              => "SYNC",
-            USE_EMBEDDED_CONSTRAINT => 1, --TODO
+            USE_EMBEDDED_CONSTRAINT => 0, --TODO
             USE_MEM_INIT            => 1,
             WAKEUP_TIME             => "disable_sleep",
             WRITE_DATA_WIDTH_A      => DATA_WIDTH,
@@ -69,7 +70,7 @@ begin
             regceb          => '1',
             rstb            => '0',
             sleep           => '0',
-            wea             => wen
+            wea             => (others => wen) --1-bit Vector
         );
 
 end architecture;

src/feedback_controller.vhd

@@ -6,7 +6,7 @@ use work.typedef_package.all;
 
 -- Feedback Controller
 -- This entity reads from the config memory and applies the resepctive configuration when the relevant 
--- timestamp is reached or exceeded. The timer starts counting when a high level is detected in the 'sync'
+-- timestamp is reached or exceeded. The timer starts counting when a high level is detected in the 'sync_pulse'
 -- signal after a reset.
 -- NOTE: This entity is continuosly reading from the memory, except when the 'reset' signal is held high.
 
@@ -24,7 +24,7 @@ entity feedback_controller is
         clk             : in std_logic;
         reset           : in std_logic;
         
-        sync            : in std_logic;
+        sync_pulse      : in std_logic;
         
         mem_addr        : out std_logic_vector(CONFIG_MEM_ADDR_WIDTH-1 downto 0);
         mem_ren         : out std_logic;
@@ -42,11 +42,11 @@ architecture arch of feedback_controller is
     constant inc : unsigned(CONFIG_MEM_ADDR_WIDTH-1 downto 0) := to_unsigned(1,CONFIG_MEM_ADDR_WIDTH);
     
     --*****SIGNAL DECLARATION*****
-    signal slot_nr, slot_nr_next : std_logic_vector(CONFIG_MEM_ADDR_WIDTH-1 downto 0) : (others => '0');
+    signal slot_nr, slot_nr_next : std_logic_vector(CONFIG_MEM_ADDR_WIDTH-1 downto 0) := (others => '0');
     signal timer : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0) := (others => '0');
-    signal sync_arrived : std_logic;
+    signal sync_pulse_arrived : std_logic;
     signal addsub_mode_next, addsub_mode_sig, add_input_mux_next, add_input_mux_sig : std_logic := '0';
-    signal delay_next, delay_sig : std_logic_vector(DELAY_WIDTH-1 downto 0); := (others => '0');
+    signal delay_next, delay_sig : std_logic_vector(DELAY_WIDTH-1 downto 0) := (others => '0');
     signal factor_next, factor_sig : std_logic_vector(FACTOR_WIDTH-1 downto 0) := (others => '0');
     
 begin
@@ -102,17 +102,17 @@ begin
         end if;
     end process;
     
-    timer : process(clk) 
+    timer_prc : process(clk) 
     begin
         if rising_edge(clk) then
             if (reset = '1') then
                 timer           <= (others => '0');
-                sync_arrived    <= '0';
+                sync_pulse_arrived  <= '0';
             else
-                if (sync_arrived = '0') then
+                if (sync_pulse_arrived = '0') then
                     -- Wait for rising edge of sync pulse
-                    if (sync = '1') then
+                    if (sync_pulse = '1') then
-                        sync_arrived    <= '1';
+                        sync_pulse_arrived  <= '1';
                     end if;
                 else
                     timer   <= std_logic_vector(unsigned(timer) + inc);

src/feedback_loop.vhd

@@ -36,6 +36,7 @@ entity feedback_loop is
         delay           : in std_logic_vector(DELAY_WIDTH-1 downto 0);  -- unsigned delay clock count
         factor          : in std_logic_vector(FACTOR_WIDTH-1 downto 0); -- 1Q3 Fixed Point
         -- DEBUG
+        reset_debug     : in std_logic;
         adc_data1_max   : out std_logic_vector(ADC_DATA_WIDTH-1 downto 0);
         adc_data2_max   : out std_logic_vector(ADC_DATA_WIDTH-1 downto 0);
         scaler_max      : out std_logic_vector(DAC_DATA_WIDTH-1 downto 0);
@@ -124,6 +125,7 @@ architecture arch of feedback_loop is
             );
             port (
                 clk         : in std_logic;
+                reset       : in std_logic;
                 delay       : in std_logic_vector(DELAY_WIDTH-1 downto 0);
                 data_in     : in std_logic_vector(DATA_WIDTH-1 downto 0);
                 data_out    : out std_logic_vector(DATA_WIDTH-1 downto 0)
@@ -131,10 +133,10 @@ architecture arch of feedback_loop is
     end component;
     
     --*****SIGNAL DECLARATION*****
-    signal delay_out, latch_out : std_logic_vector(ADC_DATA_WIDTH downto 0) := (others => '0');
+    signal delay_out : std_logic_vector(ADC_DATA_WIDTH downto 0) := (others => '0');
-    signal scaler_out, addsub_out, dac_max, scaler_max, inputA : std_logic_vector(DAC_DATA_WIDTH-1 downto 0) := (others => '0');
+    signal latch_out : std_logic_vector(ADC_DATA_WIDTH-1 downto 0) := (others => '0');
+    signal scaler_out, addsub_out, inputA : std_logic_vector(DAC_DATA_WIDTH-1 downto 0) := (others => '0');
     signal scaler_done, addsub_done : std_logic := '0';
-    signal adc_data1_max, adc_data2_max : std_logic_vector(ADC_DATA_WIDTH-1 downto 0) := (others => '0');
     
 begin
 
@@ -147,7 +149,7 @@ begin
         )
         port map(
             sclk    => clk,
-            reset   => areset,
+            reset   => reset,
             sdata1  => adc_data_in1,
             sdata2  => adc_data_in2,
             enable  => '1',
@@ -166,6 +168,7 @@ begin
         )
         port map(
             clk         => clk,
+            reset       => reset,
             delay       => delay,
             data_in     => (adc_done & adc_data1),
             data_out    => delay_out
@@ -211,7 +214,7 @@ begin
     
     mux: process(all)
     begin
-        if (input_mux = '1') then
+        if (add_input_mux = '1') then
             inputA  <= latch_out & "0000";
         else
             inputA  <= (others => '0');
@@ -227,7 +230,7 @@ begin
             clk     => clk,
             reset   => reset,
             mode    => addsub_mode,
-            cap     => input_mux,
+            cap     => add_input_mux,
             A       => inputA,
             B       => scaler_out,
             RES     => addsub_out

src/feedback_top.vhd

@@ -0,0 +1,265 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.typedef_package.all;
+
+
+entity feedback_top is
+    port (
+        --XILLYBUS
+        xillybus_clk    : in std_logic;
+        fifo_rd_data    : out std_logic_vector(DEBUG_FIFO_DATA_WIDTH-1 downto 0);
+        fifo_ren        : in std_logic;
+        fifo_empty      : out std_logic;
+        mem_addr        : in std_logic_vector(CONFIG_MEM_ADDR_WIDTH downto 0);
+        mem_wr_data     : in std_logic_vector(CONFIG_MEM_DATA_WIDTH-1 downto 0);
+        mem_wen         : in std_logic;
+        mem_full        : out std_logic;
+        --FPGA
+        clk_in          : in std_logic;
+        areset          : in std_logic;
+        areset_debug    : in std_logic;
+        async_pulse     : in std_logic;
+        astandby        : in std_logic;
+        adc_data_in1    : in std_logic;
+        adc_data_in2    : in std_logic;
+        adc_cs_n        : out std_logic;
+        adc_sclk        : out std_logic;
+        dac_data_out    : out std_logic;
+        dac_cs_n        : out std_logic;
+        dac_ldac        : out std_logic;
+        dac_sclk        : out std_logic
+    );
+end entity;
+
+architecture arch of feedback_top is
+    
+    --*****COMPONENT DECLARATION*****
+    component clockgen is
+        generic (
+            CLKFBOUT_MULT   : integer := 41;
+            CLKIN1_PERIOD   : real := 10.000000;
+            CLKOUT0_DIVIDE  : integer := 41;
+            DIVCLK_DIVIDE   : integer := 5
+        );
+        port (
+            clk_in  : in std_logic;
+            clk_out : out std_logic
+        );
+    end component;
+    
+    component synchronizer is
+        generic (
+            SYNC_STAGES : integer := 2
+        );
+        port (
+            clk     : in std_logic;
+            input   : in std_logic;
+            output  : out std_logic
+        );
+    end component;
+    
+    component feedback_loop is
+        port (
+            clk             : in std_logic;
+            reset           : in std_logic;
+            adc_data_in1    : in std_logic;
+            adc_data_in2    : in std_logic;
+            adc_cs_n        : out std_logic;
+            dac_data_out    : out std_logic;
+            dac_cs_n        : out std_logic;
+            dac_ldac        : out std_logic;
+            -- DYNAMIC CONFIGURATION
+            addsub_mode     : in std_logic;                                 -- (1=ADD, 0=SUB)
+            add_input_mux   : in std_logic;                                 -- (1=ADC Input 2, 0=GND)
+            delay           : in std_logic_vector(DELAY_WIDTH-1 downto 0);  -- unsigned delay clock count
+            factor          : in std_logic_vector(FACTOR_WIDTH-1 downto 0); -- 1Q3 Fixed Point
+            -- DEBUG
+            reset_debug     : in std_logic;
+            adc_data1_max   : out std_logic_vector(ADC_DATA_WIDTH-1 downto 0);
+            adc_data2_max   : out std_logic_vector(ADC_DATA_WIDTH-1 downto 0);
+            scaler_max      : out std_logic_vector(DAC_DATA_WIDTH-1 downto 0);
+            dac_max         : out std_logic_vector(DAC_DATA_WIDTH-1 downto 0)
+        );
+    end component;
+    
+    component feedback_controller is
+        port (
+            clk             : in std_logic;
+            reset           : in std_logic;
+            
+            sync_pulse      : in std_logic;
+            
+            mem_addr        : out std_logic_vector(CONFIG_MEM_ADDR_WIDTH-1 downto 0);
+            mem_ren         : out std_logic;
+            mem_data        : in std_logic_vector(CONFIG_DATA_WIDTH-1 downto 0);
+            
+            addsub_mode     : out std_logic;
+            add_input_mux   : out std_logic;
+            delay           : out std_logic_vector(DELAY_WIDTH-1 downto 0);
+            factor          : out std_logic_vector(FACTOR_WIDTH-1 downto 0)
+        );
+    end component;
+    
+    component xillybus_link is
+        generic (
+            DEBUG_SEND_INTERVAL : integer := 20000000
+        );
+        port (
+            --***XILLYBUS IF***
+            xillybus_clk    : in std_logic;
+            -- FIFO
+            fifo_rd_data    : out std_logic_vector(DEBUG_FIFO_DATA_WIDTH-1 downto 0);
+            fifo_ren        : in std_logic;
+            fifo_empty      : out std_logic;
+            -- RAM
+            mem_addr        : in std_logic_vector(CONFIG_MEM_ADDR_WIDTH downto 0);
+            mem_wr_data     : in std_logic_vector(CONFIG_MEM_DATA_WIDTH-1 downto 0);
+            mem_wen         : in std_logic;
+            --***FPGA IF***
+            fpga_clk        : in std_logic;
+            reset           : in std_logic;
+            -- Dynamic Configuration
+            config_addr     : in std_logic_vector(CONFIG_MEM_ADDR_WIDTH-1 downto 0);
+            config_ren      : in std_logic;
+            config_data     : out std_logic_vector(CONFIG_DATA_WIDTH-1 downto 0);
+            -- DEBUG
+            adc_data1_max   : in std_logic_vector(ADC_DATA_WIDTH-1 downto 0);
+            adc_data2_max   : in std_logic_vector(ADC_DATA_WIDTH-1 downto 0);
+            scaler_max      : in std_logic_vector(DAC_DATA_WIDTH-1 downto 0);
+            dac_max         : in std_logic_vector(DAC_DATA_WIDTH-1 downto 0)
+        );
+    end component;
+    
+    
+    
+    --*****SIGNAL DECLARATION*****
+    signal clk_20, reset, sync_pulse, standby, reset_debug : std_logic := '0';
+    signal addsub_mode, add_input_mux : std_logic := '0';
+    signal delay : std_logic_vector(DELAY_WIDTH-1 downto 0) := (others => '0');
+    signal factor : std_logic_vector(FACTOR_WIDTH-1 downto 0) := (others => '0');
+    signal adc_data1_max, adc_data2_max : std_logic_vector(ADC_DATA_WIDTH-1 downto 0) := (others => '0');
+    signal scaler_max, dac_max : std_logic_vector(DAC_DATA_WIDTH-1 downto 0) := (others => '0');
+    signal config_addr : std_logic_vector(CONFIG_MEM_ADDR_WIDTH-1 downto 0) := (others => '0');
+    signal config_ren : std_logic := '0';
+    signal config_data : std_logic_vector(CONFIG_DATA_WIDTH-1 downto 0) := (others => '0');
+    
+begin
+    
+    clockgen_inst : clockgen
+        generic map (
+            CLKFBOUT_MULT   => CLKFBOUT_MULT,
+            CLKIN1_PERIOD   => CLKIN1_PERIOD,
+            CLKOUT0_DIVIDE  => CLKOUT0_DIVIDE,
+            DIVCLK_DIVIDE   => DIVCLK_DIVIDE
+        )
+        port map(
+            clk_in  => clk_in,
+            clk_out => clk_20
+        );
+    
+    reset_sync : synchronizer
+        generic map (
+            SYNC_STAGES => SYNC_STAGES
+        )
+        port map (
+            clk     => clk_20,
+            input   => areset,
+            output  => reset
+        );
+    
+    sync_pulse_sync : synchronizer
+        generic map (
+            SYNC_STAGES => SYNC_STAGES
+        )
+        port map (
+            clk     => clk_20,
+            input   => async_pulse,
+            output  => sync_pulse
+        );
+    
+    standby_sync : synchronizer
+        generic map (
+            SYNC_STAGES => SYNC_STAGES
+        )
+        port map (
+            clk     => clk_20,
+            input   => astandby,
+            output  => standby
+        );
+    
+    reset_debug_sync : synchronizer
+        generic map (
+            SYNC_STAGES => SYNC_STAGES
+        )
+        port map (
+            clk     => clk_20,
+            input   => areset_debug,
+            output  => reset_debug
+        );
+    
+    feedback_loop_inst : feedback_loop
+        port map (
+            clk             => clk_20,
+            reset           => reset,
+            adc_data_in1    => adc_data_in1,
+            adc_data_in2    => adc_data_in2,
+            adc_cs_n        => adc_cs_n,
+            dac_data_out    => dac_data_out,
+            dac_cs_n        => dac_cs_n,
+            dac_ldac        => dac_ldac,
+            addsub_mode     => addsub_mode,
+            add_input_mux   => add_input_mux,
+            delay           => delay,
+            factor          => factor,
+            reset_debug     => reset_debug,
+            adc_data1_max   => adc_data1_max,
+            adc_data2_max   => adc_data2_max,
+            scaler_max      => scaler_max,
+            dac_max         => dac_max
+        );
+    
+    feedback_controller_inst : feedback_controller
+        port map (
+            clk             => clk_20,
+            reset           => reset or standby,
+            sync_pulse      => sync_pulse,
+            mem_addr        => config_addr,
+            mem_ren         => config_ren,
+            mem_data        => config_data,
+            addsub_mode     => addsub_mode,
+            add_input_mux   => add_input_mux,
+            delay           => delay,
+            factor          => factor
+        );
+    
+    xillybus_link_inst : xillybus_link
+        generic map (
+            DEBUG_SEND_INTERVAL => DEBUG_SEND_INTERVAL
+        )
+        port map (
+            xillybus_clk    => xillybus_clk,
+            fifo_rd_data    => fifo_rd_data,
+            fifo_ren        => fifo_ren,
+            fifo_empty      => fifo_empty,
+            mem_addr        => mem_addr,
+            mem_wr_data     => mem_wr_data,
+            mem_wen         => mem_wen,
+            fpga_clk        => clk_20,
+            reset           => reset,
+            config_addr     => config_addr,
+            config_ren      => config_ren,
+            config_data     => config_data,
+            adc_data1_max   => adc_data1_max,
+            adc_data2_max   => adc_data2_max,
+            scaler_max      => scaler_max,
+            dac_max         => dac_max
+        );
+    
+    -- Connect ADC and DAC to FPGA clock
+    adc_sclk    <= clk_20;
+    dac_sclk    <= clk_20;
+    -- Connect standy to mem_full signal, to prevent simutanuoys read/writing on memory
+    mem_full    <= not standby;
+end architecture;

src/scaler.vhd

@@ -43,8 +43,8 @@ begin
             A_WIDTH         => DATA_WIDTH,
             B_WIDTH         => FACTOR_WIDTH,
             PIPELINE_STAGES => PIPELINE_STAGES
-        );
+        )
-        port (
+        port map(
             clk => clk,
             A   => data_in,
             B   => factor,

src/single_port_ram.vhd

@@ -58,7 +58,7 @@ begin
             regcea          => '1',
             rsta            => '0',
             sleep           => '0',
-            wea             => wen
+            wea             => (others => wen) --1-bit Vector
         );
 
 end architecture;

src/synchronizer.vhd

@@ -0,0 +1,31 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity synchronizer is
+    generic (
+        SYNC_STAGES : integer := 2
+    );
+    port (
+        clk     : in std_logic;
+        input   : in std_logic;
+        output  : out std_logic
+    );
+end entity;
+
+architecture arch of synchronizer is
+    
+    --*****SIGNAl DECLARATION*****
+    signal sync_array : std_logic_vector(SYNC_STAGES-1 downto 0) := (others => '0');
+    
+begin
+
+    sync : process(clk)
+    begin
+        if rising_edge(clk) then
+            output      <= sync_array(SYNC_STAGES-1);
+            sync_array  <= sync_array(SYNC_STAGES-2 downto 0) & input;
+        end if;
+    end process;
+    
+end architecture;

src/top.xdc

@@ -1,4 +1,4 @@
-create_clock -period 10.000 -name sys_clk -waveform {0.000 5.000} [get_ports sys_clk]
+create_clock -period 10.000 -name sys_clk -waveform {0.000 5.000} [get_ports clk_in]
 create_clock -period 50.000 -name VIRTUAL_dac_sclk_OBUF -waveform {0.000 25.000}
 set_input_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -clock_fall -min -add_delay -10.000 [get_ports adc_data_in1]
 set_input_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -clock_fall -max -add_delay 10.000 [get_ports adc_data_in1]
@@ -9,8 +9,8 @@ set_output_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -max -add_delay 5.000
 set_output_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -min -add_delay -5.000 [get_ports dac_data_out]
 set_output_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -max -add_delay 10.000 [get_ports dac_data_out]
 
-set_property PACKAGE_PIN Y9 [get_ports sys_clk]
+set_property PACKAGE_PIN Y9 [get_ports clk_in]
-set_property IOSTANDARD LVCMOS33 [get_ports sys_clk]
+set_property IOSTANDARD LVCMOS33 [get_ports clk_in]
 
 set_property PACKAGE_PIN P16 [get_ports areset]
 set_property PACKAGE_PIN Y11 [get_ports adc_cs_n]

src/typedef_package.vhd

@@ -37,6 +37,10 @@ package typedef_package is
     constant CLKOUT0_DIVIDE  : integer := 41;
     constant DIVCLK_DIVIDE   : integer := 5;
     
+    constant SYNC_STAGES : integer := 2;
+    
+    constant DEBUG_SEND_INTERVAL : integer := 20000000;
+    
     --TODO: 3-stage sync to delay write-mode 1 clk cycle
     
     --*****FUNCTION DECLARATIONS*****

src/xillybus_link.vhd

@@ -53,8 +53,7 @@ architecture arch of xillybus_link is
     component dual_port_ram is
         generic (
             ADDR_WIDTH      : integer := 8;
-            DATA_WIDTH      : integer := 16;
+            DATA_WIDTH      : integer := 16
-            MEMORY_DEPTH    : integer := 20
         );
         port (
             wr_clk      : in std_logic;
@@ -72,8 +71,8 @@ architecture arch of xillybus_link is
         generic (
             DATA_WIDTH          : integer := 32;
             FIFO_DEPTH          : integer := 16;    -- (16 - 4194304)
-            PROG_EMPTY  : integer := 3;     -- MIN:3    MAX:(FIFO_DEPTH-3)
+            PROG_EMPTY_THRESH   : integer := 3;     -- MIN:3    MAX:(FIFO_DEPTH-3)
-            PROG_FULL   : integer := 13     -- MIN:3+CDC_SYNC_STAGES    MAX:(FIFO_DEPTH-3)
+            PROG_FULL_THRESH    : integer := 13     -- MIN:3+CDC_SYNC_STAGES    MAX:(FIFO_DEPTH-3)
         );
         port (
             wr_clk      : in std_logic;
@@ -97,7 +96,7 @@ architecture arch of xillybus_link is
     
     --*****SIGNAL DEFINITION*****
     signal cnt, cnt_next : integer range 0 to DEBUG_SEND_INTERVAL := 0;
-    signal stage : STAGE_TYPE := WAIT_COUNTER;
+    signal stage, stage_next : STAGE_TYPE := WAIT_COUNTER;
     signal fifo_almost_full, fifo_wen : std_logic := '0';
     signal fifo_wr_data : std_logic_vector(DEBUG_FIFO_DATA_WIDTH-1 downto 0) := (others => '0');
     
@@ -166,20 +165,20 @@ begin
         fifo_wen    <= '0';
         fifo_wr_data<= (others => '0');
         
-        case (stage)
+        case (stage) is
             when WAIT_COUNTER => 
                 if(cnt = DEBUG_SEND_INTERVAL) then
                     if(fifo_almost_full = '1') then
-                        stage_next => WAIT_FIFO;
+                        stage_next <= WAIT_FIFO;
                     else
-                        stage_next => SEND1;
+                        stage_next <= SEND1;
                     end if;
                 else
-                    cnt_next => cnt + 1;
+                    cnt_next    <= cnt + 1;
                 end if;
             when WAIT_FIFO =>
                 if(fifo_almost_full = '0') then
-                    stage_next => SEND1;
+                    stage_next  <= SEND1;
                 end if;
             when SEND1 =>
                 fifo_wen                    <= '1';

syn/labor-mst.xpr

@@ -62,13 +62,55 @@
   <FileSets Version="1" Minor="31">
     <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
       <Filter Type="Srcs"/>
-      <File Path="$PPRDIR/../src/clockgen.vhd">
+      <File Path="$PPRDIR/../src/addsub.vhd">
-        <FileInfo>
+        <FileInfo SFType="VHDL2008">
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PPRDIR/../src/open_loop.vhd">
+      <File Path="$PPRDIR/../src/async_fifo.vhd">
+        <FileInfo SFType="VHDL2008">
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../src/clockgen.vhd">
+        <FileInfo SFType="VHDL2008">
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../src/delay_line.vhd">
+        <FileInfo SFType="VHDL2008">
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../src/dual_port_ram.vhd">
+        <FileInfo SFType="VHDL2008">
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../src/typedef_package.vhd">
+        <FileInfo SFType="VHDL2008">
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../src/feedback_controller.vhd">
+        <FileInfo SFType="VHDL2008">
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../src/feedback_loop.vhd">
+        <FileInfo SFType="VHDL2008">
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../src/mult.vhd">
         <FileInfo SFType="VHDL2008">
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
@@ -86,16 +128,53 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PPRDIR/../src/scaler.vhd">
+        <FileInfo SFType="VHDL2008">
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../src/single_port_ram.vhd">
+        <FileInfo SFType="VHDL2008">
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../src/synchronizer.vhd">
+        <FileInfo SFType="VHDL2008">
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../src/xillybus_link.vhd">
+        <FileInfo SFType="VHDL2008">
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../src/feedback_top.vhd">
+        <FileInfo SFType="VHDL2008">
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../src/open_loop.vhd">
+        <FileInfo SFType="VHDL2008">
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <File Path="$PPRDIR/../src/top.vhd">
-        <FileInfo>
+        <FileInfo SFType="VHDL2008">
+          <Attr Name="AutoDisabled" Val="1"/>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="top"/>
+        <Option Name="TopModule" Val="feedback_top"/>
-        <Option Name="TopAutoSet" Val="TRUE"/>
       </Config>
     </FileSet>
     <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">