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* Added Xillybus demo project

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Greek 2020-04-26 11:42:06 +02:00
parent 779cd73e8d
commit 9818d0d27a
44 changed files with 13778 additions and 0 deletions
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xillinux-syn/.gitignore vendored Normal file
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#Ignore Directories
/vivado/**
/vivado-essentials/**
#Unignore Directories (Needed to unignore files in Subdirectories)
!*/
#WHITELIST
#Vivado Project File
!*.xpr
#Block Design
!*.bd
!system.v
!xillydemo.xdc
!showstopper.tcl
#Unignore .XCI Files (Only in First subdirectory)
!/vivado-essentials/*/*.xci
#Unignore Vivado IP Repo
!/vivado-essentials/vivado-ip/**

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xillinux-syn/bootfiles/boot.bin Normal file
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xillinux-syn/bootfiles/devicetree.dtb Normal file
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xillinux-syn/cores/xillybus_core.ngc Normal file
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xillinux-syn/cores/xillyvga_core.ngc Normal file
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xillinux-syn/system/data/ps7_system_prj.xml Normal file
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<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE project PUBLIC "project" "project.dtd" >
<project version="1.0" >
<set param="PCW::SD0::PERIPHERAL::ENABLE" value="1" />
<set param="PCW::UIPARAM::DDR::BL" value="8" />
<set param="PCW::UIPARAM::DDR::DRAM_WIDTH" value="16 Bits" />
<set param="PCW::UIPARAM::DDR::MEMORY_TYPE" value="DDR 3" />
<set param="PCW::GPIO::GPIO::IO" value="MIO" />
<set param="PCW::I2C0::PERIPHERAL::ENABLE" value="0" />
<set param="PCW::PRESET::GLOBAL::CONFIG" value="Default" />
<set param="PCW::UART1::PERIPHERAL::ENABLE" value="1" />
<set param="PCW::UART1::UART1::IO" value="MIO 48 .. 49" />
<set param="PCW::UART1::GRP_FULL::ENABLE" value="0" />
<set param="PCW::QSPI::PERIPHERAL::ENABLE" value="1" />
<set param="PCW::SD0::GRP_CD::ENABLE" value="1" />
<set param="PCW::SD0::GRP_WP::ENABLE" value="1" />
<set param="PCW::SD0::GRP_POW::ENABLE" value="0" />
<set param="PCW::SD0::GRP_CD::IO" value="MIO 47" />
<set param="PCW::SD0::GRP_WP::IO" value="MIO 46" />
<set param="PCW::TTC0::PERIPHERAL::ENABLE" value="1" />
<set param="PCW::TTC0::TTC0::IO" value="EMIO" />
<set param="PCW::ENET0::PERIPHERAL::ENABLE" value="1" />
<set param="PCW::ENET0::GRP_MDIO::ENABLE" value="1" />
<set param="PCW::ENET0::ENET0::IO" value="MIO 16 .. 27" />
<set param="PCW::ENET0::GRP_MDIO::IO" value="MIO 52 .. 53" />
<set param="PCW::USB0::PERIPHERAL::ENABLE" value="1" />
<set param="PCW::USB0::USB0::IO" value="MIO 28 .. 39" />
<set param="PCW::QSPI::QSPI::IO" value="MIO 1 .. 6" />
<set param="PCW::MIO::MIO[1]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[2]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[2]::IOTYPE" value="LVCMOS 3.3V" />
<set param="PCW::MIO::MIO[2]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[3]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[3]::IOTYPE" value="LVCMOS 3.3V" />
<set param="PCW::MIO::MIO[3]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[4]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[4]::IOTYPE" value="LVCMOS 3.3V" />
<set param="PCW::MIO::MIO[4]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[5]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[5]::IOTYPE" value="LVCMOS 3.3V" />
<set param="PCW::MIO::MIO[5]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[6]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[6]::IOTYPE" value="LVCMOS 3.3V" />
<set param="PCW::MIO::MIO[6]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[7]::SLEW" value="slow" />
<set param="PCW::MIO::MIO[7]::IOTYPE" value="LVCMOS 3.3V" />
<set param="PCW::MIO::MIO[7]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[8]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[8]::IOTYPE" value="LVCMOS 3.3V" />
<set param="PCW::MIO::MIO[8]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[9]::SLEW" value="slow" />
<set param="PCW::MIO::MIO[9]::IOTYPE" value="LVCMOS 3.3V" />
<set param="PCW::MIO::MIO[9]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[10]::SLEW" value="slow" />
<set param="PCW::MIO::MIO[10]::IOTYPE" value="LVCMOS 3.3V" />
<set param="PCW::MIO::MIO[10]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[11]::SLEW" value="slow" />
<set param="PCW::MIO::MIO[11]::IOTYPE" value="LVCMOS 3.3V" />
<set param="PCW::MIO::MIO[11]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[12]::SLEW" value="slow" />
<set param="PCW::MIO::MIO[12]::IOTYPE" value="LVCMOS 3.3V" />
<set param="PCW::MIO::MIO[12]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[13]::SLEW" value="slow" />
<set param="PCW::MIO::MIO[13]::IOTYPE" value="LVCMOS 3.3V" />
<set param="PCW::MIO::MIO[13]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[14]::SLEW" value="slow" />
<set param="PCW::MIO::MIO[14]::IOTYPE" value="LVCMOS 3.3V" />
<set param="PCW::MIO::MIO[14]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[15]::SLEW" value="slow" />
<set param="PCW::MIO::MIO[15]::IOTYPE" value="LVCMOS 3.3V" />
<set param="PCW::MIO::MIO[15]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[16]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[16]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[16]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[17]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[17]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[17]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[18]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[18]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[18]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[19]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[19]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[19]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[20]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[20]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[20]::PULLUP" value="disabled" />
<set param="PCW::PJTAG::PERIPHERAL::ENABLE" value="0" />
<set param="PCW::MIO::MIO[0]::SLEW" value="slow" />
<set param="PCW::MIO::MIO[0]::IOTYPE" value="LVCMOS 3.3V" />
<set param="PCW::GPIO::PERIPHERAL::ENABLE" value="1" />
<set param="PCW::MIO::MIO[0]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[1]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[1]::IOTYPE" value="LVCMOS 3.3V" />
<set param="PCW::UIPARAM::DDR::PARTNO" value="MT41J128M16 HA-15E" />
<set param="PCW::GPIO::EMIO_GPIO::ENABLE" value="1" />
<set param="PCW::GPIO::EMIO_GPIO::IO" value="56" />
<set param="PCW:GPIO::EMIO_GPIO::WIDTH" value="56" />
<set param="PCW::GPIO::V2.00.A::C_EN_EMIO_GPIO" value="1" />
<set param="PCW::PRESET::GLOBAL::DEFAULT" value="powerup" />
<set param="PCW::APU::PERIPHERAL::FREQMHZ" value="666.666667" />
<set param="PCW::FPGA0::PERIPHERAL::FREQMHZ" value="100.000000" />
<set param="PCW::FPGA1::PERIPHERAL::FREQMHZ" value="100.000000" />
<set param="PCW::FPGA2::PERIPHERAL::FREQMHZ" value="50.000000" />
<set param="PCW::UIPARAM::DDR::DEVICE_CAPACITY" value="2048 MBits" />
<set param="PCW::UIPARAM::DDR::SPEED_BIN" value="DDR3_1066F" />
<set param="PCW::UIPARAM::DDR::FREQ_MHZ" value="533.333313" />
<set param="PCW::UIPARAM::DDR::ROW_ADDR_COUNT" value="14" />
<set param="PCW::UIPARAM::DDR::CL" value="7" />
<set param="PCW::UIPARAM::DDR::CWL" value="6" />
<set param="PCW::UIPARAM::DDR::T_RCD" value="7" />
<set param="PCW::UIPARAM::DDR::T_RP" value="7" />
<set param="PCW::UIPARAM::DDR::T_RC" value="49.5" />
<set param="PCW::UIPARAM::DDR::T_RAS_MIN" value="36.0" />
<set param="PCW::UIPARAM::DDR::T_FAW" value="45.0" />
<set param="PCW::UIPARAM::DDR::DQS_TO_CLK_DELAY_0" value="0.025" />
<set param="PCW::UIPARAM::DDR::DQS_TO_CLK_DELAY_1" value="0.028" />
<set param="PCW::UIPARAM::DDR::DQS_TO_CLK_DELAY_2" value="-0.009" />
<set param="PCW::UIPARAM::DDR::DQS_TO_CLK_DELAY_3" value="-0.061" />
<set param="PCW::MIO::MIO[21]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[21]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[21]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[22]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[22]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[22]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[23]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[23]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::QSPI::PERIPHERAL::FREQMHZ" value="200.000000" />
<set param="PCW::ENET0::PERIPHERAL::FREQMHZ" value="1000 Mbps" />
<set param="PCW::SDIO::PERIPHERAL::FREQMHZ" value="50" />
<set param="PCW::UART::PERIPHERAL::FREQMHZ" value="50" />
<set param="PCW::CAN::PERIPHERAL::FREQMHZ" value="100" />
<set param="PCW::PRESET::FPGA::PARTNUMBER" value="xc7z020clg484-1" />
<set param="PCW::PRESET::FPGA::SPEED" value="-1" />
<set param="PCW::PRESET::BANK0::VOLTAGE" value="LVCMOS 3.3V" />
<set param="PCW::PRESET::BANK1::VOLTAGE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[23]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[24]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[24]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[24]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[25]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[25]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[25]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[26]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[26]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[26]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[27]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[27]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[27]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[28]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[28]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[28]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[29]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[29]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[29]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[30]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[30]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[30]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[31]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[31]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[31]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[32]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[32]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[32]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[33]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[33]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[33]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[34]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[34]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[34]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[35]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[35]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[35]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[36]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[36]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[36]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[37]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[37]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[37]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[38]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[38]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[38]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[39]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[39]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[39]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[40]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[40]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[40]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[41]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[41]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[41]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[42]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[42]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[42]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[43]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[43]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[43]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[44]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[44]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[44]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[45]::SLEW" value="fast" />
<set param="PCW::MIO::MIO[45]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[45]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[46]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[46]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[47]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[47]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[48]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[48]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[49]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[49]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[50]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[50]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[50]::DIRECTION" value="in" />
<set param="PCW::MIO::MIO[51]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[51]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[51]::DIRECTION" value="in" />
<set param="PCW::MIO::MIO[52]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[52]::PULLUP" value="disabled" />
<set param="PCW::MIO::MIO[53]::IOTYPE" value="LVCMOS 1.8V" />
<set param="PCW::MIO::MIO[53]::PULLUP" value="disabled" />
<set param="PCW::UIPARAM::DDR::TRAIN_WRITE_LEVEL" value="1" />
<set param="PCW::UIPARAM::DDR::TRAIN_READ_GATE" value="1" />
<set param="PCW::UIPARAM::DDR::TRAIN_DATA_EYE" value="1" />
<set param="PCW::UIPARAM::DDR::USE_INTERNAL_VREF" value="1" />
<set param="PCW::UIPARAM::DDR::BOARD_DELAY0" value="0.41" />
<set param="PCW::UIPARAM::DDR::BOARD_DELAY1" value="0.411" />
<set param="PCW::UIPARAM::DDR::BOARD_DELAY2" value="0.341" />
<set param="PCW::UIPARAM::DDR::BOARD_DELAY3" value="0.358" />
<set param="PCW::DDR::V4.00.A::C_S_AXI_HP0_BASEADDR" value="0x00000000" />
<set param="PCW::DDR::V4.00.A::C_S_AXI_HP0_HIGHADDR" value="0x1FFFFFFF" />
<set param="PCW::DDR::V4.00.A::C_S_AXI_HP1_BASEADDR" value="0x00000000" />
<set param="PCW::DDR::V4.00.A::C_S_AXI_HP1_HIGHADDR" value="0x1FFFFFFF" />
<set param="PCW::DDR::V4.00.A::C_S_AXI_HP2_BASEADDR" value="0x00000000" />
<set param="PCW::DDR::V4.00.A::C_S_AXI_HP2_HIGHADDR" value="0x1FFFFFFF" />
<set param="PCW::DDR::V4.00.A::C_S_AXI_HP3_BASEADDR" value="0x00000000" />
<set param="PCW::DDR::V4.00.A::C_S_AXI_HP3_HIGHADDR" value="0x1FFFFFFF" />
<set param="PCW::DDR::AXI_HP0::DATAWIDTH" value="64" />
<set param="PCW::DDR::AXI_HP2::DATAWIDTH" value="32" />
</project>

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FILES
xillybus_lite.ngc

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xillinux-syn/system/pcores/xillybus_lite_v1_00_a/data/xillybus_lite_v2_1_0.mpd Normal file
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BEGIN xillybus_lite
## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION HDL = VERILOG
OPTION STYLE = BLACKBOX
OPTION IP_GROUP = MICROBLAZE:USER
OPTION DESC = XILLYBUS_LITE
OPTION LONG_DESC = Xillybus Lite plain register interface
OPTION ARCH_SUPPORT_MAP = (spartan6t=PRODUCTION, spartan6=PRODUCTION, spartan6l=PRODUCTION, qspartan6t=PRODUCTION, qspartan6=PRODUCTION, aspartan6t=PRODUCTION, aspartan6=PRODUCTION, virtex6lx=PRODUCTION, virtex6sx=PRODUCTION, virtex6cx=PRODUCTION, virtex6llx=PRODUCTION, virtex6lsx=PRODUCTION, qspartan6l=PRODUCTION, qvirtex6lx=PRODUCTION, qvirtex6sx=PRODUCTION, qvirtex6fx=PRODUCTION, qvirtex6tx=PRODUCTION, virtex7=PRODUCTION, kintex7=PRODUCTION, artix7=PRODUCTION, zynq=PRODUCTION, virtex7l=PRODUCTION, kintex7l=PRODUCTION, aartix7=PRODUCTION, artix7l=PRODUCTION, virtex7ht=PRODUCTION, qvirtex7=PRODUCTION, qkintex7=PRODUCTION, qkintex7l=PRODUCTION, qartix7=PRODUCTION, qartix7l=PRODUCTION, azynq=PRODUCTION, qzynq=PRODUCTION, qvirtex7l=PRODUCTION)
## Bus Interfaces
BUS_INTERFACE BUS = S_AXI, BUS_STD = AXI, BUS_TYPE = SLAVE
## Generics for VHDL or Parameters for Verilog
PARAMETER C_S_AXI_DATA_WIDTH = 32, DT = INTEGER, BUS = S_AXI, ASSIGNMENT = CONSTANT, TYPE = NON_HDL
PARAMETER C_S_AXI_ADDR_WIDTH = 32, DT = INTEGER, BUS = S_AXI, ASSIGNMENT = CONSTANT, TYPE = NON_HDL
PARAMETER C_S_AXI_MIN_SIZE = 0x000001ff, DT = std_logic_vector, BUS = S_AXI, TYPE = NON_HDL
PARAMETER C_USE_WSTRB = 1, DT = INTEGER, ASSIGNMENT = CONSTANT, TYPE = NON_HDL
PARAMETER C_DPHASE_TIMEOUT = 8, DT = INTEGER, TYPE = NON_HDL
PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x100, PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = S_AXI, TYPE = NON_HDL
PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = S_AXI, TYPE = NON_HDL
PARAMETER C_SLV_AWIDTH = 32, DT = INTEGER, TYPE = NON_HDL
PARAMETER C_SLV_DWIDTH = 32, DT = INTEGER, TYPE = NON_HDL
PARAMETER C_MAX_BURST_LEN = 16, DT = INTEGER, ASSIGNMENT = CONSTANT, TYPE = NON_HDL
PARAMETER C_NATIVE_DATA_WIDTH = 32, DT = INTEGER, ASSIGNMENT = CONSTANT, TYPE = NON_HDL
PARAMETER C_S_AXI_PROTOCOL = AXI4LITE, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, DT = STRING, BUS = S_AXI
## Ports
PORT S_AXI_ACLK = "", DIR = I, SIGIS = CLK, BUS = S_AXI
PORT S_AXI_ARESETN = ARESETN, DIR = I, SIGIS = RST, BUS = S_AXI
PORT S_AXI_AWADDR = AWADDR, DIR = I, VEC = [31:0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_AWVALID = AWVALID, DIR = I, BUS = S_AXI
PORT S_AXI_WDATA = WDATA, DIR = I, VEC = [31:0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_WSTRB = WSTRB, DIR = I, VEC = [3:0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_WVALID = WVALID, DIR = I, BUS = S_AXI
PORT S_AXI_BREADY = BREADY, DIR = I, BUS = S_AXI
PORT S_AXI_ARADDR = ARADDR, DIR = I, VEC = [31:0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_ARVALID = ARVALID, DIR = I, BUS = S_AXI
PORT S_AXI_RREADY = RREADY, DIR = I, BUS = S_AXI
PORT S_AXI_ARREADY = ARREADY, DIR = O, BUS = S_AXI
PORT S_AXI_RDATA = RDATA, DIR = O, VEC = [31:0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_RRESP = RRESP, DIR = O, VEC = [1:0], BUS = S_AXI
PORT S_AXI_RVALID = RVALID, DIR = O, BUS = S_AXI
PORT S_AXI_WREADY = WREADY, DIR = O, BUS = S_AXI
PORT S_AXI_BRESP = BRESP, DIR = O, VEC = [1:0], BUS = S_AXI
PORT S_AXI_BVALID = BVALID, DIR = O, BUS = S_AXI
PORT S_AXI_AWREADY = AWREADY, DIR = O, BUS = S_AXI
PORT host_interrupt = "", DIR = O, INTERRUPT_PRIORITY = LOW, SIGIS = INTERRUPT, SENSITIVITY = EDGE_RISING
PORT user_clk = "", DIR = O
PORT user_wren = "", DIR = O
PORT user_wstrb = "", DIR = O, VEC = [3:0]
PORT user_rden = "", DIR = O
PORT user_rd_data = "", DIR = I, VEC = [31:0]
PORT user_wr_data = "", DIR = O, VEC = [31:0]
PORT user_addr = "", DIR = O, VEC = [31:0]
PORT user_irq = "", DIR = I
END

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###################################################################
##
## Name : xillybus
## Desc : Microprocessor Peripheral Description
## : Automatically generated by PsfUtility
##
###################################################################
BEGIN xillybus
## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VERILOG
OPTION IP_GROUP = MICROBLAZE:USER
OPTION DESC = XILLYBUS
OPTION LONG_DESC = Xillybus stub peripheral for AXI3 and AXI4
OPTION ARCH_SUPPORT_MAP = (spartan6t=PRODUCTION, spartan6=PRODUCTION, spartan6l=PRODUCTION, qspartan6t=PRODUCTION, qspartan6=PRODUCTION, aspartan6t=PRODUCTION, aspartan6=PRODUCTION, virtex6lx=PRODUCTION, virtex6sx=PRODUCTION, virtex6cx=PRODUCTION, virtex6llx=PRODUCTION, virtex6lsx=PRODUCTION, qspartan6l=PRODUCTION, qvirtex6lx=PRODUCTION, qvirtex6sx=PRODUCTION, qvirtex6fx=PRODUCTION, qvirtex6tx=PRODUCTION, virtex7=PRODUCTION, kintex7=PRODUCTION, artix7=PRODUCTION, zynq=PRODUCTION, virtex7l=PRODUCTION, kintex7l=PRODUCTION, aartix7=PRODUCTION, artix7l=PRODUCTION, virtex7ht=PRODUCTION, qvirtex7=PRODUCTION, qkintex7=PRODUCTION, qkintex7l=PRODUCTION, qartix7=PRODUCTION, qartix7l=PRODUCTION, azynq=PRODUCTION, qzynq=PRODUCTION, qvirtex7l=PRODUCTION)
## Bus Interfaces
BUS_INTERFACE BUS = M_AXI, BUS_STD = AXI, BUS_TYPE = MASTER
BUS_INTERFACE BUS = S_AXI, BUS_STD = AXI, BUS_TYPE = SLAVE
## Generics for VHDL or Parameters for Verilog
PARAMETER C_S_AXI_DATA_WIDTH = 32, DT = INTEGER, BUS = S_AXI, ASSIGNMENT = CONSTANT
PARAMETER C_S_AXI_ADDR_WIDTH = 32, DT = INTEGER, BUS = S_AXI, ASSIGNMENT = CONSTANT
PARAMETER C_S_AXI_MIN_SIZE = 0x000001ff, DT = std_logic_vector, BUS = S_AXI
PARAMETER C_USE_WSTRB = 1, DT = INTEGER, ASSIGNMENT = CONSTANT
PARAMETER C_DPHASE_TIMEOUT = 8, DT = INTEGER
PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x100, PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = S_AXI
PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = S_AXI
PARAMETER C_SLV_AWIDTH = 32, DT = INTEGER
PARAMETER C_SLV_DWIDTH = 64, DT = INTEGER
PARAMETER C_M_AXI_ADDR_WIDTH = 32, DT = INTEGER, BUS = M_AXI, ASSIGNMENT = CONSTANT
PARAMETER C_M_AXI_DATA_WIDTH = 64, DT = INTEGER, BUS = M_AXI, ASSIGNMENT = CONSTANT
PARAMETER C_MAX_BURST_LEN = 16, DT = INTEGER, ASSIGNMENT = CONSTANT
PARAMETER C_NATIVE_DATA_WIDTH = 64, DT = INTEGER, ASSIGNMENT = CONSTANT
PARAMETER C_M_AXI_PROTOCOL = AXI3, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, DT = STRING, BUS = M_AXI
PARAMETER C_S_AXI_PROTOCOL = AXI4LITE, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, DT = STRING, BUS = S_AXI
## Ports
PORT S_AXI_ACLK = "", DIR = I, SIGIS = CLK, BUS = S_AXI
PORT S_AXI_ARESETN = ARESETN, DIR = I, SIGIS = RST, BUS = S_AXI
PORT Interrupt = "", DIR = O, INTERRUPT_PRIORITY = LOW, SIGIS = INTERRUPT, SENSITIVITY = EDGE_RISING
PORT S_AXI_AWADDR = AWADDR, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_AWVALID = AWVALID, DIR = I, BUS = S_AXI
PORT S_AXI_WDATA = WDATA, DIR = I, VEC = [(C_S_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_WSTRB = WSTRB, DIR = I, VEC = [((C_S_AXI_DATA_WIDTH/8)-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_WVALID = WVALID, DIR = I, BUS = S_AXI
PORT S_AXI_BREADY = BREADY, DIR = I, BUS = S_AXI
PORT S_AXI_ARADDR = ARADDR, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_ARVALID = ARVALID, DIR = I, BUS = S_AXI
PORT S_AXI_RREADY = RREADY, DIR = I, BUS = S_AXI
PORT S_AXI_ARREADY = ARREADY, DIR = O, BUS = S_AXI
PORT S_AXI_RDATA = RDATA, DIR = O, VEC = [(C_S_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_RRESP = RRESP, DIR = O, VEC = [1:0], BUS = S_AXI
PORT S_AXI_RVALID = RVALID, DIR = O, BUS = S_AXI
PORT S_AXI_WREADY = WREADY, DIR = O, BUS = S_AXI
PORT S_AXI_BRESP = BRESP, DIR = O, VEC = [1:0], BUS = S_AXI
PORT S_AXI_BVALID = BVALID, DIR = O, BUS = S_AXI
PORT S_AXI_AWREADY = AWREADY, DIR = O, BUS = S_AXI
PORT m_axi_aclk = "", DIR = I, SIGIS = CLK, BUS = M_AXI
PORT m_axi_aresetn = ARESETN, DIR = I, SIGIS = RST, BUS = M_AXI
PORT m_axi_arready = ARREADY, DIR = I, BUS = M_AXI
PORT m_axi_arvalid = ARVALID, DIR = O, BUS = M_AXI
PORT m_axi_araddr = ARADDR, DIR = O, VEC = [(C_M_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = M_AXI
PORT m_axi_arlen = ARLEN, DIR = O, VEC = [3:0], BUS = M_AXI
PORT m_axi_arsize = ARSIZE, DIR = O, VEC = [2:0], BUS = M_AXI
PORT m_axi_arburst = ARBURST, DIR = O, VEC = [1:0], BUS = M_AXI
PORT m_axi_arprot = ARPROT, DIR = O, VEC = [2:0], BUS = M_AXI
PORT m_axi_arcache = ARCACHE, DIR = O, VEC = [3:0], BUS = M_AXI
PORT m_axi_rready = RREADY, DIR = O, BUS = M_AXI
PORT m_axi_rvalid = RVALID, DIR = I, BUS = M_AXI
PORT m_axi_rdata = RDATA, DIR = I, VEC = [(C_M_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = M_AXI
PORT m_axi_rresp = RRESP, DIR = I, VEC = [1:0], BUS = M_AXI
PORT m_axi_rlast = RLAST, DIR = I, BUS = M_AXI
PORT m_axi_awready = AWREADY, DIR = I, BUS = M_AXI
PORT m_axi_awvalid = AWVALID, DIR = O, BUS = M_AXI
PORT m_axi_awaddr = AWADDR, DIR = O, VEC = [(C_M_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = M_AXI
PORT m_axi_awlen = AWLEN, DIR = O, VEC = [3:0], BUS = M_AXI
PORT m_axi_awsize = AWSIZE, DIR = O, VEC = [2:0], BUS = M_AXI
PORT m_axi_awburst = AWBURST, DIR = O, VEC = [1:0], BUS = M_AXI
PORT m_axi_awprot = AWPROT, DIR = O, VEC = [2:0], BUS = M_AXI
PORT m_axi_awcache = AWCACHE, DIR = O, VEC = [3:0], BUS = M_AXI
PORT m_axi_wready = WREADY, DIR = I, BUS = M_AXI
PORT m_axi_wvalid = WVALID, DIR = O, BUS = M_AXI
PORT m_axi_wdata = WDATA, DIR = O, VEC = [(C_M_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = M_AXI
PORT m_axi_wstrb = WSTRB, DIR = O, VEC = [((C_M_AXI_DATA_WIDTH/8)-1):0], ENDIAN = LITTLE, BUS = M_AXI
PORT m_axi_wlast = WLAST, DIR = O, BUS = M_AXI
PORT m_axi_bready = BREADY, DIR = O, BUS = M_AXI
PORT m_axi_bvalid = BVALID, DIR = I, BUS = M_AXI
PORT m_axi_bresp = BRESP, DIR = I, VEC = [1:0], BUS = M_AXI
PORT xillybus_bus_clk = "", DIR = O
PORT xillybus_bus_rst_n = "", DIR = O
PORT xillybus_S_AXI_AWADDR = "", DIR = O, VEC = [(C_S_AXI_ADDR_WIDTH-1):0]
PORT xillybus_S_AXI_AWVALID = "", DIR = O
PORT xillybus_S_AXI_WDATA = "", DIR = O, VEC = [(C_S_AXI_DATA_WIDTH-1):0]
PORT xillybus_S_AXI_WSTRB = "", DIR = O, VEC = [((C_S_AXI_DATA_WIDTH/8)-1):0]
PORT xillybus_S_AXI_WVALID = "", DIR = O
PORT xillybus_S_AXI_BREADY = "", DIR = O
PORT xillybus_S_AXI_ARADDR = "", DIR = O, VEC = [(C_S_AXI_ADDR_WIDTH-1):0]
PORT xillybus_S_AXI_ARVALID = "", DIR = O
PORT xillybus_S_AXI_RREADY = "", DIR = O
PORT xillybus_S_AXI_ARREADY = "", DIR = I
PORT xillybus_S_AXI_RDATA = "", DIR = I, VEC = [(C_S_AXI_DATA_WIDTH-1):0]
PORT xillybus_S_AXI_RRESP = "", DIR = I, VEC = [1:0]
PORT xillybus_S_AXI_RVALID = "", DIR = I
PORT xillybus_S_AXI_WREADY = "", DIR = I
PORT xillybus_S_AXI_BRESP = "", DIR = I, VEC = [1:0]
PORT xillybus_S_AXI_BVALID = "", DIR = I
PORT xillybus_S_AXI_AWREADY = "", DIR = I
PORT xillybus_M_AXI_ARREADY = "", DIR = O
PORT xillybus_M_AXI_ARVALID = "", DIR = I
PORT xillybus_M_AXI_ARADDR = "", DIR = I, VEC = [(C_M_AXI_ADDR_WIDTH-1):0]
PORT xillybus_M_AXI_ARLEN = "", DIR = I, VEC = [3:0]
PORT xillybus_M_AXI_ARSIZE = "", DIR = I, VEC = [2:0]
PORT xillybus_M_AXI_ARBURST = "", DIR = I, VEC = [1:0]
PORT xillybus_M_AXI_ARPROT = "", DIR = I, VEC = [2:0]
PORT xillybus_M_AXI_ARCACHE = "", DIR = I, VEC = [3:0]
PORT xillybus_M_AXI_RREADY = "", DIR = I
PORT xillybus_M_AXI_RVALID = "", DIR = O
PORT xillybus_M_AXI_RDATA = "", DIR = O, VEC = [(C_M_AXI_DATA_WIDTH-1):0]
PORT xillybus_M_AXI_RRESP = "", DIR = O, VEC = [1:0]
PORT xillybus_M_AXI_RLAST = "", DIR = O
PORT xillybus_M_AXI_AWREADY = "", DIR = O
PORT xillybus_M_AXI_AWVALID = "", DIR = I
PORT xillybus_M_AXI_AWADDR = "", DIR = I, VEC = [(C_M_AXI_ADDR_WIDTH-1):0]
PORT xillybus_M_AXI_AWLEN = "", DIR = I, VEC = [3:0]
PORT xillybus_M_AXI_AWSIZE = "", DIR = I, VEC = [2:0]
PORT xillybus_M_AXI_AWBURST = "", DIR = I, VEC = [1:0]
PORT xillybus_M_AXI_AWPROT = "", DIR = I, VEC = [2:0]
PORT xillybus_M_AXI_AWCACHE = "", DIR = I, VEC = [3:0]
PORT xillybus_M_AXI_WREADY = "", DIR = O
PORT xillybus_M_AXI_WVALID = "", DIR = I
PORT xillybus_M_AXI_WDATA = "", DIR = I, VEC = [(C_M_AXI_DATA_WIDTH-1):0]
PORT xillybus_M_AXI_WSTRB = "", DIR = I, VEC = [((C_M_AXI_DATA_WIDTH/8)-1):0]
PORT xillybus_M_AXI_WLAST = "", DIR = I
PORT xillybus_M_AXI_BREADY = "", DIR = I
PORT xillybus_M_AXI_BVALID = "", DIR = O
PORT xillybus_M_AXI_BRESP = "", DIR = O, VEC = [1:0]
PORT xillybus_host_interrupt = "", DIR = I
END

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lib xillybus_v1_00_a xillybus verilog

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module xillybus #(
parameter C_S_AXI_DATA_WIDTH = 32,
parameter C_S_AXI_ADDR_WIDTH = 32,
parameter C_M_AXI_ADDR_WIDTH = 32,
parameter C_M_AXI_DATA_WIDTH = 64,
parameter C_S_AXI_MIN_SIZE = 32'h000001ff,
parameter C_USE_WSTRB = 1,
parameter C_DPHASE_TIMEOUT = 8,
parameter C_BASEADDR = 32'h79c00000,
parameter C_HIGHADDR = 32'h79c0ffff,
parameter C_SLV_AWIDTH = 32,
parameter C_SLV_DWIDTH = 64,
parameter C_MAX_BURST_LEN = 256,
parameter C_NATIVE_DATA_WIDTH = 64
)
(
input S_AXI_ACLK,
input S_AXI_ARESETN,
output Interrupt,
input [(C_S_AXI_ADDR_WIDTH-1):0] S_AXI_AWADDR,
input S_AXI_AWVALID,
input [(C_S_AXI_DATA_WIDTH-1):0] S_AXI_WDATA,
input [((C_S_AXI_DATA_WIDTH/8)-1):0] S_AXI_WSTRB,
input S_AXI_WVALID,
input S_AXI_BREADY,
input [(C_S_AXI_ADDR_WIDTH-1):0] S_AXI_ARADDR,
input S_AXI_ARVALID,
input S_AXI_RREADY,
output S_AXI_ARREADY,
output [(C_S_AXI_DATA_WIDTH-1):0] S_AXI_RDATA,
output [1:0] S_AXI_RRESP,
output S_AXI_RVALID,
output S_AXI_WREADY,
output [1:0] S_AXI_BRESP,
output S_AXI_BVALID,
output S_AXI_AWREADY,
input m_axi_aclk,
input m_axi_aresetn,
input m_axi_arready,
output m_axi_arvalid,
output [(C_M_AXI_ADDR_WIDTH-1):0] m_axi_araddr,
output [3:0] m_axi_arlen,
output [2:0] m_axi_arsize,
output [1:0] m_axi_arburst,
output [2:0] m_axi_arprot,
output [3:0] m_axi_arcache,
output m_axi_rready,
input m_axi_rvalid,
input [(C_M_AXI_DATA_WIDTH-1):0] m_axi_rdata,
input [1:0] m_axi_rresp,
input m_axi_rlast,
input m_axi_awready,
output m_axi_awvalid,
output [(C_M_AXI_ADDR_WIDTH-1):0] m_axi_awaddr,
output [3:0] m_axi_awlen,
output [2:0] m_axi_awsize,
output [1:0] m_axi_awburst,
output [2:0] m_axi_awprot,
output [3:0] m_axi_awcache,
input m_axi_wready,
output m_axi_wvalid,
output [(C_M_AXI_DATA_WIDTH-1):0] m_axi_wdata,
output [((C_M_AXI_DATA_WIDTH/8)-1):0] m_axi_wstrb,
output m_axi_wlast,
output m_axi_bready,
input m_axi_bvalid,
input [1:0] m_axi_bresp,
output xillybus_bus_clk,
output reg xillybus_bus_rst_n,
output [(C_S_AXI_ADDR_WIDTH-1):0] xillybus_S_AXI_AWADDR,
output xillybus_S_AXI_AWVALID,
output [(C_S_AXI_DATA_WIDTH-1):0] xillybus_S_AXI_WDATA,
output [((C_S_AXI_DATA_WIDTH/8)-1):0] xillybus_S_AXI_WSTRB,
output xillybus_S_AXI_WVALID,
output xillybus_S_AXI_BREADY,
output [(C_S_AXI_ADDR_WIDTH-1):0] xillybus_S_AXI_ARADDR,
output xillybus_S_AXI_ARVALID,
output xillybus_S_AXI_RREADY,
input xillybus_S_AXI_ARREADY,
input [(C_S_AXI_DATA_WIDTH-1):0] xillybus_S_AXI_RDATA,
input [1:0] xillybus_S_AXI_RRESP,
input xillybus_S_AXI_RVALID,
input xillybus_S_AXI_WREADY,
input [1:0] xillybus_S_AXI_BRESP,
input xillybus_S_AXI_BVALID,
input xillybus_S_AXI_AWREADY,
output xillybus_M_AXI_ARREADY,
input xillybus_M_AXI_ARVALID,
input [(C_M_AXI_ADDR_WIDTH-1):0] xillybus_M_AXI_ARADDR,
input [3:0] xillybus_M_AXI_ARLEN,
input [2:0] xillybus_M_AXI_ARSIZE,
input [1:0] xillybus_M_AXI_ARBURST,
input [2:0] xillybus_M_AXI_ARPROT,
input [3:0] xillybus_M_AXI_ARCACHE,
input xillybus_M_AXI_RREADY,
output xillybus_M_AXI_RVALID,
output [(C_M_AXI_DATA_WIDTH-1):0] xillybus_M_AXI_RDATA,
output [1:0] xillybus_M_AXI_RRESP,
output xillybus_M_AXI_RLAST,
output xillybus_M_AXI_AWREADY,
input xillybus_M_AXI_AWVALID,
input [(C_M_AXI_ADDR_WIDTH-1):0] xillybus_M_AXI_AWADDR,
input [3:0] xillybus_M_AXI_AWLEN,
input [2:0] xillybus_M_AXI_AWSIZE,
input [1:0] xillybus_M_AXI_AWBURST,
input [2:0] xillybus_M_AXI_AWPROT,
input [3:0] xillybus_M_AXI_AWCACHE,
output xillybus_M_AXI_WREADY,
input xillybus_M_AXI_WVALID,
input [(C_M_AXI_DATA_WIDTH-1):0] xillybus_M_AXI_WDATA,
input [((C_M_AXI_DATA_WIDTH/8)-1):0] xillybus_M_AXI_WSTRB,
input xillybus_M_AXI_WLAST,
input xillybus_M_AXI_BREADY,
output xillybus_M_AXI_BVALID,
output [1:0] xillybus_M_AXI_BRESP,
input xillybus_host_interrupt
);
reg rst_sync;
// S_AXI_ARESETN is possibly completely asyncronous to anything, while
// bus_rst is expected to be synchronous w.r.t. to bus_clk. So it's synced.
always @(posedge S_AXI_ACLK)
begin
xillybus_bus_rst_n <= rst_sync;
rst_sync <= S_AXI_ARESETN;
end
// This module merely connects the AXI signals to the Xillybus core, which
// is external to the processor. This makes it possible to swap the Xillybus
// core without reimplementing the processor.
assign xillybus_bus_clk = S_AXI_ACLK ;
assign xillybus_S_AXI_AWADDR = S_AXI_AWADDR ;
assign xillybus_S_AXI_AWVALID = S_AXI_AWVALID ;
assign xillybus_S_AXI_WDATA = S_AXI_WDATA ;
assign xillybus_S_AXI_WSTRB = S_AXI_WSTRB ;
assign xillybus_S_AXI_WVALID = S_AXI_WVALID ;
assign xillybus_S_AXI_BREADY = S_AXI_BREADY ;
assign xillybus_S_AXI_ARADDR = S_AXI_ARADDR ;
assign xillybus_S_AXI_ARVALID = S_AXI_ARVALID ;
assign xillybus_S_AXI_RREADY = S_AXI_RREADY ;
assign S_AXI_ARREADY = xillybus_S_AXI_ARREADY ;
assign S_AXI_RDATA = xillybus_S_AXI_RDATA ;
assign S_AXI_RRESP = xillybus_S_AXI_RRESP ;
assign S_AXI_RVALID = xillybus_S_AXI_RVALID ;
assign S_AXI_WREADY = xillybus_S_AXI_WREADY ;
assign S_AXI_BRESP = xillybus_S_AXI_BRESP ;
assign S_AXI_BVALID = xillybus_S_AXI_BVALID ;
assign S_AXI_AWREADY = xillybus_S_AXI_AWREADY ;
assign xillybus_M_AXI_ACLK = m_axi_aclk ;
assign xillybus_M_AXI_ARESETN = m_axi_aresetn ;
assign xillybus_M_AXI_ARREADY = m_axi_arready ;
assign m_axi_arvalid = xillybus_M_AXI_ARVALID ;
assign m_axi_araddr = xillybus_M_AXI_ARADDR ;
assign m_axi_arlen = xillybus_M_AXI_ARLEN ;
assign m_axi_arsize = xillybus_M_AXI_ARSIZE ;
assign m_axi_arburst = xillybus_M_AXI_ARBURST ;
assign m_axi_arprot = xillybus_M_AXI_ARPROT ;
assign m_axi_arcache = xillybus_M_AXI_ARCACHE ;
assign m_axi_rready = xillybus_M_AXI_RREADY ;
assign xillybus_M_AXI_RVALID = m_axi_rvalid ;
assign xillybus_M_AXI_RDATA = m_axi_rdata ;
assign xillybus_M_AXI_RRESP = m_axi_rresp ;
assign xillybus_M_AXI_RLAST = m_axi_rlast ;
assign xillybus_M_AXI_AWREADY = m_axi_awready ;
assign m_axi_awvalid = xillybus_M_AXI_AWVALID ;
assign m_axi_awaddr = xillybus_M_AXI_AWADDR ;
assign m_axi_awlen = xillybus_M_AXI_AWLEN ;
assign m_axi_awsize = xillybus_M_AXI_AWSIZE ;
assign m_axi_awburst = xillybus_M_AXI_AWBURST ;
assign m_axi_awprot = xillybus_M_AXI_AWPROT ;
assign m_axi_awcache = xillybus_M_AXI_AWCACHE ;
assign xillybus_M_AXI_WREADY = m_axi_wready ;
assign m_axi_wvalid = xillybus_M_AXI_WVALID ;
assign m_axi_wdata = xillybus_M_AXI_WDATA ;
assign m_axi_wstrb = xillybus_M_AXI_WSTRB ;
assign m_axi_wlast = xillybus_M_AXI_WLAST ;
assign m_axi_bready = xillybus_M_AXI_BREADY ;
assign xillybus_M_AXI_BVALID = m_axi_bvalid ;
assign xillybus_M_AXI_BRESP = m_axi_bresp ;
assign Interrupt = xillybus_host_interrupt;
endmodule

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BEGIN xillyvga
## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VERILOG
OPTION IP_GROUP = MICROBLAZE:USER
OPTION DESC = XILLYVGA
OPTION LONG_DESC = Xillyvga frame buffer VGA/DVI core
OPTION ARCH_SUPPORT_MAP = (spartan6t=PRODUCTION, spartan6=PRODUCTION, spartan6l=PRODUCTION, qspartan6t=PRODUCTION, qspartan6=PRODUCTION, aspartan6t=PRODUCTION, aspartan6=PRODUCTION, virtex6lx=PRODUCTION, virtex6sx=PRODUCTION, virtex6cx=PRODUCTION, virtex6llx=PRODUCTION, virtex6lsx=PRODUCTION, qspartan6l=PRODUCTION, qvirtex6lx=PRODUCTION, qvirtex6sx=PRODUCTION, qvirtex6fx=PRODUCTION, qvirtex6tx=PRODUCTION, virtex7=PRODUCTION, kintex7=PRODUCTION, artix7=PRODUCTION, zynq=PRODUCTION, virtex7l=PRODUCTION, kintex7l=PRODUCTION, aartix7=PRODUCTION, artix7l=PRODUCTION, virtex7ht=PRODUCTION, qvirtex7=PRODUCTION, qkintex7=PRODUCTION, qkintex7l=PRODUCTION, qartix7=PRODUCTION, qartix7l=PRODUCTION, azynq=PRODUCTION, qzynq=PRODUCTION, qvirtex7l=PRODUCTION)
## Bus Interfaces
BUS_INTERFACE BUS = M_AXI, BUS_STD = AXI, BUS_TYPE = MASTER
BUS_INTERFACE BUS = S_AXI, BUS_STD = AXI, BUS_TYPE = SLAVE
## Generics for VHDL or Parameters for Verilog
PARAMETER C_S_AXI_DATA_WIDTH = 32, DT = INTEGER, BUS = S_AXI, ASSIGNMENT = CONSTANT
PARAMETER C_S_AXI_ADDR_WIDTH = 32, DT = INTEGER, BUS = S_AXI, ASSIGNMENT = CONSTANT
PARAMETER C_S_AXI_MIN_SIZE = 0x000001ff, DT = std_logic_vector, BUS = S_AXI
PARAMETER C_USE_WSTRB = 1, DT = INTEGER, ASSIGNMENT = CONSTANT
PARAMETER C_DPHASE_TIMEOUT = 8, DT = INTEGER
PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x100, PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = S_AXI
PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = S_AXI
PARAMETER C_SLV_AWIDTH = 32, DT = INTEGER
PARAMETER C_SLV_DWIDTH = 32, DT = INTEGER
PARAMETER C_M_AXI_ADDR_WIDTH = 32, DT = INTEGER, BUS = M_AXI, ASSIGNMENT = CONSTANT
PARAMETER C_M_AXI_DATA_WIDTH = 32, DT = INTEGER, BUS = M_AXI, ASSIGNMENT = CONSTANT
PARAMETER C_MAX_BURST_LEN = 16, DT = INTEGER, ASSIGNMENT = CONSTANT
PARAMETER C_NATIVE_DATA_WIDTH = 32, DT = INTEGER, ASSIGNMENT = CONSTANT
PARAMETER C_M_AXI_PROTOCOL = AXI3, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, DT = STRING, BUS = M_AXI
PARAMETER C_S_AXI_PROTOCOL = AXI4LITE, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, DT = STRING, BUS = S_AXI
## Ports
PORT S_AXI_ACLK = "", DIR = I, SIGIS = CLK, BUS = S_AXI
PORT S_AXI_ARESETN = ARESETN, DIR = I, SIGIS = RST, BUS = S_AXI
PORT S_AXI_AWADDR = AWADDR, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_AWVALID = AWVALID, DIR = I, BUS = S_AXI
PORT S_AXI_WDATA = WDATA, DIR = I, VEC = [(C_S_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_WSTRB = WSTRB, DIR = I, VEC = [((C_S_AXI_DATA_WIDTH/8)-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_WVALID = WVALID, DIR = I, BUS = S_AXI
PORT S_AXI_BREADY = BREADY, DIR = I, BUS = S_AXI
PORT S_AXI_ARADDR = ARADDR, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_ARVALID = ARVALID, DIR = I, BUS = S_AXI
PORT S_AXI_RREADY = RREADY, DIR = I, BUS = S_AXI
PORT S_AXI_ARREADY = ARREADY, DIR = O, BUS = S_AXI
PORT S_AXI_RDATA = RDATA, DIR = O, VEC = [(C_S_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_RRESP = RRESP, DIR = O, VEC = [1:0], BUS = S_AXI
PORT S_AXI_RVALID = RVALID, DIR = O, BUS = S_AXI
PORT S_AXI_WREADY = WREADY, DIR = O, BUS = S_AXI
PORT S_AXI_BRESP = BRESP, DIR = O, VEC = [1:0], BUS = S_AXI
PORT S_AXI_BVALID = BVALID, DIR = O, BUS = S_AXI
PORT S_AXI_AWREADY = AWREADY, DIR = O, BUS = S_AXI
PORT m_axi_aclk = "", DIR = I, SIGIS = CLK, BUS = M_AXI
PORT m_axi_aresetn = ARESETN, DIR = I, SIGIS = RST, BUS = M_AXI
PORT m_axi_arready = ARREADY, DIR = I, BUS = M_AXI
PORT m_axi_arvalid = ARVALID, DIR = O, BUS = M_AXI
PORT m_axi_araddr = ARADDR, DIR = O, VEC = [(C_M_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = M_AXI
PORT m_axi_arlen = ARLEN, DIR = O, VEC = [3:0], BUS = M_AXI
PORT m_axi_arsize = ARSIZE, DIR = O, VEC = [2:0], BUS = M_AXI
PORT m_axi_arburst = ARBURST, DIR = O, VEC = [1:0], BUS = M_AXI
PORT m_axi_arprot = ARPROT, DIR = O, VEC = [2:0], BUS = M_AXI
PORT m_axi_arcache = ARCACHE, DIR = O, VEC = [3:0], BUS = M_AXI
PORT m_axi_rready = RREADY, DIR = O, BUS = M_AXI
PORT m_axi_rvalid = RVALID, DIR = I, BUS = M_AXI
PORT m_axi_rdata = RDATA, DIR = I, VEC = [(C_M_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = M_AXI
PORT m_axi_rresp = RRESP, DIR = I, VEC = [1:0], BUS = M_AXI
PORT m_axi_rlast = RLAST, DIR = I, BUS = M_AXI
PORT m_axi_awready = AWREADY, DIR = I, BUS = M_AXI
PORT m_axi_awvalid = AWVALID, DIR = O, BUS = M_AXI
PORT m_axi_awaddr = AWADDR, DIR = O, VEC = [(C_M_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = M_AXI
PORT m_axi_awlen = AWLEN, DIR = O, VEC = [3:0], BUS = M_AXI
PORT m_axi_awsize = AWSIZE, DIR = O, VEC = [2:0], BUS = M_AXI
PORT m_axi_awburst = AWBURST, DIR = O, VEC = [1:0], BUS = M_AXI
PORT m_axi_awprot = AWPROT, DIR = O, VEC = [2:0], BUS = M_AXI
PORT m_axi_awcache = AWCACHE, DIR = O, VEC = [3:0], BUS = M_AXI
PORT m_axi_wready = WREADY, DIR = I, BUS = M_AXI
PORT m_axi_wvalid = WVALID, DIR = O, BUS = M_AXI
PORT m_axi_wdata = WDATA, DIR = O, VEC = [(C_M_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = M_AXI
PORT m_axi_wstrb = WSTRB, DIR = O, VEC = [((C_M_AXI_DATA_WIDTH/8)-1):0], ENDIAN = LITTLE, BUS = M_AXI
PORT m_axi_wlast = WLAST, DIR = O, BUS = M_AXI
PORT m_axi_bready = BREADY, DIR = O, BUS = M_AXI
PORT m_axi_bvalid = BVALID, DIR = I, BUS = M_AXI
PORT m_axi_bresp = BRESP, DIR = I, VEC = [1:0], BUS = M_AXI
PORT clk_in = "", DIR = I
PORT vga_clk = "", DIR = O
PORT vga_hsync = "", DIR = O
PORT vga_vsync = "", DIR = O
PORT vga_de = "", DIR = O
PORT vga_red = "", DIR = O, VEC = [7:0]
PORT vga_green = "", DIR = O, VEC = [7:0]
PORT vga_blue = "", DIR = O, VEC = [7:0]
END

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lib xillyvga_v1_00_a xillyvga verilog
lib xillyvga_v1_00_a xillyvga_core verilog

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module xillyvga #(
parameter C_S_AXI_DATA_WIDTH = 32,
parameter C_S_AXI_ADDR_WIDTH = 32,
parameter C_M_AXI_ADDR_WIDTH = 32,
parameter C_M_AXI_DATA_WIDTH = 32,
parameter C_S_AXI_MIN_SIZE = 32'h000001ff,
parameter C_USE_WSTRB = 1,
parameter C_DPHASE_TIMEOUT = 8,
parameter C_BASEADDR = 32'h79c00000,
parameter C_HIGHADDR = 32'h79c0ffff,
parameter C_SLV_AWIDTH = 32,
parameter C_SLV_DWIDTH = 32,
parameter C_MAX_BURST_LEN = 256,
parameter C_NATIVE_DATA_WIDTH = 32
)
(
input S_AXI_ACLK,
input [31:0] S_AXI_ARADDR,
input S_AXI_ARESETN,
input S_AXI_ARVALID,
input [31:0] S_AXI_AWADDR,
input S_AXI_AWVALID,
input S_AXI_BREADY,
input S_AXI_RREADY,
input [31:0] S_AXI_WDATA,
input [3:0] S_AXI_WSTRB,
input S_AXI_WVALID,
input clk_in,
input m_axi_aclk,
input m_axi_aresetn,
input m_axi_arready,
input m_axi_awready,
input [1:0] m_axi_bresp,
input m_axi_bvalid,
input [31:0] m_axi_rdata,
input m_axi_rlast,
input [1:0] m_axi_rresp,
input m_axi_rvalid,
input m_axi_wready,
output S_AXI_ARREADY,
output S_AXI_AWREADY,
output [1:0] S_AXI_BRESP,
output S_AXI_BVALID,
output [31:0] S_AXI_RDATA,
output [1:0] S_AXI_RRESP,
output S_AXI_RVALID,
output S_AXI_WREADY,
output [31:0] m_axi_araddr,
output [1:0] m_axi_arburst,
output [3:0] m_axi_arcache,
output [3:0] m_axi_arlen,
output [2:0] m_axi_arprot,
output [2:0] m_axi_arsize,
output m_axi_arvalid,
output [31:0] m_axi_awaddr,
output [1:0] m_axi_awburst,
output [3:0] m_axi_awcache,
output [3:0] m_axi_awlen,
output [2:0] m_axi_awprot,
output [2:0] m_axi_awsize,
output m_axi_awvalid,
output m_axi_bready,
output m_axi_rready,
output [31:0] m_axi_wdata,
output m_axi_wlast,
output [3:0] m_axi_wstrb,
output m_axi_wvalid,
output vga_clk,
output [7:0] vga_blue,
output [7:0] vga_green,
output vga_hsync,
output [7:0] vga_red,
output vga_vsync,
output vga_de
);
xillyvga_core xillyvga_core_ins (
.S_AXI_ACLK(S_AXI_ACLK),
.S_AXI_ARADDR(S_AXI_ARADDR),
.S_AXI_ARESETN(S_AXI_ARESETN),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_AWADDR(S_AXI_AWADDR),
.S_AXI_AWVALID(S_AXI_AWVALID),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_RREADY(S_AXI_RREADY),
.S_AXI_WDATA(S_AXI_WDATA),
.S_AXI_WSTRB(S_AXI_WSTRB),
.S_AXI_WVALID(S_AXI_WVALID),
.clk_in(clk_in),
.m_axi_aclk(m_axi_aclk),
.m_axi_aresetn(m_axi_aresetn),
.m_axi_arready(m_axi_arready),
.m_axi_awready(m_axi_awready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rlast(m_axi_rlast),
.m_axi_rresp(m_axi_rresp),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wready(m_axi_wready),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_AWREADY(S_AXI_AWREADY),
.S_AXI_BRESP(S_AXI_BRESP),
.S_AXI_BVALID(S_AXI_BVALID),
.S_AXI_RDATA(S_AXI_RDATA),
.S_AXI_RRESP(S_AXI_RRESP),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_WREADY(S_AXI_WREADY),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(m_axi_arburst),
.m_axi_arcache(m_axi_arcache),
.m_axi_arlen(m_axi_arlen),
.m_axi_arprot(m_axi_arprot),
.m_axi_arsize(m_axi_arsize),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(m_axi_awburst),
.m_axi_awcache(m_axi_awcache),
.m_axi_awlen(m_axi_awlen),
.m_axi_awprot(m_axi_awprot),
.m_axi_awsize(m_axi_awsize),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bready(m_axi_bready),
.m_axi_rready(m_axi_rready),
.m_axi_wdata(m_axi_wdata),
.m_axi_wlast(m_axi_wlast),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wvalid(m_axi_wvalid),
.vga_clk(vga_clk),
.vga_blue(vga_blue),
.vga_green(vga_green),
.vga_hsync(vga_hsync),
.vga_red(vga_red),
.vga_vsync(vga_vsync),
.vga_de(vga_de)
);
endmodule

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module xillyvga_core
(
input S_AXI_ACLK,
input [31:0] S_AXI_ARADDR,
input S_AXI_ARESETN,
input S_AXI_ARVALID,
input [31:0] S_AXI_AWADDR,
input S_AXI_AWVALID,
input S_AXI_BREADY,
input S_AXI_RREADY,
input [31:0] S_AXI_WDATA,
input [3:0] S_AXI_WSTRB,
input S_AXI_WVALID,
input clk_in,
input m_axi_aclk,
input m_axi_aresetn,
input m_axi_arready,
input m_axi_awready,
input [1:0] m_axi_bresp,
input m_axi_bvalid,
input [31:0] m_axi_rdata,
input m_axi_rlast,
input [1:0] m_axi_rresp,
input m_axi_rvalid,
input m_axi_wready,
output S_AXI_ARREADY,
output S_AXI_AWREADY,
output [1:0] S_AXI_BRESP,
output S_AXI_BVALID,
output [31:0] S_AXI_RDATA,
output [1:0] S_AXI_RRESP,
output S_AXI_RVALID,
output S_AXI_WREADY,
output [31:0] m_axi_araddr,
output [1:0] m_axi_arburst,
output [3:0] m_axi_arcache,
output [3:0] m_axi_arlen,
output [2:0] m_axi_arprot,
output [2:0] m_axi_arsize,
output m_axi_arvalid,
output [31:0] m_axi_awaddr,
output [1:0] m_axi_awburst,
output [3:0] m_axi_awcache,
output [3:0] m_axi_awlen,
output [2:0] m_axi_awprot,
output [2:0] m_axi_awsize,
output m_axi_awvalid,
output m_axi_bready,
output m_axi_rready,
output [31:0] m_axi_wdata,
output m_axi_wlast,
output [3:0] m_axi_wstrb,
output m_axi_wvalid,
output vga_clk,
output [7:0] vga_blue,
output [7:0] vga_green,
output vga_hsync,
output [7:0] vga_red,
output vga_de,
output vga_vsync
);
endmodule

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# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 14.2 Build EDK_P.28xd
# Tue Jul 31 18:47:17 2012
# Target Board: xilinx.com zc702 Rev C
# Family: zynq
# Device: xc7z020
# Package: clg484
# Speed Grade: -1
# ##############################################################################
PARAMETER VERSION = 2.1.0
PORT processing_system7_0_MIO = processing_system7_0_MIO, DIR = IO, VEC = [53:0]
PORT processing_system7_0_PS_SRSTB = processing_system7_0_PS_SRSTB, DIR = I
PORT processing_system7_0_PS_CLK = processing_system7_0_PS_CLK, DIR = I, SIGIS = CLK
PORT processing_system7_0_PS_PORB = processing_system7_0_PS_PORB, DIR = I
PORT processing_system7_0_DDR_Clk = processing_system7_0_DDR_Clk, DIR = IO, SIGIS = CLK
PORT processing_system7_0_DDR_Clk_n = processing_system7_0_DDR_Clk_n, DIR = IO, SIGIS = CLK
PORT processing_system7_0_DDR_CKE = processing_system7_0_DDR_CKE, DIR = IO
PORT processing_system7_0_DDR_CS_n = processing_system7_0_DDR_CS_n, DIR = IO
PORT processing_system7_0_DDR_RAS_n = processing_system7_0_DDR_RAS_n, DIR = IO
PORT processing_system7_0_DDR_CAS_n = processing_system7_0_DDR_CAS_n, DIR = IO
PORT processing_system7_0_DDR_WEB = processing_system7_0_DDR_WEB, DIR = O
PORT processing_system7_0_DDR_BankAddr = processing_system7_0_DDR_BankAddr, DIR = IO, VEC = [2:0]
PORT processing_system7_0_DDR_Addr = processing_system7_0_DDR_Addr, DIR = IO, VEC = [14:0]
PORT processing_system7_0_DDR_ODT = processing_system7_0_DDR_ODT, DIR = IO
PORT processing_system7_0_DDR_DRSTB = processing_system7_0_DDR_DRSTB, DIR = IO, SIGIS = RST
PORT processing_system7_0_DDR_DQ = processing_system7_0_DDR_DQ, DIR = IO, VEC = [31:0]
PORT processing_system7_0_DDR_DM = processing_system7_0_DDR_DM, DIR = IO, VEC = [3:0]
PORT processing_system7_0_DDR_DQS = processing_system7_0_DDR_DQS, DIR = IO, VEC = [3:0]
PORT processing_system7_0_DDR_DQS_n = processing_system7_0_DDR_DQS_n, DIR = IO, VEC = [3:0]
PORT processing_system7_0_DDR_VRN = processing_system7_0_DDR_VRN, DIR = IO
PORT processing_system7_0_DDR_VRP = processing_system7_0_DDR_VRP, DIR = IO
PORT xillybus_bus_clk = xillybus_0_xillybus_bus_clk, DIR = O
PORT xillybus_bus_rst_n = xillybus_0_xillybus_bus_rst_n, DIR = O
PORT xillybus_S_AXI_AWADDR = xillybus_0_xillybus_S_AXI_AWADDR, DIR = O, VEC = [31:0]
PORT xillybus_S_AXI_AWVALID = xillybus_0_xillybus_S_AXI_AWVALID, DIR = O
PORT xillybus_S_AXI_WDATA = xillybus_0_xillybus_S_AXI_WDATA, DIR = O, VEC = [31:0]
PORT xillybus_S_AXI_WSTRB = xillybus_0_xillybus_S_AXI_WSTRB, DIR = O, VEC = [3:0]
PORT xillybus_S_AXI_WVALID = xillybus_0_xillybus_S_AXI_WVALID, DIR = O
PORT xillybus_S_AXI_BREADY = xillybus_0_xillybus_S_AXI_BREADY, DIR = O
PORT xillybus_S_AXI_ARADDR = xillybus_0_xillybus_S_AXI_ARADDR, DIR = O, VEC = [31:0]
PORT xillybus_S_AXI_ARVALID = xillybus_0_xillybus_S_AXI_ARVALID, DIR = O
PORT xillybus_S_AXI_RREADY = xillybus_0_xillybus_S_AXI_RREADY, DIR = O
PORT xillybus_S_AXI_ARREADY = xillybus_0_xillybus_S_AXI_ARREADY, DIR = I
PORT xillybus_S_AXI_RDATA = xillybus_0_xillybus_S_AXI_RDATA, DIR = I, VEC = [31:0]
PORT xillybus_S_AXI_RRESP = xillybus_0_xillybus_S_AXI_RRESP, DIR = I, VEC = [1:0]
PORT xillybus_S_AXI_RVALID = xillybus_0_xillybus_S_AXI_RVALID, DIR = I
PORT xillybus_S_AXI_WREADY = xillybus_0_xillybus_S_AXI_WREADY, DIR = I
PORT xillybus_S_AXI_BRESP = xillybus_0_xillybus_S_AXI_BRESP, DIR = I, VEC = [1:0]
PORT xillybus_S_AXI_BVALID = xillybus_0_xillybus_S_AXI_BVALID, DIR = I
PORT xillybus_S_AXI_AWREADY = xillybus_0_xillybus_S_AXI_AWREADY, DIR = I
PORT xillybus_M_AXI_ARREADY = xillybus_0_xillybus_M_AXI_ARREADY, DIR = O
PORT xillybus_M_AXI_ARVALID = xillybus_0_xillybus_M_AXI_ARVALID, DIR = I
PORT xillybus_M_AXI_ARADDR = xillybus_0_xillybus_M_AXI_ARADDR, DIR = I, VEC = [31:0]
PORT xillybus_M_AXI_ARLEN = xillybus_0_xillybus_M_AXI_ARLEN, DIR = I, VEC = [3:0]
PORT xillybus_M_AXI_ARSIZE = xillybus_0_xillybus_M_AXI_ARSIZE, DIR = I, VEC = [2:0]
PORT xillybus_M_AXI_ARBURST = xillybus_0_xillybus_M_AXI_ARBURST, DIR = I, VEC = [1:0]
PORT xillybus_M_AXI_ARPROT = xillybus_0_xillybus_M_AXI_ARPROT, DIR = I, VEC = [2:0]
PORT xillybus_M_AXI_ARCACHE = xillybus_0_xillybus_M_AXI_ARCACHE, DIR = I, VEC = [3:0]
PORT xillybus_M_AXI_RREADY = xillybus_0_xillybus_M_AXI_RREADY, DIR = I
PORT xillybus_M_AXI_RVALID = xillybus_0_xillybus_M_AXI_RVALID, DIR = O
PORT xillybus_M_AXI_RDATA = xillybus_0_xillybus_M_AXI_RDATA, DIR = O, VEC = [63:0]
PORT xillybus_M_AXI_RRESP = xillybus_0_xillybus_M_AXI_RRESP, DIR = O, VEC = [1:0]
PORT xillybus_M_AXI_RLAST = xillybus_0_xillybus_M_AXI_RLAST, DIR = O
PORT xillybus_M_AXI_AWREADY = xillybus_0_xillybus_M_AXI_AWREADY, DIR = O
PORT xillybus_M_AXI_AWVALID = xillybus_0_xillybus_M_AXI_AWVALID, DIR = I
PORT xillybus_M_AXI_AWADDR = xillybus_0_xillybus_M_AXI_AWADDR, DIR = I, VEC = [31:0]
PORT xillybus_M_AXI_AWLEN = xillybus_0_xillybus_M_AXI_AWLEN, DIR = I, VEC = [3:0]
PORT xillybus_M_AXI_AWSIZE = xillybus_0_xillybus_M_AXI_AWSIZE, DIR = I, VEC = [2:0]
PORT xillybus_M_AXI_AWBURST = xillybus_0_xillybus_M_AXI_AWBURST, DIR = I, VEC = [1:0]
PORT xillybus_M_AXI_AWPROT = xillybus_0_xillybus_M_AXI_AWPROT, DIR = I, VEC = [2:0]
PORT xillybus_M_AXI_AWCACHE = xillybus_0_xillybus_M_AXI_AWCACHE, DIR = I, VEC = [3:0]
PORT xillybus_M_AXI_WREADY = xillybus_0_xillybus_M_AXI_WREADY, DIR = O
PORT xillybus_M_AXI_WVALID = xillybus_0_xillybus_M_AXI_WVALID, DIR = I
PORT xillybus_M_AXI_WDATA = xillybus_0_xillybus_M_AXI_WDATA, DIR = I, VEC = [63:0]
PORT xillybus_M_AXI_WSTRB = xillybus_0_xillybus_M_AXI_WSTRB, DIR = I, VEC = [7:0]
PORT xillybus_M_AXI_WLAST = xillybus_0_xillybus_M_AXI_WLAST, DIR = I
PORT xillybus_M_AXI_BREADY = xillybus_0_xillybus_M_AXI_BREADY, DIR = I
PORT xillybus_M_AXI_BVALID = xillybus_0_xillybus_M_AXI_BVALID, DIR = O
PORT xillybus_M_AXI_BRESP = xillybus_0_xillybus_M_AXI_BRESP, DIR = O, VEC = [1:0]
PORT xillybus_host_interrupt = xillybus_0_xillybus_host_interrupt, DIR = I
PORT xillyvga_0_clk_in = net_xillyvga_0_clk_in, DIR = I
PORT xillyvga_0_vga_hsync = xillyvga_0_vga_hsync, DIR = O
PORT xillyvga_0_vga_vsync = xillyvga_0_vga_vsync, DIR = O
PORT xillyvga_0_vga_de = xillyvga_0_vga_de, DIR = O
PORT xillyvga_0_vga_red = xillyvga_0_vga_red, DIR = O, VEC = [7:0]
PORT xillyvga_0_vga_green = xillyvga_0_vga_green, DIR = O, VEC = [7:0]
PORT xillyvga_0_vga_blue = xillyvga_0_vga_blue, DIR = O, VEC = [7:0]
PORT xillyvga_0_vga_clk = xillyvga_0_vga_clk, DIR = O
PORT processing_system7_0_GPIO = processing_system7_0_GPIO, DIR = IO, VEC = [55:0]
PORT processing_system7_0_USB0_VBUS_PWRFAULT = net_processing_system7_0_USB0_VBUS_PWRFAULT, DIR = I
PORT xillybus_lite_0_user_clk_pin = xillybus_lite_0_user_clk, DIR = O
PORT xillybus_lite_0_user_wren_pin = xillybus_lite_0_user_wren, DIR = O
PORT xillybus_lite_0_user_wstrb_pin = xillybus_lite_0_user_wstrb, DIR = O, VEC = [3:0]
PORT xillybus_lite_0_user_rden_pin = xillybus_lite_0_user_rden, DIR = O
PORT xillybus_lite_0_user_rd_data_pin = net_xillybus_lite_0_user_rd_data_pin, DIR = I, VEC = [31:0]
PORT xillybus_lite_0_user_wr_data_pin = xillybus_lite_0_user_wr_data, DIR = O, VEC = [31:0]
PORT xillybus_lite_0_user_addr_pin = xillybus_lite_0_user_addr, DIR = O, VEC = [31:0]
PORT xillybus_lite_0_user_irq_pin = net_xillybus_lite_0_user_irq_pin, DIR = I
BEGIN axi_interconnect
PARAMETER INSTANCE = axi4lite_0
PARAMETER HW_VER = 1.06.a
PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
PORT interconnect_aclk = processing_system7_0_FCLK_CLK1
PORT INTERCONNECT_ARESETN = processing_system7_0_M_AXI_GP0_ARESETN
END
BEGIN processing_system7
PARAMETER INSTANCE = processing_system7_0
PARAMETER HW_VER = 4.01.a
PARAMETER C_DDR_RAM_HIGHADDR = 0x1FFFFFFF
PARAMETER C_S_AXI_HP2_HIGHADDR = 0x1FFFFFFF
PARAMETER C_USE_M_AXI_GP0 = 1
PARAMETER C_EN_EMIO_CAN0 = 0
PARAMETER C_EN_EMIO_CAN1 = 0
PARAMETER C_EN_EMIO_ENET0 = 0
PARAMETER C_EN_EMIO_ENET1 = 0
PARAMETER C_EN_EMIO_I2C0 = 0
PARAMETER C_EN_EMIO_I2C1 = 0
PARAMETER C_EN_EMIO_PJTAG = 0
PARAMETER C_EN_EMIO_SDIO0 = 0
PARAMETER C_EN_EMIO_CD_SDIO0 = 0
PARAMETER C_EN_EMIO_WP_SDIO0 = 0
PARAMETER C_EN_EMIO_SDIO1 = 0
PARAMETER C_EN_EMIO_CD_SDIO1 = 0
PARAMETER C_EN_EMIO_WP_SDIO1 = 0
PARAMETER C_EN_EMIO_SPI0 = 0
PARAMETER C_EN_EMIO_SPI1 = 0
PARAMETER C_EN_EMIO_SRAM_INT = 0
PARAMETER C_EN_EMIO_TRACE = 0
PARAMETER C_EN_EMIO_TTC0 = 1
PARAMETER C_EN_EMIO_TTC1 = 0
PARAMETER C_EN_EMIO_UART0 = 0
PARAMETER C_EN_EMIO_UART1 = 0
PARAMETER C_EN_EMIO_MODEM_UART0 = 0
PARAMETER C_EN_EMIO_MODEM_UART1 = 0
PARAMETER C_EN_EMIO_WDT = 0
PARAMETER C_EN_QSPI = 1
PARAMETER C_EN_SMC = 0
PARAMETER C_EN_CAN0 = 0
PARAMETER C_EN_CAN1 = 0
PARAMETER C_EN_ENET0 = 1
PARAMETER C_EN_ENET1 = 0
PARAMETER C_EN_I2C0 = 0
PARAMETER C_EN_I2C1 = 0
PARAMETER C_EN_PJTAG = 0
PARAMETER C_EN_SDIO0 = 1
PARAMETER C_EN_SDIO1 = 0
PARAMETER C_EN_SPI0 = 0
PARAMETER C_EN_SPI1 = 0
PARAMETER C_EN_TRACE = 0
PARAMETER C_EN_TTC0 = 1
PARAMETER C_EN_TTC1 = 0
PARAMETER C_EN_UART0 = 0
PARAMETER C_EN_UART1 = 1
PARAMETER C_EN_MODEM_UART0 = 0
PARAMETER C_EN_MODEM_UART1 = 0
PARAMETER C_EN_USB0 = 1
PARAMETER C_EN_USB1 = 0
PARAMETER C_EN_WDT = 0
PARAMETER C_EN_DDR = 1
PARAMETER C_EN_GPIO = 1
PARAMETER C_FCLK_CLK0_FREQ = 100000000
PARAMETER C_FCLK_CLK1_FREQ = 100000000
PARAMETER C_FCLK_CLK2_FREQ = 50000000
PARAMETER C_FCLK_CLK3_FREQ = 50000000
PARAMETER C_USE_S_AXI_GP0 = 0
PARAMETER C_INTERCONNECT_S_AXI_GP0_MASTERS = xillybus_0.M_AXI
PARAMETER C_USE_S_AXI_HP0 = 0
PARAMETER C_USE_S_AXI_HP2 = 1
PARAMETER C_INTERCONNECT_S_AXI_HP2_MASTERS = xillyvga_0.M_AXI
PARAMETER C_S_AXI_HP2_DATA_WIDTH = 32
PARAMETER C_EN_EMIO_GPIO = 1
PARAMETER C_EMIO_GPIO_WIDTH = 56
PARAMETER C_USE_CR_FABRIC = 1
PARAMETER C_USE_S_AXI_ACP = 1
PARAMETER C_INTERCONNECT_S_AXI_ACP_MASTERS = xillybus_0.M_AXI
PARAMETER C_S_AXI_ACP_HIGHADDR = 0x1FFFFFFF
BUS_INTERFACE M_AXI_GP0 = axi4lite_0
BUS_INTERFACE S_AXI_HP2 = axi_interconnect_1
BUS_INTERFACE S_AXI_ACP = axi_interconnect_0
PORT MIO = processing_system7_0_MIO
PORT PS_SRSTB = processing_system7_0_PS_SRSTB
PORT PS_CLK = processing_system7_0_PS_CLK
PORT PS_PORB = processing_system7_0_PS_PORB
PORT DDR_Clk = processing_system7_0_DDR_Clk
PORT DDR_Clk_n = processing_system7_0_DDR_Clk_n
PORT DDR_CKE = processing_system7_0_DDR_CKE
PORT DDR_CS_n = processing_system7_0_DDR_CS_n
PORT DDR_RAS_n = processing_system7_0_DDR_RAS_n
PORT DDR_CAS_n = processing_system7_0_DDR_CAS_n
PORT DDR_WEB = processing_system7_0_DDR_WEB
PORT DDR_BankAddr = processing_system7_0_DDR_BankAddr
PORT DDR_Addr = processing_system7_0_DDR_Addr
PORT DDR_ODT = processing_system7_0_DDR_ODT
PORT DDR_DRSTB = processing_system7_0_DDR_DRSTB
PORT DDR_DQ = processing_system7_0_DDR_DQ
PORT DDR_DM = processing_system7_0_DDR_DM
PORT DDR_DQS = processing_system7_0_DDR_DQS
PORT DDR_DQS_n = processing_system7_0_DDR_DQS_n
PORT DDR_VRN = processing_system7_0_DDR_VRN
PORT DDR_VRP = processing_system7_0_DDR_VRP
PORT M_AXI_GP0_ARESETN = processing_system7_0_M_AXI_GP0_ARESETN
PORT FCLK_CLK1 = processing_system7_0_FCLK_CLK1
PORT M_AXI_GP0_ACLK = processing_system7_0_FCLK_CLK1
PORT IRQ_F2P = xillybus_0_Interrupt & xillybus_lite_0_host_interrupt
PORT S_AXI_HP2_ARESETN = processing_system7_0_S_AXI_HP2_ARESETN
PORT S_AXI_HP2_ACLK = processing_system7_0_FCLK_CLK1
PORT GPIO = processing_system7_0_GPIO
PORT USB0_VBUS_PWRFAULT = net_processing_system7_0_USB0_VBUS_PWRFAULT
PORT FCLK_RESET0_N = processing_system7_0_FCLK_RESET0_N
PORT S_AXI_ACP_ARESETN = processing_system7_0_S_AXI_ACP_ARESETN
PORT S_AXI_ACP_ACLK = processing_system7_0_FCLK_CLK1
PORT S_AXI_ACP_AWCACHE = 0b1111
PORT S_AXI_ACP_AWUSER = 0b11111
PORT S_AXI_ACP_ARCACHE = 0b1111
PORT S_AXI_ACP_ARUSER = 0b11111
END
BEGIN xillybus
PARAMETER INSTANCE = xillybus_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x50000000
PARAMETER C_HIGHADDR = 0x50000FFF
BUS_INTERFACE S_AXI = axi4lite_0
BUS_INTERFACE M_AXI = axi_interconnect_0
PORT m_axi_aclk = processing_system7_0_FCLK_CLK1
PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK1
PORT xillybus_bus_clk = xillybus_0_xillybus_bus_clk
PORT xillybus_bus_rst_n = xillybus_0_xillybus_bus_rst_n
PORT xillybus_S_AXI_AWADDR = xillybus_0_xillybus_S_AXI_AWADDR
PORT xillybus_S_AXI_AWVALID = xillybus_0_xillybus_S_AXI_AWVALID
PORT xillybus_S_AXI_WDATA = xillybus_0_xillybus_S_AXI_WDATA
PORT xillybus_S_AXI_WSTRB = xillybus_0_xillybus_S_AXI_WSTRB
PORT xillybus_S_AXI_WVALID = xillybus_0_xillybus_S_AXI_WVALID
PORT xillybus_S_AXI_BREADY = xillybus_0_xillybus_S_AXI_BREADY
PORT xillybus_S_AXI_ARADDR = xillybus_0_xillybus_S_AXI_ARADDR
PORT xillybus_S_AXI_ARVALID = xillybus_0_xillybus_S_AXI_ARVALID
PORT xillybus_S_AXI_RREADY = xillybus_0_xillybus_S_AXI_RREADY
PORT xillybus_S_AXI_ARREADY = xillybus_0_xillybus_S_AXI_ARREADY
PORT xillybus_S_AXI_RDATA = xillybus_0_xillybus_S_AXI_RDATA
PORT xillybus_S_AXI_RRESP = xillybus_0_xillybus_S_AXI_RRESP
PORT xillybus_S_AXI_RVALID = xillybus_0_xillybus_S_AXI_RVALID
PORT xillybus_S_AXI_WREADY = xillybus_0_xillybus_S_AXI_WREADY
PORT xillybus_S_AXI_BRESP = xillybus_0_xillybus_S_AXI_BRESP
PORT xillybus_S_AXI_BVALID = xillybus_0_xillybus_S_AXI_BVALID
PORT xillybus_S_AXI_AWREADY = xillybus_0_xillybus_S_AXI_AWREADY
PORT xillybus_M_AXI_ARREADY = xillybus_0_xillybus_M_AXI_ARREADY
PORT xillybus_M_AXI_ARVALID = xillybus_0_xillybus_M_AXI_ARVALID
PORT xillybus_M_AXI_ARADDR = xillybus_0_xillybus_M_AXI_ARADDR
PORT xillybus_M_AXI_ARLEN = xillybus_0_xillybus_M_AXI_ARLEN
PORT xillybus_M_AXI_ARSIZE = xillybus_0_xillybus_M_AXI_ARSIZE
PORT xillybus_M_AXI_ARBURST = xillybus_0_xillybus_M_AXI_ARBURST
PORT xillybus_M_AXI_ARPROT = xillybus_0_xillybus_M_AXI_ARPROT
PORT xillybus_M_AXI_ARCACHE = xillybus_0_xillybus_M_AXI_ARCACHE
PORT xillybus_M_AXI_RREADY = xillybus_0_xillybus_M_AXI_RREADY
PORT xillybus_M_AXI_RVALID = xillybus_0_xillybus_M_AXI_RVALID
PORT xillybus_M_AXI_RDATA = xillybus_0_xillybus_M_AXI_RDATA
PORT xillybus_M_AXI_RRESP = xillybus_0_xillybus_M_AXI_RRESP
PORT xillybus_M_AXI_RLAST = xillybus_0_xillybus_M_AXI_RLAST
PORT xillybus_M_AXI_AWREADY = xillybus_0_xillybus_M_AXI_AWREADY
PORT xillybus_M_AXI_AWVALID = xillybus_0_xillybus_M_AXI_AWVALID
PORT xillybus_M_AXI_AWADDR = xillybus_0_xillybus_M_AXI_AWADDR
PORT xillybus_M_AXI_AWLEN = xillybus_0_xillybus_M_AXI_AWLEN
PORT xillybus_M_AXI_AWSIZE = xillybus_0_xillybus_M_AXI_AWSIZE
PORT xillybus_M_AXI_AWBURST = xillybus_0_xillybus_M_AXI_AWBURST
PORT xillybus_M_AXI_AWPROT = xillybus_0_xillybus_M_AXI_AWPROT
PORT xillybus_M_AXI_AWCACHE = xillybus_0_xillybus_M_AXI_AWCACHE
PORT xillybus_M_AXI_WREADY = xillybus_0_xillybus_M_AXI_WREADY
PORT xillybus_M_AXI_WVALID = xillybus_0_xillybus_M_AXI_WVALID
PORT xillybus_M_AXI_WDATA = xillybus_0_xillybus_M_AXI_WDATA
PORT xillybus_M_AXI_WSTRB = xillybus_0_xillybus_M_AXI_WSTRB
PORT xillybus_M_AXI_WLAST = xillybus_0_xillybus_M_AXI_WLAST
PORT xillybus_M_AXI_BREADY = xillybus_0_xillybus_M_AXI_BREADY
PORT xillybus_M_AXI_BVALID = xillybus_0_xillybus_M_AXI_BVALID
PORT xillybus_M_AXI_BRESP = xillybus_0_xillybus_M_AXI_BRESP
PORT xillybus_host_interrupt = xillybus_0_xillybus_host_interrupt
PORT Interrupt = xillybus_0_Interrupt
END
BEGIN xillyvga
PARAMETER INSTANCE = xillyvga_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x50001000
PARAMETER C_HIGHADDR = 0x50001FFF
BUS_INTERFACE M_AXI = axi_interconnect_1
BUS_INTERFACE S_AXI = axi4lite_0
PORT clk_in = net_xillyvga_0_clk_in
PORT vga_hsync = xillyvga_0_vga_hsync
PORT vga_vsync = xillyvga_0_vga_vsync
PORT vga_de = xillyvga_0_vga_de
PORT vga_red = xillyvga_0_vga_red
PORT vga_green = xillyvga_0_vga_green
PORT vga_blue = xillyvga_0_vga_blue
PORT m_axi_aclk = processing_system7_0_FCLK_CLK1
PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK1
PORT vga_clk = xillyvga_0_vga_clk
END
BEGIN axi_interconnect
PARAMETER INSTANCE = axi_interconnect_1
PARAMETER HW_VER = 1.06.a
PORT INTERCONNECT_ACLK = processing_system7_0_FCLK_CLK1
PORT INTERCONNECT_ARESETN = processing_system7_0_S_AXI_HP2_ARESETN
END
BEGIN xillybus_lite
PARAMETER INSTANCE = xillybus_lite_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x50002000
PARAMETER C_HIGHADDR = 0x50002FFF
BUS_INTERFACE S_AXI = axi4lite_0
PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK1
PORT host_interrupt = xillybus_lite_0_host_interrupt
PORT user_clk = xillybus_lite_0_user_clk
PORT user_wren = xillybus_lite_0_user_wren
PORT user_wstrb = xillybus_lite_0_user_wstrb
PORT user_rden = xillybus_lite_0_user_rden
PORT user_rd_data = net_xillybus_lite_0_user_rd_data_pin
PORT user_wr_data = xillybus_lite_0_user_wr_data
PORT user_addr = xillybus_lite_0_user_addr
PORT user_irq = net_xillybus_lite_0_user_irq_pin
END
BEGIN axi_interconnect
PARAMETER INSTANCE = axi_interconnect_0
PARAMETER HW_VER = 1.06.a
PORT INTERCONNECT_ACLK = processing_system7_0_FCLK_CLK1
PORT INTERCONNECT_ARESETN = processing_system7_0_S_AXI_ACP_ARESETN
END

31
xillinux-syn/system/system.xmp Normal file
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#Please do not modify this file by hand
XmpVersion: 14.2
VerMgmt: 14.2
IntStyle: default
Flow: ise
MHS File: system.mhs
Architecture: zynq
Device: xc7z020
Package: clg484
SpeedGrade: -1
UserCmd1:
UserCmd1Type: 0
UserCmd2:
UserCmd2Type: 0
GenSimTB: 0
SdkExportBmmBit: 0
SdkExportDir: SDK/SDK_Export
InsertNoPads: 1
WarnForEAArch: 1
HdlLang: verilog
SimModel: BEHAVIORAL
ExternalMemSim: 0
UcfFile: data/system.ucf
EnableParTimingError: 1
ShowLicenseDialog: 1
LockAddr: xillybus_0,C_BASEADDR
LockAddr: xillyvga_0,C_BASEADDR
LockAddr: xillybus_lite_0,C_BASEADDR
Processor: processing_system7_0
ElfImp:
ElfSim:

21
xillinux-syn/vhdl/src/fifo_32x512.v Normal file
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module fifo_32x512 (
clk,
srst,
din,
wr_en,
rd_en,
dout,
full,
empty
);
input clk;
input srst;
input [31 : 0] din;
input wr_en;
input rd_en;
output [31 : 0] dout;
output full;
output empty;
endmodule

22
xillinux-syn/vhdl/src/fifo_8x2048.v Normal file
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module fifo_8x2048 (
clk,
srst,
din,
wr_en,
rd_en,
dout,
full,
empty
);
input clk;
input srst;
input [7 : 0] din;
input wr_en;
input rd_en;
output [7 : 0] dout;
output full;
output empty;
endmodule

151
xillinux-syn/vhdl/src/i2s_audio.v Normal file
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module i2s_audio
(
input bus_clk,
input quiesce,
input clk_100,
output reg audio_mclk,
output reg audio_dac,
input audio_adc,
input audio_bclk,
input audio_lrclk,
input user_w_audio_wren,
input [31:0] user_w_audio_data,
output user_w_audio_full,
input user_w_audio_open,
input user_r_audio_rden,
output [31:0] user_r_audio_data,
output user_r_audio_empty,
output user_r_audio_eof,
input user_r_audio_open
);
reg audio_adc_reg;
reg audio_bclk_reg;
reg audio_lrclk_reg;
reg audio_lrclk_reg_d;
reg [1:0] clk_div;
reg [15:0] play_shreg;
reg [1:0] bclk_d;
reg fifo_rd_en;
wire bclk_rising, bclk_falling;
wire [31:0] play_fifo_data;
reg [31:0] record_shreg;
reg [4:0] record_count;
reg write_when_done;
reg fifo_wr_en;
// synthesis attribute IOB of audio_mclk is TRUE
// synthesis attribute IOB of audio_dac is TRUE
// synthesis attribute IOB of audio_adc_reg is TRUE
// synthesis attribute IOB of audio_bclk_reg is TRUE
// synthesis attribute IOB of audio_lrclk_reg is TRUE
assign user_r_audio_eof = 0;
// Produce a 25 MHz clock for MCLK
always @(posedge clk_100)
begin
clk_div <= clk_div + 1;
audio_mclk <= clk_div[1];
end
assign bclk_rising = (bclk_d == 2'b01);
assign bclk_falling = (bclk_d == 2'b10);
// BCLK runs at 3.072 MHz, so the signals are sampled and handled
// synchronously, with an obvious delay, which is negligble compared
// with a BCLK clock cycle.
always @(posedge bus_clk)
begin
audio_adc_reg <= audio_adc;
audio_bclk_reg <= audio_bclk;
audio_lrclk_reg <= audio_lrclk;
bclk_d <= { bclk_d, audio_bclk_reg };
if (bclk_rising)
audio_lrclk_reg_d <= audio_lrclk_reg;
// Playback
fifo_rd_en <= 0; // Possibly overridden below
if (bclk_rising && !audio_lrclk_reg && audio_lrclk_reg_d)
play_shreg <= play_fifo_data[31:16]; // Left channel
else if (bclk_rising && audio_lrclk_reg && !audio_lrclk_reg_d)
begin
play_shreg <= play_fifo_data[15:0]; // Right channel
fifo_rd_en <= 1;
end
else if (bclk_falling)
begin
audio_dac <= play_shreg[15];
play_shreg <= { play_shreg, 1'b0 };
end
// Recording
fifo_wr_en <= 0; // Possibly overridden below
if (bclk_rising && (record_count != 0))
begin
record_shreg <= { record_shreg, audio_adc_reg };
record_count <= record_count - 1;
if (record_count == 1)
begin
fifo_wr_en <= write_when_done;
write_when_done <= 0;
end
end
if (bclk_rising && !audio_lrclk_reg && audio_lrclk_reg_d)
begin
record_count <= 16;
write_when_done <= 0;
end
else if (bclk_rising && audio_lrclk_reg && !audio_lrclk_reg_d)
begin
record_count <= 16;
write_when_done <= 1;
end
end
// Note that there is no check on the empty line. If the FIFO is empty,
// it will emit the same output all the time, so the audio output will be
// silent, which is fairly OK for an underrun.
fifo_32x512 playback_fifo
(
.clk(bus_clk),
.srst(!user_w_audio_open),
.din(user_w_audio_data), // Bus [31 : 0]
.wr_en(user_w_audio_wren),
.rd_en(fifo_rd_en),
.dout(play_fifo_data), // Bus [31 : 0]
.full(user_w_audio_full),
.empty());
// The full lines isn't checked. Not much to do on an overrun
fifo_32x512 record_fifo
(
.clk(bus_clk),
.srst(!user_r_audio_open),
.din(record_shreg), // Bus [31 : 0]
.wr_en(fifo_wr_en),
.rd_en(user_r_audio_rden),
.dout(user_r_audio_data), // Bus [31 : 0]
.full(),
.empty(user_r_audio_empty));
endmodule

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module smbus
(
input bus_clk,
input quiesce,
input user_w_smb_wren,
input [7:0] user_w_smb_data,
output user_w_smb_full,
input user_w_smb_open,
input user_r_smb_rden,
output [7:0] user_r_smb_data,
output user_r_smb_empty,
output user_r_smb_eof,
input user_r_smb_open,
output smb_sclk,
inout smb_sdata,
output [1:0] smbus_addr
);
reg [11:0] div_counter;
reg sclk_logic, sdata_logic, sdata_sample;
reg SMBus_en, pre_en;
reg [3:0] state;
reg first, dir_write, save_direction;
reg [7:0] write_byte, read_byte;
reg [2:0] idx;
reg write_byte_valid;
reg fifo_wr_en;
reg open_d, stop_pending;
parameter clk_freq = 150; // In MHz, nearest integer
parameter st_idle = 0,
st_start = 1,
st_fetch = 2,
st_bit0 = 3,
st_bit1 = 4,
st_bit2 = 5,
st_ack0 = 6,
st_ack1 = 7,
st_ack2 = 8,
st_stop0 = 9,
st_stop1 = 10,
st_stop2 = 11; // Represented by "default"
assign user_r_smb_eof = 0;
// Emulated open collector output
// Note that sclk and sdata must be pulled up, possibly with
// a PULLUP constraint on the IOB (or a 10 kOhm ext. resistor)
assign smb_sclk = sclk_logic ? 1'bz : 1'b0 ;
assign smb_sdata = sdata_logic ? 1'bz : 1'b0 ;
assign smbus_addr = 0;
assign user_w_smb_full = write_byte_valid || stop_pending;
// SMBus_en should be high every 10 us
// This allows a huge multicycle path constraint on SBBus_en
always @(posedge bus_clk)
begin
SMBus_en <= pre_en;
sdata_sample <= smb_sdata;
fifo_wr_en <= SMBus_en && (state == st_ack0) && !dir_write;
open_d <= user_w_smb_open;
if (open_d && !user_w_smb_open)
stop_pending <= 1;
if (user_w_smb_wren)
begin
write_byte <= user_w_smb_data;
write_byte_valid <= 1; // Zeroed by state machine
end
if (div_counter == ((clk_freq * 10) - 1))
begin
div_counter <= 0;
pre_en <= 1;
end
else
begin
div_counter <= div_counter + 1;
pre_en <= 0;
end
// State machine
if (SMBus_en)
case (state)
st_idle:
begin
sclk_logic <= 1;
sdata_logic <= 1;
stop_pending <= 0;
if (write_byte_valid)
state <= st_start;
end
st_start:
begin
sdata_logic <= 0; // Start condition
first <= 1;
dir_write <= 1;
state <= st_fetch;
end
st_fetch:
begin
sclk_logic <= 0;
idx <= 7;
state <= st_bit0;
end
st_bit0:
begin
if (dir_write)
sdata_logic <= write_byte[idx];
else
sdata_logic <= 1; // Keep clear when reading
state <= st_bit1;
end
st_bit1:
begin
sclk_logic <= 1;
read_byte[idx] <= sdata_sample;
state <= st_bit2;
end
st_bit2:
begin
sclk_logic <= 0;
idx <= idx - 1;
if (idx != 0)
state <= st_bit0;
else
state <= st_ack0;
end
st_ack0:
begin
if (dir_write)
sdata_logic <= 1; // The slave should ack
else
sdata_logic <= 0; // We ack on read
save_direction <= !write_byte[0];
state <= st_ack1;
end
st_ack1:
if (!dir_write || !sdata_sample || stop_pending)
begin
state <= st_ack2; // Read mode or slave acked. Or Quit.
write_byte_valid <= 0;
end
st_ack2:
begin
sclk_logic <= 1;
if (write_byte_valid)
begin
if (first)
dir_write <= save_direction;
first <= 0;
state <= st_fetch;
end
else if (stop_pending && dir_write)
state <= st_stop0;
else if (stop_pending)
state <= st_stop2; // Don't toggle clock in read mode
end
// The three stop states toggle the clock once, so that
// we're sure that the slave has released the bus, leaving
// its acknowledge state. Used only in write direction.
st_stop0:
begin
sclk_logic <= 0;
state <= st_stop1;
end
st_stop1:
begin
sdata_logic <= 0;
state <= st_stop2;
end
default: // Normally this is st_stop2
begin
sclk_logic <= 1;
write_byte_valid <= 0;
// st_idle will raise sdata to '1', making a stop condition
state <= st_idle;
end
endcase
if (quiesce) // Override all above.
begin
state <= st_idle;
stop_pending <= 0;
write_byte_valid <= 0;
end
end
fifo_8x2048 fifo
(
.clk(bus_clk),
.srst(!user_r_smb_open),
.din(read_byte), // Bus [7 : 0]
.wr_en(fifo_wr_en),
.rd_en(user_r_smb_rden),
.dout(user_r_smb_data), // Bus [7 : 0]
.full(),
.empty(user_r_smb_empty));
endmodule

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module system
(
processing_system7_0_MIO,
processing_system7_0_PS_SRSTB,
processing_system7_0_PS_CLK,
processing_system7_0_PS_PORB,
processing_system7_0_DDR_Clk,
processing_system7_0_DDR_Clk_n,
processing_system7_0_DDR_CKE,
processing_system7_0_DDR_CS_n,
processing_system7_0_DDR_RAS_n,
processing_system7_0_DDR_CAS_n,
processing_system7_0_DDR_WEB,
processing_system7_0_DDR_BankAddr,
processing_system7_0_DDR_Addr,
processing_system7_0_DDR_ODT,
processing_system7_0_DDR_DRSTB,
processing_system7_0_DDR_DQ,
processing_system7_0_DDR_DM,
processing_system7_0_DDR_DQS,
processing_system7_0_DDR_DQS_n,
processing_system7_0_DDR_VRN,
processing_system7_0_DDR_VRP,
xillybus_bus_clk,
xillybus_bus_rst_n,
xillybus_S_AXI_AWADDR,
xillybus_S_AXI_AWVALID,
xillybus_S_AXI_WDATA,
xillybus_S_AXI_WSTRB,
xillybus_S_AXI_WVALID,
xillybus_S_AXI_BREADY,
xillybus_S_AXI_ARADDR,
xillybus_S_AXI_ARVALID,
xillybus_S_AXI_RREADY,
xillybus_S_AXI_ARREADY,
xillybus_S_AXI_RDATA,
xillybus_S_AXI_RRESP,
xillybus_S_AXI_RVALID,
xillybus_S_AXI_WREADY,
xillybus_S_AXI_BRESP,
xillybus_S_AXI_BVALID,
xillybus_S_AXI_AWREADY,
xillybus_M_AXI_ARREADY,
xillybus_M_AXI_ARVALID,
xillybus_M_AXI_ARADDR,
xillybus_M_AXI_ARLEN,
xillybus_M_AXI_ARSIZE,
xillybus_M_AXI_ARBURST,
xillybus_M_AXI_ARPROT,
xillybus_M_AXI_ARCACHE,
xillybus_M_AXI_RREADY,
xillybus_M_AXI_RVALID,
xillybus_M_AXI_RDATA,
xillybus_M_AXI_RRESP,
xillybus_M_AXI_RLAST,
xillybus_M_AXI_AWREADY,
xillybus_M_AXI_AWVALID,
xillybus_M_AXI_AWADDR,
xillybus_M_AXI_AWLEN,
xillybus_M_AXI_AWSIZE,
xillybus_M_AXI_AWBURST,
xillybus_M_AXI_AWPROT,
xillybus_M_AXI_AWCACHE,
xillybus_M_AXI_WREADY,
xillybus_M_AXI_WVALID,
xillybus_M_AXI_WDATA,
xillybus_M_AXI_WSTRB,
xillybus_M_AXI_WLAST,
xillybus_M_AXI_BREADY,
xillybus_M_AXI_BVALID,
xillybus_M_AXI_BRESP,
xillybus_host_interrupt,
xillyvga_0_clk_in,
xillyvga_0_vga_hsync,
xillyvga_0_vga_vsync,
xillyvga_0_vga_de,
xillyvga_0_vga_red,
xillyvga_0_vga_green,
xillyvga_0_vga_blue,
xillyvga_0_vga_clk,
processing_system7_0_GPIO,
processing_system7_0_USB0_VBUS_PWRFAULT,
xillybus_lite_0_user_clk_pin,
xillybus_lite_0_user_wren_pin,
xillybus_lite_0_user_wstrb_pin,
xillybus_lite_0_user_rden_pin,
xillybus_lite_0_user_rd_data_pin,
xillybus_lite_0_user_wr_data_pin,
xillybus_lite_0_user_addr_pin,
xillybus_lite_0_user_irq_pin
);
inout [53:0] processing_system7_0_MIO;
input processing_system7_0_PS_SRSTB;
input processing_system7_0_PS_CLK;
input processing_system7_0_PS_PORB;
inout processing_system7_0_DDR_Clk;
inout processing_system7_0_DDR_Clk_n;
inout processing_system7_0_DDR_CKE;
inout processing_system7_0_DDR_CS_n;
inout processing_system7_0_DDR_RAS_n;
inout processing_system7_0_DDR_CAS_n;
output processing_system7_0_DDR_WEB;
inout [2:0] processing_system7_0_DDR_BankAddr;
inout [14:0] processing_system7_0_DDR_Addr;
inout processing_system7_0_DDR_ODT;
inout processing_system7_0_DDR_DRSTB;
inout [31:0] processing_system7_0_DDR_DQ;
inout [3:0] processing_system7_0_DDR_DM;
inout [3:0] processing_system7_0_DDR_DQS;
inout [3:0] processing_system7_0_DDR_DQS_n;
inout processing_system7_0_DDR_VRN;
inout processing_system7_0_DDR_VRP;
output xillybus_bus_clk;
output xillybus_bus_rst_n;
output [31:0] xillybus_S_AXI_AWADDR;
output xillybus_S_AXI_AWVALID;
output [31:0] xillybus_S_AXI_WDATA;
output [3:0] xillybus_S_AXI_WSTRB;
output xillybus_S_AXI_WVALID;
output xillybus_S_AXI_BREADY;
output [31:0] xillybus_S_AXI_ARADDR;
output xillybus_S_AXI_ARVALID;
output xillybus_S_AXI_RREADY;
input xillybus_S_AXI_ARREADY;
input [31:0] xillybus_S_AXI_RDATA;
input [1:0] xillybus_S_AXI_RRESP;
input xillybus_S_AXI_RVALID;
input xillybus_S_AXI_WREADY;
input [1:0] xillybus_S_AXI_BRESP;
input xillybus_S_AXI_BVALID;
input xillybus_S_AXI_AWREADY;
output xillybus_M_AXI_ARREADY;
input xillybus_M_AXI_ARVALID;
input [31:0] xillybus_M_AXI_ARADDR;
input [3:0] xillybus_M_AXI_ARLEN;
input [2:0] xillybus_M_AXI_ARSIZE;
input [1:0] xillybus_M_AXI_ARBURST;
input [2:0] xillybus_M_AXI_ARPROT;
input [3:0] xillybus_M_AXI_ARCACHE;
input xillybus_M_AXI_RREADY;
output xillybus_M_AXI_RVALID;
output [63:0] xillybus_M_AXI_RDATA;
output [1:0] xillybus_M_AXI_RRESP;
output xillybus_M_AXI_RLAST;
output xillybus_M_AXI_AWREADY;
input xillybus_M_AXI_AWVALID;
input [31:0] xillybus_M_AXI_AWADDR;
input [3:0] xillybus_M_AXI_AWLEN;
input [2:0] xillybus_M_AXI_AWSIZE;
input [1:0] xillybus_M_AXI_AWBURST;
input [2:0] xillybus_M_AXI_AWPROT;
input [3:0] xillybus_M_AXI_AWCACHE;
output xillybus_M_AXI_WREADY;
input xillybus_M_AXI_WVALID;
input [63:0] xillybus_M_AXI_WDATA;
input [7:0] xillybus_M_AXI_WSTRB;
input xillybus_M_AXI_WLAST;
input xillybus_M_AXI_BREADY;
output xillybus_M_AXI_BVALID;
output [1:0] xillybus_M_AXI_BRESP;
input xillybus_host_interrupt;
input xillyvga_0_clk_in;
output xillyvga_0_vga_hsync;
output xillyvga_0_vga_vsync;
output xillyvga_0_vga_de;
output [7:0] xillyvga_0_vga_red;
output [7:0] xillyvga_0_vga_green;
output [7:0] xillyvga_0_vga_blue;
output xillyvga_0_vga_clk;
inout [55:0] processing_system7_0_GPIO;
input processing_system7_0_USB0_VBUS_PWRFAULT;
output xillybus_lite_0_user_clk_pin;
output xillybus_lite_0_user_wren_pin;
output [3:0] xillybus_lite_0_user_wstrb_pin;
output xillybus_lite_0_user_rden_pin;
input [31:0] xillybus_lite_0_user_rd_data_pin;
output [31:0] xillybus_lite_0_user_wr_data_pin;
output [31:0] xillybus_lite_0_user_addr_pin;
input xillybus_lite_0_user_irq_pin;
endmodule

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`timescale 1ns / 10ps
module xillybus(GPIO_LED, quiesce, MIO, PS_SRSTB, PS_CLK, PS_PORB, DDR_Clk,
DDR_Clk_n, DDR_CKE, DDR_CS_n, DDR_RAS_n, DDR_CAS_n, DDR_WEB, DDR_BankAddr,
DDR_Addr, DDR_ODT, DDR_DRSTB, DDR_DQ, DDR_DM, DDR_DQS, DDR_DQS_n, DDR_VRN,
DDR_VRP, bus_clk, PS_GPIO, otg_oc, clk_100, vga4_red, vga4_green, vga4_blue,
vga_hsync, vga_vsync, user_clk, user_wren, user_wstrb, user_rden,
user_rd_data, user_wr_data, user_addr, user_irq, user_r_smb_rden,
user_r_smb_data, user_r_smb_empty, user_r_smb_eof, user_r_smb_open,
user_w_smb_wren, user_w_smb_data, user_w_smb_full, user_w_smb_open,
user_r_audio_rden, user_r_audio_data, user_r_audio_empty, user_r_audio_eof,
user_r_audio_open, user_w_audio_wren, user_w_audio_data, user_w_audio_full,
user_w_audio_open, user_r_read_32_rden, user_r_read_32_data,
user_r_read_32_empty, user_r_read_32_eof, user_r_read_32_open,
user_w_write_32_wren, user_w_write_32_data, user_w_write_32_full,
user_w_write_32_open, user_r_read_8_rden, user_r_read_8_data,
user_r_read_8_empty, user_r_read_8_eof, user_r_read_8_open,
user_w_write_8_wren, user_w_write_8_data, user_w_write_8_full,
user_w_write_8_open, user_r_mem_8_rden, user_r_mem_8_data,
user_r_mem_8_empty, user_r_mem_8_eof, user_r_mem_8_open, user_w_mem_8_wren,
user_w_mem_8_data, user_w_mem_8_full, user_w_mem_8_open, user_mem_8_addr,
user_mem_8_addr_update);
input PS_SRSTB;
input PS_CLK;
input PS_PORB;
input otg_oc;
input clk_100;
input [31:0] user_rd_data;
input user_irq;
input [7:0] user_r_smb_data;
input user_r_smb_empty;
input user_r_smb_eof;
input user_w_smb_full;
input [31:0] user_r_audio_data;
input user_r_audio_empty;
input user_r_audio_eof;
input user_w_audio_full;
input [31:0] user_r_read_32_data;
input user_r_read_32_empty;
input user_r_read_32_eof;
input user_w_write_32_full;
input [7:0] user_r_read_8_data;
input user_r_read_8_empty;
input user_r_read_8_eof;
input user_w_write_8_full;
input [7:0] user_r_mem_8_data;
input user_r_mem_8_empty;
input user_r_mem_8_eof;
input user_w_mem_8_full;
output [3:0] GPIO_LED;
output quiesce;
output DDR_WEB;
output bus_clk;
output [3:0] vga4_red;
output [3:0] vga4_green;
output [3:0] vga4_blue;
output vga_hsync;
output vga_vsync;
output user_clk;
output user_wren;
output [3:0] user_wstrb;
output user_rden;
output [31:0] user_wr_data;
output [31:0] user_addr;
output user_r_smb_rden;
output user_r_smb_open;
output user_w_smb_wren;
output [7:0] user_w_smb_data;
output user_w_smb_open;
output user_r_audio_rden;
output user_r_audio_open;
output user_w_audio_wren;
output [31:0] user_w_audio_data;
output user_w_audio_open;
output user_r_read_32_rden;
output user_r_read_32_open;
output user_w_write_32_wren;
output [31:0] user_w_write_32_data;
output user_w_write_32_open;
output user_r_read_8_rden;
output user_r_read_8_open;
output user_w_write_8_wren;
output [7:0] user_w_write_8_data;
output user_w_write_8_open;
output user_r_mem_8_rden;
output user_r_mem_8_open;
output user_w_mem_8_wren;
output [7:0] user_w_mem_8_data;
output user_w_mem_8_open;
output [4:0] user_mem_8_addr;
output user_mem_8_addr_update;
inout [53:0] MIO;
inout DDR_Clk;
inout DDR_Clk_n;
inout DDR_CKE;
inout DDR_CS_n;
inout DDR_RAS_n;
inout DDR_CAS_n;
inout [2:0] DDR_BankAddr;
inout [14:0] DDR_Addr;
inout DDR_ODT;
inout DDR_DRSTB;
inout [31:0] DDR_DQ;
inout [3:0] DDR_DM;
inout [3:0] DDR_DQS;
inout [3:0] DDR_DQS_n;
inout DDR_VRN;
inout DDR_VRP;
inout [55:0] PS_GPIO;
wire bus_rst_n;
wire [31:0] S_AXI_AWADDR;
wire S_AXI_AWVALID;
wire [31:0] S_AXI_WDATA;
wire [3:0] S_AXI_WSTRB;
wire S_AXI_WVALID;
wire S_AXI_BREADY;
wire [31:0] S_AXI_ARADDR;
wire S_AXI_ARVALID;
wire S_AXI_RREADY;
wire S_AXI_ARREADY;
wire [31:0] S_AXI_RDATA;
wire [1:0] S_AXI_RRESP;
wire S_AXI_RVALID;
wire S_AXI_WREADY;
wire [1:0] S_AXI_BRESP;
wire S_AXI_BVALID;
wire S_AXI_AWREADY;
wire M_AXI_ACP_ARREADY;
wire M_AXI_ACP_ARVALID;
wire [31:0] M_AXI_ACP_ARADDR;
wire [3:0] M_AXI_ACP_ARLEN;
wire [2:0] M_AXI_ACP_ARSIZE;
wire [1:0] M_AXI_ACP_ARBURST;
wire [2:0] M_AXI_ACP_ARPROT;
wire [3:0] M_AXI_ACP_ARCACHE;
wire M_AXI_ACP_RREADY;
wire M_AXI_ACP_RVALID;
wire [63:0] M_AXI_ACP_RDATA;
wire [1:0] M_AXI_ACP_RRESP;
wire M_AXI_ACP_RLAST;
wire M_AXI_ACP_AWREADY;
wire M_AXI_ACP_AWVALID;
wire [31:0] M_AXI_ACP_AWADDR;
wire [3:0] M_AXI_ACP_AWLEN;
wire [2:0] M_AXI_ACP_AWSIZE;
wire [1:0] M_AXI_ACP_AWBURST;
wire [2:0] M_AXI_ACP_AWPROT;
wire [3:0] M_AXI_ACP_AWCACHE;
wire M_AXI_ACP_WREADY;
wire M_AXI_ACP_WVALID;
wire [63:0] M_AXI_ACP_WDATA;
wire [7:0] M_AXI_ACP_WSTRB;
wire M_AXI_ACP_WLAST;
wire M_AXI_ACP_BREADY;
wire M_AXI_ACP_BVALID;
wire [1:0] M_AXI_ACP_BRESP;
wire host_interrupt;
wire [7:0] xillyvga_0_vga_red;
wire [7:0] xillyvga_0_vga_green;
wire [7:0] xillyvga_0_vga_blue;
wire vga_hsync_w;
wire vga_vsync_w;
wire USB0_VBUS_PWRFAULT;
// This perl snippet turns the input/output ports to wires, so only
// those that really connect something become real ports (input/output
// keywords are used to create global variables)
assign USB0_VBUS_PWRFAULT = !otg_oc;
// synthesis attribute IOB of vga_iob_ff is "TRUE"
FDCE vga_iob_ff [13:0]
(
.Q( { vga4_red, vga4_green, vga4_blue, vga_hsync, vga_vsync} ),
.D( { xillyvga_0_vga_red[7:4],
xillyvga_0_vga_green[7:4],
xillyvga_0_vga_blue[7:4],
vga_hsync_w, vga_vsync_w } ),
.C(vga_clk), .CE(1'b1), .CLR(1'b0)
);
(* BOX_TYPE = "user_black_box" *)
system
system_i (
.processing_system7_0_MIO ( MIO ),
.processing_system7_0_PS_SRSTB ( PS_SRSTB ),
.processing_system7_0_PS_CLK ( PS_CLK ),
.processing_system7_0_PS_PORB ( PS_PORB ),
.processing_system7_0_DDR_Clk ( DDR_Clk ),
.processing_system7_0_DDR_Clk_n ( DDR_Clk_n ),
.processing_system7_0_DDR_CKE ( DDR_CKE ),
.processing_system7_0_DDR_CS_n ( DDR_CS_n ),
.processing_system7_0_DDR_RAS_n ( DDR_RAS_n ),
.processing_system7_0_DDR_CAS_n ( DDR_CAS_n ),
.processing_system7_0_DDR_WEB ( DDR_WEB ),
.processing_system7_0_DDR_BankAddr ( DDR_BankAddr ),
.processing_system7_0_DDR_Addr ( DDR_Addr ),
.processing_system7_0_DDR_ODT ( DDR_ODT ),
.processing_system7_0_DDR_DRSTB ( DDR_DRSTB ),
.processing_system7_0_DDR_DQ ( DDR_DQ ),
.processing_system7_0_DDR_DM ( DDR_DM ),
.processing_system7_0_DDR_DQS ( DDR_DQS ),
.processing_system7_0_DDR_DQS_n ( DDR_DQS_n ),
.processing_system7_0_DDR_VRN ( DDR_VRN ),
.processing_system7_0_DDR_VRP ( DDR_VRP ),
.processing_system7_0_GPIO ( PS_GPIO ),
.processing_system7_0_USB0_VBUS_PWRFAULT ( USB0_VBUS_PWRFAULT ),
.xillybus_bus_clk ( bus_clk ),
.xillybus_bus_rst_n ( bus_rst_n ),
.xillybus_S_AXI_AWADDR ( S_AXI_AWADDR ),
.xillybus_S_AXI_AWVALID ( S_AXI_AWVALID ),
.xillybus_S_AXI_WDATA ( S_AXI_WDATA ),
.xillybus_S_AXI_WSTRB ( S_AXI_WSTRB ),
.xillybus_S_AXI_WVALID ( S_AXI_WVALID ),
.xillybus_S_AXI_BREADY ( S_AXI_BREADY ),
.xillybus_S_AXI_ARADDR ( S_AXI_ARADDR ),
.xillybus_S_AXI_ARVALID ( S_AXI_ARVALID ),
.xillybus_S_AXI_RREADY ( S_AXI_RREADY ),
.xillybus_S_AXI_ARREADY ( S_AXI_ARREADY ),
.xillybus_S_AXI_RDATA ( S_AXI_RDATA ),
.xillybus_S_AXI_RRESP ( S_AXI_RRESP ),
.xillybus_S_AXI_RVALID ( S_AXI_RVALID ),
.xillybus_S_AXI_WREADY ( S_AXI_WREADY ),
.xillybus_S_AXI_BRESP ( S_AXI_BRESP ),
.xillybus_S_AXI_BVALID ( S_AXI_BVALID ),
.xillybus_S_AXI_AWREADY ( S_AXI_AWREADY ),
.xillybus_M_AXI_ARREADY ( M_AXI_ACP_ARREADY ),
.xillybus_M_AXI_ARVALID ( M_AXI_ACP_ARVALID ),
.xillybus_M_AXI_ARADDR ( M_AXI_ACP_ARADDR ),
.xillybus_M_AXI_ARLEN ( M_AXI_ACP_ARLEN ),
.xillybus_M_AXI_ARSIZE ( M_AXI_ACP_ARSIZE ),
.xillybus_M_AXI_ARBURST ( M_AXI_ACP_ARBURST ),
.xillybus_M_AXI_ARPROT ( M_AXI_ACP_ARPROT ),
.xillybus_M_AXI_ARCACHE ( M_AXI_ACP_ARCACHE ),
.xillybus_M_AXI_RREADY ( M_AXI_ACP_RREADY ),
.xillybus_M_AXI_RVALID ( M_AXI_ACP_RVALID ),
.xillybus_M_AXI_RDATA ( M_AXI_ACP_RDATA ),
.xillybus_M_AXI_RRESP ( M_AXI_ACP_RRESP ),
.xillybus_M_AXI_RLAST ( M_AXI_ACP_RLAST ),
.xillybus_M_AXI_AWREADY ( M_AXI_ACP_AWREADY ),
.xillybus_M_AXI_AWVALID ( M_AXI_ACP_AWVALID ),
.xillybus_M_AXI_AWADDR ( M_AXI_ACP_AWADDR ),
.xillybus_M_AXI_AWLEN ( M_AXI_ACP_AWLEN ),
.xillybus_M_AXI_AWSIZE ( M_AXI_ACP_AWSIZE ),
.xillybus_M_AXI_AWBURST ( M_AXI_ACP_AWBURST ),
.xillybus_M_AXI_AWPROT ( M_AXI_ACP_AWPROT ),
.xillybus_M_AXI_AWCACHE ( M_AXI_ACP_AWCACHE ),
.xillybus_M_AXI_WREADY ( M_AXI_ACP_WREADY ),
.xillybus_M_AXI_WVALID ( M_AXI_ACP_WVALID ),
.xillybus_M_AXI_WDATA ( M_AXI_ACP_WDATA ),
.xillybus_M_AXI_WSTRB ( M_AXI_ACP_WSTRB ),
.xillybus_M_AXI_WLAST ( M_AXI_ACP_WLAST ),
.xillybus_M_AXI_BREADY ( M_AXI_ACP_BREADY ),
.xillybus_M_AXI_BVALID ( M_AXI_ACP_BVALID ),
.xillybus_M_AXI_BRESP ( M_AXI_ACP_BRESP ),
.xillybus_host_interrupt ( host_interrupt ),
.xillyvga_0_clk_in ( clk_100 ),
.xillyvga_0_vga_hsync ( vga_hsync_w ),
.xillyvga_0_vga_vsync ( vga_vsync_w ),
.xillyvga_0_vga_de ( ), // For use with DVI
.xillyvga_0_vga_red ( xillyvga_0_vga_red ),
.xillyvga_0_vga_green ( xillyvga_0_vga_green ),
.xillyvga_0_vga_blue ( xillyvga_0_vga_blue ),
.xillyvga_0_vga_clk(vga_clk),
.xillybus_lite_0_user_clk_pin ( user_clk ),
.xillybus_lite_0_user_wren_pin ( user_wren ),
.xillybus_lite_0_user_wstrb_pin ( user_wstrb ),
.xillybus_lite_0_user_rden_pin ( user_rden ),
.xillybus_lite_0_user_rd_data_pin ( user_rd_data ),
.xillybus_lite_0_user_wr_data_pin ( user_wr_data ),
.xillybus_lite_0_user_addr_pin ( user_addr ),
.xillybus_lite_0_user_irq_pin ( user_irq )
);
xillybus_core xillybus_core_ins(.user_r_mem_8_rden_w(user_r_mem_8_rden),
.user_r_mem_8_data_w(user_r_mem_8_data), .user_r_mem_8_empty_w(user_r_mem_8_empty),
.user_r_mem_8_eof_w(user_r_mem_8_eof), .user_r_mem_8_open_w(user_r_mem_8_open),
.user_w_mem_8_wren_w(user_w_mem_8_wren), .user_w_mem_8_data_w(user_w_mem_8_data),
.user_w_mem_8_full_w(user_w_mem_8_full), .user_w_mem_8_open_w(user_w_mem_8_open),
.user_mem_8_addr_w(user_mem_8_addr), .user_mem_8_addr_update_w(user_mem_8_addr_update),
.GPIO_LED_w(GPIO_LED), .bus_clk_w(bus_clk), .bus_rst_n_w(bus_rst_n),
.S_AXI_AWADDR_w(S_AXI_AWADDR), .S_AXI_AWVALID_w(S_AXI_AWVALID),
.S_AXI_WDATA_w(S_AXI_WDATA), .quiesce_w(quiesce),
.S_AXI_WSTRB_w(S_AXI_WSTRB), .S_AXI_WVALID_w(S_AXI_WVALID),
.S_AXI_BREADY_w(S_AXI_BREADY), .S_AXI_ARADDR_w(S_AXI_ARADDR),
.S_AXI_ARVALID_w(S_AXI_ARVALID), .S_AXI_RREADY_w(S_AXI_RREADY),
.S_AXI_ARREADY_w(S_AXI_ARREADY), .S_AXI_RDATA_w(S_AXI_RDATA),
.S_AXI_RRESP_w(S_AXI_RRESP), .S_AXI_RVALID_w(S_AXI_RVALID),
.S_AXI_WREADY_w(S_AXI_WREADY), .S_AXI_BRESP_w(S_AXI_BRESP),
.S_AXI_BVALID_w(S_AXI_BVALID), .S_AXI_AWREADY_w(S_AXI_AWREADY),
.M_AXI_ACP_ARREADY_w(M_AXI_ACP_ARREADY), .M_AXI_ACP_ARVALID_w(M_AXI_ACP_ARVALID),
.M_AXI_ACP_ARADDR_w(M_AXI_ACP_ARADDR), .M_AXI_ACP_ARLEN_w(M_AXI_ACP_ARLEN),
.M_AXI_ACP_ARSIZE_w(M_AXI_ACP_ARSIZE), .M_AXI_ACP_ARBURST_w(M_AXI_ACP_ARBURST),
.M_AXI_ACP_ARPROT_w(M_AXI_ACP_ARPROT), .M_AXI_ACP_ARCACHE_w(M_AXI_ACP_ARCACHE),
.M_AXI_ACP_RREADY_w(M_AXI_ACP_RREADY), .M_AXI_ACP_RVALID_w(M_AXI_ACP_RVALID),
.M_AXI_ACP_RDATA_w(M_AXI_ACP_RDATA), .user_r_smb_rden_w(user_r_smb_rden),
.user_r_smb_data_w(user_r_smb_data), .user_r_smb_empty_w(user_r_smb_empty),
.user_r_smb_eof_w(user_r_smb_eof), .M_AXI_ACP_RRESP_w(M_AXI_ACP_RRESP),
.user_r_smb_open_w(user_r_smb_open), .M_AXI_ACP_RLAST_w(M_AXI_ACP_RLAST),
.M_AXI_ACP_AWREADY_w(M_AXI_ACP_AWREADY), .M_AXI_ACP_AWVALID_w(M_AXI_ACP_AWVALID),
.M_AXI_ACP_AWADDR_w(M_AXI_ACP_AWADDR), .M_AXI_ACP_AWLEN_w(M_AXI_ACP_AWLEN),
.M_AXI_ACP_AWSIZE_w(M_AXI_ACP_AWSIZE), .user_w_smb_wren_w(user_w_smb_wren),
.user_w_smb_data_w(user_w_smb_data), .user_w_smb_full_w(user_w_smb_full),
.user_w_smb_open_w(user_w_smb_open), .M_AXI_ACP_AWBURST_w(M_AXI_ACP_AWBURST),
.M_AXI_ACP_AWPROT_w(M_AXI_ACP_AWPROT), .M_AXI_ACP_AWCACHE_w(M_AXI_ACP_AWCACHE),
.M_AXI_ACP_WREADY_w(M_AXI_ACP_WREADY), .user_r_audio_rden_w(user_r_audio_rden),
.user_r_audio_data_w(user_r_audio_data), .user_r_audio_empty_w(user_r_audio_empty),
.user_r_audio_eof_w(user_r_audio_eof), .M_AXI_ACP_WVALID_w(M_AXI_ACP_WVALID),
.user_r_audio_open_w(user_r_audio_open), .M_AXI_ACP_WDATA_w(M_AXI_ACP_WDATA),
.M_AXI_ACP_WSTRB_w(M_AXI_ACP_WSTRB), .M_AXI_ACP_WLAST_w(M_AXI_ACP_WLAST),
.M_AXI_ACP_BREADY_w(M_AXI_ACP_BREADY), .M_AXI_ACP_BVALID_w(M_AXI_ACP_BVALID),
.M_AXI_ACP_BRESP_w(M_AXI_ACP_BRESP), .user_w_audio_wren_w(user_w_audio_wren),
.user_w_audio_data_w(user_w_audio_data), .user_w_audio_full_w(user_w_audio_full),
.host_interrupt_w(host_interrupt), .user_w_audio_open_w(user_w_audio_open),
.user_r_read_32_rden_w(user_r_read_32_rden), .user_r_read_32_data_w(user_r_read_32_data),
.user_r_read_32_empty_w(user_r_read_32_empty),
.user_r_read_32_eof_w(user_r_read_32_eof), .user_r_read_32_open_w(user_r_read_32_open),
.user_w_write_32_wren_w(user_w_write_32_wren),
.user_w_write_32_data_w(user_w_write_32_data),
.user_w_write_32_full_w(user_w_write_32_full),
.user_w_write_32_open_w(user_w_write_32_open),
.user_r_read_8_rden_w(user_r_read_8_rden), .user_r_read_8_data_w(user_r_read_8_data),
.user_r_read_8_empty_w(user_r_read_8_empty), .user_r_read_8_eof_w(user_r_read_8_eof),
.user_r_read_8_open_w(user_r_read_8_open), .user_w_write_8_wren_w(user_w_write_8_wren),
.user_w_write_8_data_w(user_w_write_8_data), .user_w_write_8_full_w(user_w_write_8_full),
.user_w_write_8_open_w(user_w_write_8_open));
endmodule

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module xillybus_core
(
input M_AXI_ACP_ARREADY_w,
input M_AXI_ACP_AWREADY_w,
input [1:0] M_AXI_ACP_BRESP_w,
input M_AXI_ACP_BVALID_w,
input [63:0] M_AXI_ACP_RDATA_w,
input M_AXI_ACP_RLAST_w,
input [1:0] M_AXI_ACP_RRESP_w,
input M_AXI_ACP_RVALID_w,
input M_AXI_ACP_WREADY_w,
input [31:0] S_AXI_ARADDR_w,
input S_AXI_ARVALID_w,
input [31:0] S_AXI_AWADDR_w,
input S_AXI_AWVALID_w,
input S_AXI_BREADY_w,
input S_AXI_RREADY_w,
input [31:0] S_AXI_WDATA_w,
input [3:0] S_AXI_WSTRB_w,
input S_AXI_WVALID_w,
input bus_clk_w,
input bus_rst_n_w,
input [31:0] user_r_audio_data_w,
input user_r_audio_empty_w,
input user_r_audio_eof_w,
input [7:0] user_r_mem_8_data_w,
input user_r_mem_8_empty_w,
input user_r_mem_8_eof_w,
input [31:0] user_r_read_32_data_w,
input user_r_read_32_empty_w,
input user_r_read_32_eof_w,
input [7:0] user_r_read_8_data_w,
input user_r_read_8_empty_w,
input user_r_read_8_eof_w,
input [7:0] user_r_smb_data_w,
input user_r_smb_empty_w,
input user_r_smb_eof_w,
input user_w_audio_full_w,
input user_w_mem_8_full_w,
input user_w_smb_full_w,
input user_w_write_32_full_w,
input user_w_write_8_full_w,
output [3:0] GPIO_LED_w,
output [31:0] M_AXI_ACP_ARADDR_w,
output [1:0] M_AXI_ACP_ARBURST_w,
output [3:0] M_AXI_ACP_ARCACHE_w,
output [3:0] M_AXI_ACP_ARLEN_w,
output [2:0] M_AXI_ACP_ARPROT_w,
output [2:0] M_AXI_ACP_ARSIZE_w,
output M_AXI_ACP_ARVALID_w,
output [31:0] M_AXI_ACP_AWADDR_w,
output [1:0] M_AXI_ACP_AWBURST_w,
output [3:0] M_AXI_ACP_AWCACHE_w,
output [3:0] M_AXI_ACP_AWLEN_w,
output [2:0] M_AXI_ACP_AWPROT_w,
output [2:0] M_AXI_ACP_AWSIZE_w,
output M_AXI_ACP_AWVALID_w,
output M_AXI_ACP_BREADY_w,
output M_AXI_ACP_RREADY_w,
output [63:0] M_AXI_ACP_WDATA_w,
output M_AXI_ACP_WLAST_w,
output [7:0] M_AXI_ACP_WSTRB_w,
output M_AXI_ACP_WVALID_w,
output S_AXI_ARREADY_w,
output S_AXI_AWREADY_w,
output [1:0] S_AXI_BRESP_w,
output S_AXI_BVALID_w,
output [31:0] S_AXI_RDATA_w,
output [1:0] S_AXI_RRESP_w,
output S_AXI_RVALID_w,
output S_AXI_WREADY_w,
output host_interrupt_w,
output quiesce_w,
output user_mem_8_addr_update_w,
output [4:0] user_mem_8_addr_w,
output user_r_audio_open_w,
output user_r_audio_rden_w,
output user_r_mem_8_open_w,
output user_r_mem_8_rden_w,
output user_r_read_32_open_w,
output user_r_read_32_rden_w,
output user_r_read_8_open_w,
output user_r_read_8_rden_w,
output user_r_smb_open_w,
output user_r_smb_rden_w,
output [31:0] user_w_audio_data_w,
output user_w_audio_open_w,
output user_w_audio_wren_w,
output [7:0] user_w_mem_8_data_w,
output user_w_mem_8_open_w,
output user_w_mem_8_wren_w,
output [7:0] user_w_smb_data_w,
output user_w_smb_open_w,
output user_w_smb_wren_w,
output [31:0] user_w_write_32_data_w,
output user_w_write_32_open_w,
output user_w_write_32_wren_w,
output [7:0] user_w_write_8_data_w,
output user_w_write_8_open_w,
output user_w_write_8_wren_w
);
endmodule

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NET "clk_100" TNM_NET = "TN_gclk";
TIMESPEC "TS_gclk" = PERIOD "TN_gclk" 10 ns HIGH 50 %;
# The VGA outputs are turned into an analog voltage by virtue of a resistor
# network, so the flip flops driving these must sit in the IOBs to minimize
# timing skew. The RTL code should handle this, but the constraint below
# is there to fail if something goes wrong about this.
INST "xillybus_ins/vga_iob_ff[*]" TNM = "tgrp_vga_pads_ffs";
TIMESPEC "TS_force_iob_ffs" = FROM "tgrp_vga_pads_ffs" 5.5 ns ;
NET "clk_100" LOC = Y9 | IOSTANDARD=LVCMOS33; # "GCLK"
NET "GPIO_LED[0]" LOC = T22 | IOSTANDARD=LVCMOS33; # "LD0"
NET "GPIO_LED[1]" LOC = T21 | IOSTANDARD=LVCMOS33; # "LD1"
NET "GPIO_LED[2]" LOC = U22 | IOSTANDARD=LVCMOS33; # "LD2"
NET "GPIO_LED[3]" LOC = U21 | IOSTANDARD=LVCMOS33; # "LD3"
NET "vga4_blue[0]" LOC = Y21 | IOSTANDARD=LVCMOS33; # "VGA-B1"
NET "vga4_blue[1]" LOC = Y20 | IOSTANDARD=LVCMOS33; # "VGA-B2"
NET "vga4_blue[2]" LOC = AB20 | IOSTANDARD=LVCMOS33; # "VGA-B3"
NET "vga4_blue[3]" LOC = AB19 | IOSTANDARD=LVCMOS33; # "VGA-B4"
NET "vga4_green[0]" LOC = AB22 | IOSTANDARD=LVCMOS33; # "VGA-G1"
NET "vga4_green[1]" LOC = AA22 | IOSTANDARD=LVCMOS33; # "VGA-G2"
NET "vga4_green[2]" LOC = AB21 | IOSTANDARD=LVCMOS33; # "VGA-G3"
NET "vga4_green[3]" LOC = AA21 | IOSTANDARD=LVCMOS33; # "VGA-G4"
NET "vga4_red[0]" LOC = V20 | IOSTANDARD=LVCMOS33; # "VGA-R1"
NET "vga4_red[1]" LOC = U20 | IOSTANDARD=LVCMOS33; # "VGA-R2"
NET "vga4_red[2]" LOC = V19 | IOSTANDARD=LVCMOS33; # "VGA-R3"
NET "vga4_red[3]" LOC = V18 | IOSTANDARD=LVCMOS33; # "VGA-R4"
NET "vga_vsync" LOC = Y19 | IOSTANDARD=LVCMOS33; # "VGA-VS"
NET "vga_hsync" LOC = AA19 | IOSTANDARD=LVCMOS33; # "VGA-HS"
# IMPORTANT: Since four LEDs are taken by the Xillybus IP core, the pin
# placement doesn't match the one given by Digilent.
# GPIO pin to reset the USB OTG PHY
NET PS_GPIO[0] LOC = G17 | IOSTANDARD = LVCMOS33; # USB-Reset
# On-board OLED
NET PS_GPIO[1] LOC = U11 | IOSTANDARD = LVCMOS33; # OLED-VBAT
NET PS_GPIO[2] LOC = U12 | IOSTANDARD = LVCMOS33; # OLED-VDD
NET PS_GPIO[3] LOC = U9 | IOSTANDARD = LVCMOS33; # OLED-RES
NET PS_GPIO[4] LOC = U10 | IOSTANDARD = LVCMOS33; # OLED-DC
NET PS_GPIO[5] LOC = AB12 | IOSTANDARD = LVCMOS33; # OLED-SCLK
NET PS_GPIO[6] LOC = AA12 | IOSTANDARD = LVCMOS33; # OLED-SDIN
# On-board LEDs. Note that only for LEDs are allocated, as opposed to
# Digilent's eight, and all placements that follow are shifted by four.
# There was no other choice, as the tools don't allow unplaced PS GPIO pins.
NET PS_GPIO[7] LOC = V22 | IOSTANDARD = LVCMOS33; # LD4
NET PS_GPIO[8] LOC = W22 | IOSTANDARD = LVCMOS33; # LD5
NET PS_GPIO[9] LOC = U19 | IOSTANDARD = LVCMOS33; # LD6
NET PS_GPIO[10] LOC = U14 | IOSTANDARD = LVCMOS33; # LD7
# On-board Slide Switches
NET PS_GPIO[11] LOC = F22 | IOSTANDARD = LVCMOS33; # SW0
NET PS_GPIO[12] LOC = G22 | IOSTANDARD = LVCMOS33; # SW1
NET PS_GPIO[13] LOC = H22 | IOSTANDARD = LVCMOS33; # SW2
NET PS_GPIO[14] LOC = F21 | IOSTANDARD = LVCMOS33; # SW3
NET PS_GPIO[15] LOC = H19 | IOSTANDARD = LVCMOS33; # SW4
NET PS_GPIO[16] LOC = H18 | IOSTANDARD = LVCMOS33; # SW5
NET PS_GPIO[17] LOC = H17 | IOSTANDARD = LVCMOS33; # SW6
NET PS_GPIO[18] LOC = M15 | IOSTANDARD = LVCMOS33; # SW7
# On-board Left, Right, Up, Down, and Select Pushbuttons
NET PS_GPIO[19] LOC = N15 | IOSTANDARD = LVCMOS33; # BTNL
NET PS_GPIO[20] LOC = R18 | IOSTANDARD = LVCMOS33; # BTNR
NET PS_GPIO[21] LOC = T18 | IOSTANDARD = LVCMOS33; # BTNU
NET PS_GPIO[22] LOC = R16 | IOSTANDARD = LVCMOS33; # BTND
NET PS_GPIO[23] LOC = P16 | IOSTANDARD = LVCMOS33; # BTNS
# Pmod JA
NET PS_GPIO[24] LOC = Y11 | IOSTANDARD = LVCMOS33; # JA1
NET PS_GPIO[25] LOC = AA11 | IOSTANDARD = LVCMOS33; # JA2
NET PS_GPIO[26] LOC = Y10 | IOSTANDARD = LVCMOS33; # JA3
NET PS_GPIO[27] LOC = AA9 | IOSTANDARD = LVCMOS33; # JA4
NET PS_GPIO[28] LOC = AB11 | IOSTANDARD = LVCMOS33; # JA7
NET PS_GPIO[29] LOC = AB10 | IOSTANDARD = LVCMOS33; # JA8
NET PS_GPIO[30] LOC = AB9 | IOSTANDARD = LVCMOS33; # JA9
NET PS_GPIO[31] LOC = AA8 | IOSTANDARD = LVCMOS33; # JA10
# Pmod JB
NET PS_GPIO[32] LOC = W12 | IOSTANDARD = LVCMOS33; # JB1
NET PS_GPIO[33] LOC = W11 | IOSTANDARD = LVCMOS33; # JB2
NET PS_GPIO[34] LOC = V10 | IOSTANDARD = LVCMOS33; # JB3
NET PS_GPIO[35] LOC = W8 | IOSTANDARD = LVCMOS33; # JB4
NET PS_GPIO[36] LOC = V12 | IOSTANDARD = LVCMOS33; # JB7
NET PS_GPIO[37] LOC = W10 | IOSTANDARD = LVCMOS33; # JB8
NET PS_GPIO[38] LOC = V9 | IOSTANDARD = LVCMOS33; # JB9
NET PS_GPIO[39] LOC = V8 | IOSTANDARD = LVCMOS33; # JB10
# Pmod JC
NET PS_GPIO[40] LOC = AB7 | IOSTANDARD = LVCMOS33; # JC1_P (JC1)
NET PS_GPIO[41] LOC = AB6 | IOSTANDARD = LVCMOS33; # JC1_N (JC2)
NET PS_GPIO[42] LOC = Y4 | IOSTANDARD = LVCMOS33; # JC2_P (JC3)
NET PS_GPIO[43] LOC = AA4 | IOSTANDARD = LVCMOS33; # JC2_N (JC4)
NET PS_GPIO[44] LOC = R6 | IOSTANDARD = LVCMOS33; # JC3_P (JC7)
NET PS_GPIO[45] LOC = T6 | IOSTANDARD = LVCMOS33; # JC3_N (JC8)
NET PS_GPIO[46] LOC = T4 | IOSTANDARD = LVCMOS33; # JC4_P (JC9)
NET PS_GPIO[47] LOC = U4 | IOSTANDARD = LVCMOS33; # JC4_N (JC10)
# Pmod JD
NET PS_GPIO[48] LOC = V7 | IOSTANDARD = LVCMOS33; # JD1_P (JD1)
NET PS_GPIO[49] LOC = W7 | IOSTANDARD = LVCMOS33; # JD1_N (JD2)
NET PS_GPIO[50] LOC = V5 | IOSTANDARD = LVCMOS33; # JD2_P (JD3)
NET PS_GPIO[51] LOC = V4 | IOSTANDARD = LVCMOS33; # JD2_N (JD4)
NET PS_GPIO[52] LOC = W6 | IOSTANDARD = LVCMOS33; # JD3_P (JD7)
NET PS_GPIO[53] LOC = W5 | IOSTANDARD = LVCMOS33; # JD3_N (JD8)
NET PS_GPIO[54] LOC = U6 | IOSTANDARD = LVCMOS33; # JD4_P (JD9)
NET PS_GPIO[55] LOC = U5 | IOSTANDARD = LVCMOS33; # JD4_N (JD10)
# Pin for detecting USB OTG over-current condition
NET otg_oc LOC = L16 | IOSTANDARD="LVCMOS33";
# Pins connected to sound chip
NET smbus_addr[0] LOC = AB1 | IOSTANDARD=LVCMOS33; # "AC-ADR0"
NET smbus_addr[1] LOC = Y5 | IOSTANDARD=LVCMOS33; # "AC-ADR1"
NET smb_sclk LOC = AB4 | IOSTANDARD=LVCMOS33; # "AC-SCK"
NET smb_sdata LOC = AB5 | IOSTANDARD=LVCMOS33; # "AC-SDA"
NET audio_dac LOC = Y8 | IOSTANDARD=LVCMOS33; # "AC-GPIO0"
NET audio_adc LOC = AA7 | IOSTANDARD=LVCMOS33; # "AC-GPIO1"
NET audio_bclk LOC = AA6 | IOSTANDARD=LVCMOS33; # "AC-GPIO2"
NET audio_lrclk LOC = Y6 | IOSTANDARD=LVCMOS33; # "AC-GPIO3"
NET audio_mclk LOC = AB2 | IOSTANDARD=LVCMOS33; # "AC-MCLK"

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xillinux-syn/vhdl/src/xillydemo.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity xillydemo is
port (
-- For Vivado, delete the port declarations for PS_CLK, PS_PORB and
-- PS_SRSTB, and uncomment their declarations as signals further below.
PS_CLK : IN std_logic;
PS_PORB : IN std_logic;
PS_SRSTB : IN std_logic;
clk_100 : IN std_logic;
otg_oc : IN std_logic;
PS_GPIO : INOUT std_logic_vector(55 DOWNTO 0);
GPIO_LED : OUT std_logic_vector(3 DOWNTO 0);
vga4_blue : OUT std_logic_vector(3 DOWNTO 0);
vga4_green : OUT std_logic_vector(3 DOWNTO 0);
vga4_red : OUT std_logic_vector(3 DOWNTO 0);
vga_hsync : OUT std_logic;
vga_vsync : OUT std_logic;
audio_mclk : OUT std_logic;
audio_dac : OUT std_logic;
audio_adc : IN std_logic;
audio_bclk : IN std_logic;
audio_lrclk : IN std_logic;
smb_sclk : OUT std_logic;
smb_sdata : INOUT std_logic;
smbus_addr : OUT std_logic_vector(1 DOWNTO 0));
end xillydemo;
architecture sample_arch of xillydemo is
component xillybus
port (
PS_CLK : IN std_logic;
PS_PORB : IN std_logic;
PS_SRSTB : IN std_logic;
clk_100 : IN std_logic;
otg_oc : IN std_logic;
DDR_Addr : INOUT std_logic_vector(14 DOWNTO 0);
DDR_BankAddr : INOUT std_logic_vector(2 DOWNTO 0);
DDR_CAS_n : INOUT std_logic;
DDR_CKE : INOUT std_logic;
DDR_CS_n : INOUT std_logic;
DDR_Clk : INOUT std_logic;
DDR_Clk_n : INOUT std_logic;
DDR_DM : INOUT std_logic_vector(3 DOWNTO 0);
DDR_DQ : INOUT std_logic_vector(31 DOWNTO 0);
DDR_DQS : INOUT std_logic_vector(3 DOWNTO 0);
DDR_DQS_n : INOUT std_logic_vector(3 DOWNTO 0);
DDR_DRSTB : INOUT std_logic;
DDR_ODT : INOUT std_logic;
DDR_RAS_n : INOUT std_logic;
DDR_VRN : INOUT std_logic;
DDR_VRP : INOUT std_logic;
MIO : INOUT std_logic_vector(53 DOWNTO 0);
PS_GPIO : INOUT std_logic_vector(55 DOWNTO 0);
DDR_WEB : OUT std_logic;
GPIO_LED : OUT std_logic_vector(3 DOWNTO 0);
bus_clk : OUT std_logic;
quiesce : OUT std_logic;
vga4_blue : OUT std_logic_vector(3 DOWNTO 0);
vga4_green : OUT std_logic_vector(3 DOWNTO 0);
vga4_red : OUT std_logic_vector(3 DOWNTO 0);
vga_hsync : OUT std_logic;
vga_vsync : OUT std_logic;
user_r_mem_8_rden : OUT std_logic;
user_r_mem_8_empty : IN std_logic;
user_r_mem_8_data : IN std_logic_vector(7 DOWNTO 0);
user_r_mem_8_eof : IN std_logic;
user_r_mem_8_open : OUT std_logic;
user_w_mem_8_wren : OUT std_logic;
user_w_mem_8_full : IN std_logic;
user_w_mem_8_data : OUT std_logic_vector(7 DOWNTO 0);
user_w_mem_8_open : OUT std_logic;
user_mem_8_addr : OUT std_logic_vector(4 DOWNTO 0);
user_mem_8_addr_update : OUT std_logic;
user_r_read_32_rden : OUT std_logic;
user_r_read_32_empty : IN std_logic;
user_r_read_32_data : IN std_logic_vector(31 DOWNTO 0);
user_r_read_32_eof : IN std_logic;
user_r_read_32_open : OUT std_logic;
user_r_read_8_rden : OUT std_logic;
user_r_read_8_empty : IN std_logic;
user_r_read_8_data : IN std_logic_vector(7 DOWNTO 0);
user_r_read_8_eof : IN std_logic;
user_r_read_8_open : OUT std_logic;
user_w_write_32_wren : OUT std_logic;
user_w_write_32_full : IN std_logic;
user_w_write_32_data : OUT std_logic_vector(31 DOWNTO 0);
user_w_write_32_open : OUT std_logic;
user_w_write_8_wren : OUT std_logic;
user_w_write_8_full : IN std_logic;
user_w_write_8_data : OUT std_logic_vector(7 DOWNTO 0);
user_w_write_8_open : OUT std_logic;
user_r_audio_rden : OUT std_logic;
user_r_audio_empty : IN std_logic;
user_r_audio_data : IN std_logic_vector(31 DOWNTO 0);
user_r_audio_eof : IN std_logic;
user_r_audio_open : OUT std_logic;
user_w_audio_wren : OUT std_logic;
user_w_audio_full : IN std_logic;
user_w_audio_data : OUT std_logic_vector(31 DOWNTO 0);
user_w_audio_open : OUT std_logic;
user_r_smb_rden : OUT std_logic;
user_r_smb_empty : IN std_logic;
user_r_smb_data : IN std_logic_vector(7 DOWNTO 0);
user_r_smb_eof : IN std_logic;
user_r_smb_open : OUT std_logic;
user_w_smb_wren : OUT std_logic;
user_w_smb_full : IN std_logic;
user_w_smb_data : OUT std_logic_vector(7 DOWNTO 0);
user_w_smb_open : OUT std_logic;
user_clk : OUT std_logic;
user_wren : OUT std_logic;
user_wstrb : OUT std_logic_vector(3 DOWNTO 0);
user_rden : OUT std_logic;
user_rd_data : IN std_logic_vector(31 DOWNTO 0);
user_wr_data : OUT std_logic_vector(31 DOWNTO 0);
user_addr : OUT std_logic_vector(31 DOWNTO 0);
user_irq : IN std_logic);
end component;
component fifo_8x2048
port (
clk: IN std_logic;
srst: IN std_logic;
din: IN std_logic_VECTOR(7 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
full: OUT std_logic;
empty: OUT std_logic);
end component;
component fifo_32x512
port (
clk: IN std_logic;
srst: IN std_logic;
din: IN std_logic_VECTOR(31 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(31 downto 0);
full: OUT std_logic;
empty: OUT std_logic);
end component;
component i2s_audio
port (
bus_clk : IN std_logic;
clk_100 : IN std_logic;
quiesce : IN std_logic;
audio_mclk : OUT std_logic;
audio_dac : OUT std_logic;
audio_adc : IN std_logic;
audio_bclk : IN std_logic;
audio_lrclk : IN std_logic;
user_r_audio_rden : IN std_logic;
user_r_audio_empty : OUT std_logic;
user_r_audio_data : OUT std_logic_vector(31 DOWNTO 0);
user_r_audio_eof : OUT std_logic;
user_r_audio_open : IN std_logic;
user_w_audio_wren : IN std_logic;
user_w_audio_full : OUT std_logic;
user_w_audio_data : IN std_logic_vector(31 DOWNTO 0);
user_w_audio_open : IN std_logic);
end component;
component smbus
port (
bus_clk : IN std_logic;
quiesce : IN std_logic;
smb_sclk : OUT std_logic;
smb_sdata : INOUT std_logic;
smbus_addr : OUT std_logic_vector(1 DOWNTO 0);
user_r_smb_rden : IN std_logic;
user_r_smb_empty : OUT std_logic;
user_r_smb_data : OUT std_logic_vector(7 DOWNTO 0);
user_r_smb_eof : OUT std_logic;
user_r_smb_open : IN std_logic;
user_w_smb_wren : IN std_logic;
user_w_smb_full : OUT std_logic;
user_w_smb_data : IN std_logic_vector(7 DOWNTO 0);
user_w_smb_open : IN std_logic);
end component;
-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of fifo_32x512: component is true;
attribute syn_black_box of fifo_8x2048: component is true;
type demo_mem is array(0 TO 31) of std_logic_vector(7 DOWNTO 0);
signal demoarray : demo_mem;
signal litearray0 : demo_mem;
signal litearray1 : demo_mem;
signal litearray2 : demo_mem;
signal litearray3 : demo_mem;
signal bus_clk : std_logic;
signal quiesce : std_logic;
signal reset_8 : std_logic;
signal reset_32 : std_logic;
signal ram_addr : integer range 0 to 31;
signal lite_addr : integer range 0 to 31;
signal user_r_mem_8_rden : std_logic;
signal user_r_mem_8_empty : std_logic;
signal user_r_mem_8_data : std_logic_vector(7 DOWNTO 0);
signal user_r_mem_8_eof : std_logic;
signal user_r_mem_8_open : std_logic;
signal user_w_mem_8_wren : std_logic;
signal user_w_mem_8_full : std_logic;
signal user_w_mem_8_data : std_logic_vector(7 DOWNTO 0);
signal user_w_mem_8_open : std_logic;
signal user_mem_8_addr : std_logic_vector(4 DOWNTO 0);
signal user_mem_8_addr_update : std_logic;
signal user_r_read_32_rden : std_logic;
signal user_r_read_32_empty : std_logic;
signal user_r_read_32_data : std_logic_vector(31 DOWNTO 0);
signal user_r_read_32_eof : std_logic;
signal user_r_read_32_open : std_logic;
signal user_r_read_8_rden : std_logic;
signal user_r_read_8_empty : std_logic;
signal user_r_read_8_data : std_logic_vector(7 DOWNTO 0);
signal user_r_read_8_eof : std_logic;
signal user_r_read_8_open : std_logic;
signal user_w_write_32_wren : std_logic;
signal user_w_write_32_full : std_logic;
signal user_w_write_32_data : std_logic_vector(31 DOWNTO 0);
signal user_w_write_32_open : std_logic;
signal user_w_write_8_wren : std_logic;
signal user_w_write_8_full : std_logic;
signal user_w_write_8_data : std_logic_vector(7 DOWNTO 0);
signal user_w_write_8_open : std_logic;
signal user_r_audio_rden : std_logic;
signal user_r_audio_empty : std_logic;
signal user_r_audio_data : std_logic_vector(31 DOWNTO 0);
signal user_r_audio_eof : std_logic;
signal user_r_audio_open : std_logic;
signal user_w_audio_wren : std_logic;
signal user_w_audio_full : std_logic;
signal user_w_audio_data : std_logic_vector(31 DOWNTO 0);
signal user_w_audio_open : std_logic;
signal user_r_smb_rden : std_logic;
signal user_r_smb_empty : std_logic;
signal user_r_smb_data : std_logic_vector(7 DOWNTO 0);
signal user_r_smb_eof : std_logic;
signal user_r_smb_open : std_logic;
signal user_w_smb_wren : std_logic;
signal user_w_smb_full : std_logic;
signal user_w_smb_data : std_logic_vector(7 DOWNTO 0);
signal user_w_smb_open : std_logic;
signal user_clk : std_logic;
signal user_wren : std_logic;
signal user_wstrb : std_logic_vector(3 DOWNTO 0);
signal user_rden : std_logic;
signal user_rd_data : std_logic_vector(31 DOWNTO 0);
signal user_wr_data : std_logic_vector(31 DOWNTO 0);
signal user_addr : std_logic_vector(31 DOWNTO 0);
signal user_irq : std_logic;
-- Note that none of the ARM processor's direct connections to pads is
-- defined as I/O on this module. Normally, they should be connected
-- as toplevel ports here, but that confuses Vivado 2013.4 to think that
-- some of these ports are real I/Os, causing an implementation failure.
-- This detachment results in a lot of warnings during synthesis and
-- implementation, but has no practical significance, as these pads are
-- completely unrelated to the FPGA bitstream.
-- signal PS_CLK : std_logic;
-- signal PS_PORB : std_logic;
-- signal PS_SRSTB : std_logic;
signal DDR_Addr : std_logic_vector(14 DOWNTO 0);
signal DDR_BankAddr : std_logic_vector(2 DOWNTO 0);
signal DDR_CAS_n : std_logic;
signal DDR_CKE : std_logic;
signal DDR_CS_n : std_logic;
signal DDR_Clk : std_logic;
signal DDR_Clk_n : std_logic;
signal DDR_DM : std_logic_vector(3 DOWNTO 0);
signal DDR_DQ : std_logic_vector(31 DOWNTO 0);
signal DDR_DQS : std_logic_vector(3 DOWNTO 0);
signal DDR_DQS_n : std_logic_vector(3 DOWNTO 0);
signal DDR_DRSTB : std_logic;
signal DDR_ODT : std_logic;
signal DDR_RAS_n : std_logic;
signal DDR_VRN : std_logic;
signal DDR_VRP : std_logic;
signal MIO : std_logic_vector(53 DOWNTO 0);
signal DDR_WEB : std_logic;
begin
xillybus_ins : xillybus
port map (
-- Ports related to /dev/xillybus_mem_8
-- FPGA to CPU signals:
user_r_mem_8_rden => user_r_mem_8_rden,
user_r_mem_8_empty => user_r_mem_8_empty,
user_r_mem_8_data => user_r_mem_8_data,
user_r_mem_8_eof => user_r_mem_8_eof,
user_r_mem_8_open => user_r_mem_8_open,
-- CPU to FPGA signals:
user_w_mem_8_wren => user_w_mem_8_wren,
user_w_mem_8_full => user_w_mem_8_full,
user_w_mem_8_data => user_w_mem_8_data,
user_w_mem_8_open => user_w_mem_8_open,
-- Address signals:
user_mem_8_addr => user_mem_8_addr,
user_mem_8_addr_update => user_mem_8_addr_update,
-- Ports related to /dev/xillybus_read_32
-- FPGA to CPU signals:
user_r_read_32_rden => user_r_read_32_rden,
user_r_read_32_empty => user_r_read_32_empty,
user_r_read_32_data => user_r_read_32_data,
user_r_read_32_eof => user_r_read_32_eof,
user_r_read_32_open => user_r_read_32_open,
-- Ports related to /dev/xillybus_read_8
-- FPGA to CPU signals:
user_r_read_8_rden => user_r_read_8_rden,
user_r_read_8_empty => user_r_read_8_empty,
user_r_read_8_data => user_r_read_8_data,
user_r_read_8_eof => user_r_read_8_eof,
user_r_read_8_open => user_r_read_8_open,
-- Ports related to /dev/xillybus_write_32
-- CPU to FPGA signals:
user_w_write_32_wren => user_w_write_32_wren,
user_w_write_32_full => user_w_write_32_full,
user_w_write_32_data => user_w_write_32_data,
user_w_write_32_open => user_w_write_32_open,
-- Ports related to /dev/xillybus_write_8
-- CPU to FPGA signals:
user_w_write_8_wren => user_w_write_8_wren,
user_w_write_8_full => user_w_write_8_full,
user_w_write_8_data => user_w_write_8_data,
user_w_write_8_open => user_w_write_8_open,
-- Ports related to Xillybus Lite
user_clk => user_clk,
user_wren => user_wren,
user_wstrb => user_wstrb,
user_rden => user_rden,
user_rd_data => user_rd_data,
user_wr_data => user_wr_data,
user_addr => user_addr,
user_irq => user_irq,
-- Ports related to /dev/xillybus_audio
-- FPGA to CPU signals:
user_r_audio_rden => user_r_audio_rden,
user_r_audio_empty => user_r_audio_empty,
user_r_audio_data => user_r_audio_data,
user_r_audio_eof => user_r_audio_eof,
user_r_audio_open => user_r_audio_open,
-- CPU to FPGA signals:
user_w_audio_wren => user_w_audio_wren,
user_w_audio_full => user_w_audio_full,
user_w_audio_data => user_w_audio_data,
user_w_audio_open => user_w_audio_open,
-- Ports related to /dev/xillybus_smb
-- FPGA to CPU signals:
user_r_smb_rden => user_r_smb_rden,
user_r_smb_empty => user_r_smb_empty,
user_r_smb_data => user_r_smb_data,
user_r_smb_eof => user_r_smb_eof,
user_r_smb_open => user_r_smb_open,
-- CPU to FPGA signals:
user_w_smb_wren => user_w_smb_wren,
user_w_smb_full => user_w_smb_full,
user_w_smb_data => user_w_smb_data,
user_w_smb_open => user_w_smb_open,
-- General signals
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
clk_100 => clk_100,
otg_oc => otg_oc,
DDR_Addr => DDR_Addr,
DDR_BankAddr => DDR_BankAddr,
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM => DDR_DM,
DDR_DQ => DDR_DQ,
DDR_DQS => DDR_DQS,
DDR_DQS_n => DDR_DQS_n,
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
MIO => MIO,
PS_GPIO => PS_GPIO,
DDR_WEB => DDR_WEB,
GPIO_LED => GPIO_LED,
bus_clk => bus_clk,
quiesce => quiesce,
vga4_blue => vga4_blue,
vga4_green => vga4_green,
vga4_red => vga4_red,
vga_hsync => vga_hsync,
vga_vsync => vga_vsync
);
-- Xillybus Lite
user_irq <= '0'; -- No interrupts for now
lite_addr <= conv_integer(user_addr(6 DOWNTO 2));
process (user_clk)
begin
if (user_clk'event and user_clk = '1') then
if (user_wstrb(0) = '1') then
litearray0(lite_addr) <= user_wr_data(7 DOWNTO 0);
end if;
if (user_wstrb(1) = '1') then
litearray1(lite_addr) <= user_wr_data(15 DOWNTO 8);
end if;
if (user_wstrb(2) = '1') then
litearray2(lite_addr) <= user_wr_data(23 DOWNTO 16);
end if;
if (user_wstrb(3) = '1') then
litearray3(lite_addr) <= user_wr_data(31 DOWNTO 24);
end if;
if (user_rden = '1') then
user_rd_data <= litearray3(lite_addr) & litearray2(lite_addr) &
litearray1(lite_addr) & litearray0(lite_addr);
end if;
end if;
end process;
-- A simple inferred RAM
ram_addr <= conv_integer(user_mem_8_addr);
process (bus_clk)
begin
if (bus_clk'event and bus_clk = '1') then
if (user_w_mem_8_wren = '1') then
demoarray(ram_addr) <= user_w_mem_8_data;
end if;
if (user_r_mem_8_rden = '1') then
user_r_mem_8_data <= demoarray(ram_addr);
end if;
end if;
end process;
user_r_mem_8_empty <= '0';
user_r_mem_8_eof <= '0';
user_w_mem_8_full <= '0';
-- 32-bit loopback
fifo_32 : fifo_32x512
port map(
clk => bus_clk,
srst => reset_32,
din => user_w_write_32_data,
wr_en => user_w_write_32_wren,
rd_en => user_r_read_32_rden,
dout => user_r_read_32_data,
full => user_w_write_32_full,
empty => user_r_read_32_empty
);
reset_32 <= not (user_w_write_32_open or user_r_read_32_open);
user_r_read_32_eof <= '0';
-- 8-bit loopback
fifo_8 : fifo_8x2048
port map(
clk => bus_clk,
srst => reset_8,
din => user_w_write_8_data,
wr_en => user_w_write_8_wren,
rd_en => user_r_read_8_rden,
dout => user_r_read_8_data,
full => user_w_write_8_full,
empty => user_r_read_8_empty
);
reset_8 <= not (user_w_write_8_open or user_r_read_8_open);
user_r_read_8_eof <= '0';
audio_ins : i2s_audio
port map(
bus_clk => bus_clk,
clk_100 => clk_100,
quiesce => quiesce,
audio_mclk => audio_mclk,
audio_dac => audio_dac,
audio_adc => audio_adc,
audio_bclk => audio_bclk,
audio_lrclk => audio_lrclk,
user_r_audio_rden => user_r_audio_rden,
user_r_audio_empty => user_r_audio_empty,
user_r_audio_data => user_r_audio_data,
user_r_audio_eof => user_r_audio_eof,
user_r_audio_open => user_r_audio_open,
user_w_audio_wren => user_w_audio_wren,
user_w_audio_full => user_w_audio_full,
user_w_audio_data => user_w_audio_data,
user_w_audio_open => user_w_audio_open
);
smbus_ins : smbus
port map(
bus_clk => bus_clk,
quiesce => quiesce,
smb_sclk => smb_sclk,
smb_sdata => smb_sdata,
smbus_addr => smbus_addr,
user_r_smb_rden => user_r_smb_rden,
user_r_smb_empty => user_r_smb_empty,
user_r_smb_data => user_r_smb_data,
user_r_smb_eof => user_r_smb_eof,
user_r_smb_open => user_r_smb_open,
user_w_smb_wren => user_w_smb_wren,
user_w_smb_full => user_w_smb_full,
user_w_smb_data => user_w_smb_data,
user_w_smb_open => user_w_smb_open
);
end sample_arch;

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# Xillydemo project generation script for Vivado 2014.4 and up
set origin_dir [file dirname [info script]]
if {[string first { } $origin_dir] >= 0} {
send_msg_id xillydemo-1 error "The path to the the project directory contains white space(s): \"$origin_dir\". This is known to cause problems with Vivado. Please move the project to a path without white spaces, and try again."
}
set proj_name xillydemo
set proj_dir "[file normalize $origin_dir/vivado]"
set thepart "xc7z020clg484-1"
# Set the directory for essentials for Vivado
set essentials_dir "[file normalize "$origin_dir/../vivado-essentials"]"
# Create project
create_project $proj_name "$proj_dir/"
# Set project properties
set obj [get_projects $proj_name]
set_property "default_lib" "xil_defaultlib" $obj
set_property "part" $thepart $obj
set_property "simulator_language" "Mixed" $obj
set_property "source_mgmt_mode" "DisplayOnly" $obj
set_property target_language VHDL $obj
set_property "ip_repo_paths" "$essentials_dir/vivado-ip" [current_fileset]
update_ip_catalog
# Create 'sources_1' fileset (if not found)
if {[string equal [get_filesets sources_1] ""]} {
create_fileset -srcset sources_1
}
# Set 'sources_1' fileset properties
set obj [get_filesets sources_1]
set_property "edif_extra_search_paths" "[file normalize "$origin_dir/../cores"]" $obj
set_property "top" "xillydemo" $obj
# Add files to 'sources_1' fileset
set obj [get_filesets sources_1]
set files [list \
$origin_dir/src/xillydemo.vhd \
$origin_dir/src/smbus.v \
$origin_dir/src/i2s_audio.v \
$origin_dir/src/xillybus.v \
$origin_dir/src/xillybus_core.v \
$essentials_dir/system.v \
$essentials_dir/vga_fifo/vga_fifo.xci \
$essentials_dir/fifo_8x2048/fifo_8x2048.xci \
$essentials_dir/fifo_32x512/fifo_32x512.xci \
$essentials_dir/vivado_system/vivado_system.bd \
]
add_files -norecurse -fileset $obj $files
upgrade_ip [get_ips]
# A bug in Vivado drops one slave interface on the AXI4-Lite to AXI3
# crossbar when vivado_system.bd is loaded. So AXI4-Lite slaves are
# connected with the Tcl commands below.
open_bd_design $essentials_dir/vivado_system/vivado_system.bd
startgroup
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/processing_system7_0/M_AXI_GP0" Clk "Auto" } [get_bd_intf_pins xillybus_ip_0/S_AXI]
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/processing_system7_0/M_AXI_GP0" Clk "Auto" } [get_bd_intf_pins xillyvga_0/S_AXI]
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/processing_system7_0/M_AXI_GP0" Clk "Auto" } [get_bd_intf_pins xillybus_lite_0/S_AXI]
set_property range 4K [get_bd_addr_segs {processing_system7_0/Data/SEG_xillybus_ip_0_reg0}]
set_property range 4K [get_bd_addr_segs {processing_system7_0/Data/SEG_xillyvga_0_reg0}]
set_property range 4K [get_bd_addr_segs {processing_system7_0/Data/SEG_xillybus_lite_0_reg0}]
set_property offset 0x50000000 [get_bd_addr_segs {processing_system7_0/Data/SEG_xillybus_ip_0_reg0}]
set_property offset 0x50001000 [get_bd_addr_segs {processing_system7_0/Data/SEG_xillyvga_0_reg0}]
set_property offset 0x50002000 [get_bd_addr_segs {processing_system7_0/Data/SEG_xillybus_lite_0_reg0}]
endgroup
save_bd_design
close_bd_design vivado_system
# Create 'constrs_1' fileset (if not found)
if {[string equal [get_filesets constrs_1] ""]} {
create_fileset -constrset constrs_1
}
# Add files to 'constrs_1' fileset
set obj [get_filesets constrs_1]
add_files -fileset $obj -norecurse $essentials_dir/xillydemo.xdc
# Set 'constrs_1' fileset properties
set obj [get_filesets constrs_1]
# Create 'sim_1' fileset (if not found)
if {[string equal [get_filesets sim_1] ""]} {
create_fileset -simset sim_1
}
# Add files to 'sim_1' fileset
set obj [get_filesets sim_1]
# Empty (no sources present)
# Set 'sim_1' fileset properties
set obj [get_filesets sim_1]
set_property "top" "unknown" $obj
set_property "xsim.simulate.runtime" "1000 ns" $obj
set_property "xsim.simulate.uut" "UUT" $obj
# Create 'synth_1' run (if not found)
if {[string equal [get_runs synth_1] ""]} {
create_run -name synth_1 -part $thepart -flow {Vivado Synthesis 2013} -strategy "Vivado Synthesis Defaults" -constrset constrs_1
}
set obj [get_runs synth_1]
set_property "part" $thepart $obj
# Create 'impl_1' run (if not found)
if {[string equal [get_runs impl_1] ""]} {
create_run -name impl_1 -part $thepart -flow {Vivado Implementation 2013} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1
}
set obj [get_runs impl_1]
set_property "part" $thepart $obj
set_property STEPS.ROUTE_DESIGN.TCL.POST "$essentials_dir/showstopper.tcl" $obj
# Calm down critical warnings for issues that are known to be OK
set_msg_config -new_severity "INFO" -id {BD 41-968} -string {{xillybus_S_AXI} }
set_msg_config -new_severity "INFO" -id {BD 41-968} -string {{xillybus_M_AXI} }
set_msg_config -new_severity "INFO" -id {BD 41-967} -string {{xillybus_ip_0/xillybus_M_AXI} }
set_msg_config -new_severity "INFO" -id {BD 41-967} -string {{xillybus_ip_0/xillybus_S_AXI} }
set_msg_config -new_severity "INFO" -id {BD 41-678} -string {{xillybus_S_AXI/Reg} }
set_msg_config -new_severity "INFO" -id {BD 41-1356} -string {{xillybus_S_AXI/Reg} }
set_msg_config -new_severity "INFO" -id {BD 41-759} -string {{xlconcat_0/In} }
set_msg_config -new_severity "INFO" -id {BD 41-759} -string {{xlconcat_0/In} }
set_msg_config -new_severity "INFO" -id {filemgmt 20-1440} -string {{xillybus_lite.ngc} }
# The processor's native pads are detached in the logic design to prevent
# Vivado from confusing itself. This causes a lot of critical warnings about
# meaningless contraints not being applied. So drop the warnings.
set_msg_config -new_severity "INFO" -id {Netlist 29-160} -string {{vivado_system_processing_system7} }
puts "INFO: Project created: $proj_name"
# Uncomment the two following lines for a full implementation
#launch_runs -jobs 8 impl_1 -to_step write_bitstream
#wait_on_run impl_1

388
xillinux-syn/vhdl/xillydemo.xise Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.2" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="src/system.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="src/xillydemo.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="src/xillybus.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="src/xillybus_core.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="src/fifo_32x512.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="src/fifo_8x2048.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="src/xillydemo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="src/i2s_audio.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="src/smbus.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
</files>
<properties>
<property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-1" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-1" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Cores Search Directories" xil_pn:value="../system/implementation|../cores|../runonce" xil_pn:valueState="non-default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc7z020" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Zynq" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-1" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
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<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
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</project>

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xillinux-syn/vivado-essentials/fifo_32x512/fifo_32x512.xci Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:name>unknown</spirit:name>
<spirit:version>1.0</spirit:version>
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xillinux-syn/vivado-essentials/fifo_8x2048/fifo_8x2048.xci Normal file
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
<xilinx:componentInstanceExtensions>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count_Width" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_rach" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_wach" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_wrch" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count_Width" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TDATA_NUM_BYTES" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TKEEP_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TSTRB_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count_Width" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>

28
xillinux-syn/vivado-essentials/showstopper.tcl Normal file
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# Halt the flow with an error if the timing constraints weren't met
set minireport [report_timing_summary -no_header -no_detailed_paths -return_string]
if {! [string match -nocase {*timing constraints are met*} $minireport]} {
send_msg_id showstopper-0 error "Timing constraints weren't met. Please check your design. See Timing Summary Report."
return -code error
}
if {! [string match -nocase {*There are 0 register/latch pins with no clock*} $minireport]} {
send_msg_id showstopper-1 error "There are registers with no clock. Please check your design. See Timing Summary Report."
return -code error
}
if {! [string match -nocase {*There are 0 register/latch pins with constant_clock*} $minireport]} {
send_msg_id showstopper-2 error "The design is poorly constrained: There are registers assumed to have a constant clock. Please check your design. See Timing Summary Report."
return -code error
}
if {! [string match -nocase {*There are 0 pins that are not constrained for maximum delay due to constant clock*} $minireport]} {
send_msg_id showstopper-3 error "The design is poorly constrained: There are internal endpoints that are not constrained due to a constant clock. Please check your design. See Timing Summary Report."
return -code error
}
if {! [string match -nocase {*There are 0 pins that are not constrained for maximum delay*} $minireport]} {
send_msg_id showstopper-4 error "The design is poorly constrained: There are internal endpoints that are not constrained. Please check your design. See Timing Summary Report."
return -code error
}

200
xillinux-syn/vivado-essentials/system.v Normal file
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// Wrapper for vivado_system. This matches the signals' names in XPS with
// those of Vivado.
module system (
inout [53:0] processing_system7_0_MIO,
input processing_system7_0_PS_SRSTB,
input processing_system7_0_PS_CLK,
input processing_system7_0_PS_PORB,
inout processing_system7_0_DDR_Clk,
inout processing_system7_0_DDR_Clk_n,
inout processing_system7_0_DDR_CKE,
inout processing_system7_0_DDR_CS_n,
inout processing_system7_0_DDR_RAS_n,
inout processing_system7_0_DDR_CAS_n,
output processing_system7_0_DDR_WEB,
inout [2:0] processing_system7_0_DDR_BankAddr,
inout [14:0] processing_system7_0_DDR_Addr,
inout processing_system7_0_DDR_ODT,
inout processing_system7_0_DDR_DRSTB,
inout [31:0] processing_system7_0_DDR_DQ,
inout [3:0] processing_system7_0_DDR_DM,
inout [3:0] processing_system7_0_DDR_DQS,
inout [3:0] processing_system7_0_DDR_DQS_n,
inout processing_system7_0_DDR_VRN,
inout processing_system7_0_DDR_VRP,
output xillybus_bus_clk,
output xillybus_bus_rst_n,
output [31:0] xillybus_S_AXI_AWADDR,
output xillybus_S_AXI_AWVALID,
output [31:0] xillybus_S_AXI_WDATA,
output [3:0] xillybus_S_AXI_WSTRB,
output xillybus_S_AXI_WVALID,
output xillybus_S_AXI_BREADY,
output [31:0] xillybus_S_AXI_ARADDR,
output xillybus_S_AXI_ARVALID,
output xillybus_S_AXI_RREADY,
input xillybus_S_AXI_ARREADY,
input [31:0] xillybus_S_AXI_RDATA,
input [1:0] xillybus_S_AXI_RRESP,
input xillybus_S_AXI_RVALID,
input xillybus_S_AXI_WREADY,
input [1:0] xillybus_S_AXI_BRESP,
input xillybus_S_AXI_BVALID,
input xillybus_S_AXI_AWREADY,
output xillybus_M_AXI_ARREADY,
input xillybus_M_AXI_ARVALID,
input [31:0] xillybus_M_AXI_ARADDR,
input [3:0] xillybus_M_AXI_ARLEN,
input [2:0] xillybus_M_AXI_ARSIZE,
input [1:0] xillybus_M_AXI_ARBURST,
input [2:0] xillybus_M_AXI_ARPROT,
input [3:0] xillybus_M_AXI_ARCACHE,
input xillybus_M_AXI_RREADY,
output xillybus_M_AXI_RVALID,
output [63:0] xillybus_M_AXI_RDATA,
output [1:0] xillybus_M_AXI_RRESP,
output xillybus_M_AXI_RLAST,
output xillybus_M_AXI_AWREADY,
input xillybus_M_AXI_AWVALID,
input [31:0] xillybus_M_AXI_AWADDR,
input [3:0] xillybus_M_AXI_AWLEN,
input [2:0] xillybus_M_AXI_AWSIZE,
input [1:0] xillybus_M_AXI_AWBURST,
input [2:0] xillybus_M_AXI_AWPROT,
input [3:0] xillybus_M_AXI_AWCACHE,
output xillybus_M_AXI_WREADY,
input xillybus_M_AXI_WVALID,
input [63:0] xillybus_M_AXI_WDATA,
input [7:0] xillybus_M_AXI_WSTRB,
input xillybus_M_AXI_WLAST,
input xillybus_M_AXI_BREADY,
output xillybus_M_AXI_BVALID,
output [1:0] xillybus_M_AXI_BRESP,
input xillybus_host_interrupt,
input xillyvga_0_clk_in,
output xillyvga_0_vga_hsync,
output xillyvga_0_vga_vsync,
output xillyvga_0_vga_de,
output [7:0] xillyvga_0_vga_red,
output [7:0] xillyvga_0_vga_green,
output [7:0] xillyvga_0_vga_blue,
output xillyvga_0_vga_clk,
inout [55:0] processing_system7_0_GPIO,
input processing_system7_0_USB0_VBUS_PWRFAULT,
output xillybus_lite_0_user_clk_pin,
output xillybus_lite_0_user_wren_pin,
output [3:0] xillybus_lite_0_user_wstrb_pin,
output xillybus_lite_0_user_rden_pin,
input [31:0] xillybus_lite_0_user_rd_data_pin,
output [31:0] xillybus_lite_0_user_wr_data_pin,
output [31:0] xillybus_lite_0_user_addr_pin,
input xillybus_lite_0_user_irq_pin
);
wire [55:0] gpio_tri_i, gpio_tri_o, gpio_tri_t;
genvar i;
generate
for (i=0; i<56; i=i+1)
begin: gpio
assign gpio_tri_i[i] = processing_system7_0_GPIO[i];
assign processing_system7_0_GPIO[i] = gpio_tri_t[i] ? 1'bz :
gpio_tri_o[i];
end
endgenerate
vivado_system vivado_system_i
(.DDR_addr(processing_system7_0_DDR_Addr),
.DDR_ba(processing_system7_0_DDR_BankAddr),
.DDR_cas_n(processing_system7_0_DDR_CAS_n),
.DDR_ck_n(processing_system7_0_DDR_Clk_n),
.DDR_ck_p(processing_system7_0_DDR_Clk_p),
.DDR_cke(processing_system7_0_DDR_CKE),
.DDR_cs_n(processing_system7_0_DDR_CS_n),
.DDR_dm(processing_system7_0_DDR_DM),
.DDR_dq(processing_system7_0_DDR_DQ),
.DDR_dqs_n(processing_system7_0_DDR_DQS_n),
.DDR_dqs_p(processing_system7_0_DDR_DQS),
.DDR_odt(processing_system7_0_DDR_ODT),
.DDR_ras_n(processing_system7_0_DDR_RAS_n),
.DDR_reset_n(processing_system7_0_DDR_DRSTB),
.DDR_we_n(processing_system7_0_DDR_WEB),
.FIXED_IO_ddr_vrn(processing_system7_0_DDR_VRN),
.FIXED_IO_ddr_vrp(processing_system7_0_DDR_VRP),
.FIXED_IO_mio(processing_system7_0_MIO),
.FIXED_IO_ps_clk(processing_system7_0_PS_CLK),
.FIXED_IO_ps_porb(processing_system7_0_PS_PORB),
.FIXED_IO_ps_srstb(processing_system7_0_PS_SRSTB),
.GPIO_0_tri_i(gpio_tri_i),
.GPIO_0_tri_o(gpio_tri_o),
.GPIO_0_tri_t(gpio_tri_t),
.USBIND_0_port_indctl(),
.USBIND_0_vbus_pwrfault(processing_system7_0_USB0_VBUS_PWRFAULT),
.USBIND_0_vbus_pwrselect(),
.clk_in(xillyvga_0_clk_in),
.user_addr(xillybus_lite_0_user_addr_pin),
.user_clk(xillybus_lite_0_user_clk_pin),
.user_irq(xillybus_lite_0_user_irq_pin),
.user_rd_data(xillybus_lite_0_user_rd_data_pin),
.user_rden(xillybus_lite_0_user_rden_pin),
.user_wr_data(xillybus_lite_0_user_wr_data_pin),
.user_wren(xillybus_lite_0_user_wren_pin),
.user_wstrb(xillybus_lite_0_user_wstrb_pin),
.vga_blue(xillyvga_0_vga_blue),
.vga_clk(xillyvga_0_vga_clk),
.vga_de(xillyvga_0_vga_de),
.vga_green(xillyvga_0_vga_green),
.vga_hsync(xillyvga_0_vga_hsync),
.vga_red(xillyvga_0_vga_red),
.vga_vsync(xillyvga_0_vga_vsync),
.xillybus_M_AXI_araddr(xillybus_M_AXI_ARADDR),
.xillybus_M_AXI_arburst(xillybus_M_AXI_ARBURST),
.xillybus_M_AXI_arcache(xillybus_M_AXI_ARCACHE),
.xillybus_M_AXI_arlen(xillybus_M_AXI_ARLEN),
.xillybus_M_AXI_arprot(xillybus_M_AXI_ARPROT),
.xillybus_M_AXI_arready(xillybus_M_AXI_ARREADY),
.xillybus_M_AXI_arsize(xillybus_M_AXI_ARSIZE),
.xillybus_M_AXI_arvalid(xillybus_M_AXI_ARVALID),
.xillybus_M_AXI_awaddr(xillybus_M_AXI_AWADDR),
.xillybus_M_AXI_awburst(xillybus_M_AXI_AWBURST),
.xillybus_M_AXI_awcache(xillybus_M_AXI_AWCACHE),
.xillybus_M_AXI_awlen(xillybus_M_AXI_AWLEN),
.xillybus_M_AXI_awprot(xillybus_M_AXI_AWPROT),
.xillybus_M_AXI_awready(xillybus_M_AXI_AWREADY),
.xillybus_M_AXI_awsize(xillybus_M_AXI_AWSIZE),
.xillybus_M_AXI_awvalid(xillybus_M_AXI_AWVALID),
.xillybus_M_AXI_bready(xillybus_M_AXI_BREADY),
.xillybus_M_AXI_bresp(xillybus_M_AXI_BRESP),
.xillybus_M_AXI_bvalid(xillybus_M_AXI_BVALID),
.xillybus_M_AXI_rdata(xillybus_M_AXI_RDATA),
.xillybus_M_AXI_rlast(xillybus_M_AXI_RLAST),
.xillybus_M_AXI_rready(xillybus_M_AXI_RREADY),
.xillybus_M_AXI_rresp(xillybus_M_AXI_RRESP),
.xillybus_M_AXI_rvalid(xillybus_M_AXI_RVALID),
.xillybus_M_AXI_wdata(xillybus_M_AXI_WDATA),
.xillybus_M_AXI_wlast(xillybus_M_AXI_WLAST),
.xillybus_M_AXI_wready(xillybus_M_AXI_WREADY),
.xillybus_M_AXI_wstrb(xillybus_M_AXI_WSTRB),
.xillybus_M_AXI_wvalid(xillybus_M_AXI_WVALID),
.xillybus_S_AXI_araddr(xillybus_S_AXI_ARADDR),
.xillybus_S_AXI_arready(xillybus_S_AXI_ARREADY),
.xillybus_S_AXI_arvalid(xillybus_S_AXI_ARVALID),
.xillybus_S_AXI_awaddr(xillybus_S_AXI_AWADDR),
.xillybus_S_AXI_awready(xillybus_S_AXI_AWREADY),
.xillybus_S_AXI_awvalid(xillybus_S_AXI_AWVALID),
.xillybus_S_AXI_bready(xillybus_S_AXI_BREADY),
.xillybus_S_AXI_bresp(xillybus_S_AXI_BRESP),
.xillybus_S_AXI_bvalid(xillybus_S_AXI_BVALID),
.xillybus_S_AXI_rdata(xillybus_S_AXI_RDATA),
.xillybus_S_AXI_rready(xillybus_S_AXI_RREADY),
.xillybus_S_AXI_rresp(xillybus_S_AXI_RRESP),
.xillybus_S_AXI_rvalid(xillybus_S_AXI_RVALID),
.xillybus_S_AXI_wdata(xillybus_S_AXI_WDATA),
.xillybus_S_AXI_wready(xillybus_S_AXI_WREADY),
.xillybus_S_AXI_wstrb(xillybus_S_AXI_WSTRB),
.xillybus_S_AXI_wvalid(xillybus_S_AXI_WVALID),
.xillybus_bus_clk(xillybus_bus_clk),
.xillybus_bus_rst_n(xillybus_bus_rst_n),
.xillybus_host_interrupt(xillybus_host_interrupt));
endmodule

571
xillinux-syn/vivado-essentials/vga_fifo/vga_fifo.xci Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>xci</spirit:library>
<spirit:name>unknown</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>vga_fifo</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.2"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
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</spirit:design>

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xillinux-syn/vivado-essentials/vivado-ip/xillybus_ip/component.xml Normal file
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xillinux-syn/vivado-essentials/vivado-ip/xillybus_ip/xillybus.srcs/sources_1/imports/verilog/xillybus_ip.v Normal file
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module xillybus_ip #(
parameter C_S_AXI_DATA_WIDTH = 32,
parameter C_S_AXI_ADDR_WIDTH = 32,
parameter C_M_AXI_ADDR_WIDTH = 32,
parameter C_M_AXI_DATA_WIDTH = 64
)
(
input S_AXI_ACLK,
input S_AXI_ARESETN,
output Interrupt,
input [(C_S_AXI_ADDR_WIDTH-1):0] S_AXI_AWADDR,
input S_AXI_AWVALID,
input [(C_S_AXI_DATA_WIDTH-1):0] S_AXI_WDATA,
input [((C_S_AXI_DATA_WIDTH/8)-1):0] S_AXI_WSTRB,
input S_AXI_WVALID,
input S_AXI_BREADY,
input [(C_S_AXI_ADDR_WIDTH-1):0] S_AXI_ARADDR,
input S_AXI_ARVALID,
input S_AXI_RREADY,
output S_AXI_ARREADY,
output [(C_S_AXI_DATA_WIDTH-1):0] S_AXI_RDATA,
output [1:0] S_AXI_RRESP,
output S_AXI_RVALID,
output S_AXI_WREADY,
output [1:0] S_AXI_BRESP,
output S_AXI_BVALID,
output S_AXI_AWREADY,
input m_axi_aclk,
input m_axi_aresetn,
input m_axi_arready,
output m_axi_arvalid,
output [(C_M_AXI_ADDR_WIDTH-1):0] m_axi_araddr,
output [3:0] m_axi_arlen,
output [2:0] m_axi_arsize,
output [1:0] m_axi_arburst,
output [2:0] m_axi_arprot,
output [3:0] m_axi_arcache,
output m_axi_rready,
input m_axi_rvalid,
input [(C_M_AXI_DATA_WIDTH-1):0] m_axi_rdata,
input [1:0] m_axi_rresp,
input m_axi_rlast,
input m_axi_awready,
output m_axi_awvalid,
output [(C_M_AXI_ADDR_WIDTH-1):0] m_axi_awaddr,
output [3:0] m_axi_awlen,
output [2:0] m_axi_awsize,
output [1:0] m_axi_awburst,
output [2:0] m_axi_awprot,
output [3:0] m_axi_awcache,
input m_axi_wready,
output m_axi_wvalid,
output [(C_M_AXI_DATA_WIDTH-1):0] m_axi_wdata,
output [((C_M_AXI_DATA_WIDTH/8)-1):0] m_axi_wstrb,
output m_axi_wlast,
output m_axi_bready,
input m_axi_bvalid,
input [1:0] m_axi_bresp,
output xillybus_bus_clk,
output reg xillybus_bus_rst_n,
output [(C_S_AXI_ADDR_WIDTH-1):0] xillybus_S_AXI_AWADDR,
output xillybus_S_AXI_AWVALID,
output [(C_S_AXI_DATA_WIDTH-1):0] xillybus_S_AXI_WDATA,
output [((C_S_AXI_DATA_WIDTH/8)-1):0] xillybus_S_AXI_WSTRB,
output xillybus_S_AXI_WVALID,
output xillybus_S_AXI_BREADY,
output [(C_S_AXI_ADDR_WIDTH-1):0] xillybus_S_AXI_ARADDR,
output xillybus_S_AXI_ARVALID,
output xillybus_S_AXI_RREADY,
input xillybus_S_AXI_ARREADY,
input [(C_S_AXI_DATA_WIDTH-1):0] xillybus_S_AXI_RDATA,
input [1:0] xillybus_S_AXI_RRESP,
input xillybus_S_AXI_RVALID,
input xillybus_S_AXI_WREADY,
input [1:0] xillybus_S_AXI_BRESP,
input xillybus_S_AXI_BVALID,
input xillybus_S_AXI_AWREADY,
output xillybus_M_AXI_ARREADY,
input xillybus_M_AXI_ARVALID,
input [(C_M_AXI_ADDR_WIDTH-1):0] xillybus_M_AXI_ARADDR,
input [3:0] xillybus_M_AXI_ARLEN,
input [2:0] xillybus_M_AXI_ARSIZE,
input [1:0] xillybus_M_AXI_ARBURST,
input [2:0] xillybus_M_AXI_ARPROT,
input [3:0] xillybus_M_AXI_ARCACHE,
input xillybus_M_AXI_RREADY,
output xillybus_M_AXI_RVALID,
output [(C_M_AXI_DATA_WIDTH-1):0] xillybus_M_AXI_RDATA,
output [1:0] xillybus_M_AXI_RRESP,
output xillybus_M_AXI_RLAST,
output xillybus_M_AXI_AWREADY,
input xillybus_M_AXI_AWVALID,
input [(C_M_AXI_ADDR_WIDTH-1):0] xillybus_M_AXI_AWADDR,
input [3:0] xillybus_M_AXI_AWLEN,
input [2:0] xillybus_M_AXI_AWSIZE,
input [1:0] xillybus_M_AXI_AWBURST,
input [2:0] xillybus_M_AXI_AWPROT,
input [3:0] xillybus_M_AXI_AWCACHE,
output xillybus_M_AXI_WREADY,
input xillybus_M_AXI_WVALID,
input [(C_M_AXI_DATA_WIDTH-1):0] xillybus_M_AXI_WDATA,
input [((C_M_AXI_DATA_WIDTH/8)-1):0] xillybus_M_AXI_WSTRB,
input xillybus_M_AXI_WLAST,
input xillybus_M_AXI_BREADY,
output xillybus_M_AXI_BVALID,
output [1:0] xillybus_M_AXI_BRESP,
input xillybus_host_interrupt
);
reg rst_sync;
// S_AXI_ARESETN is possibly completely asyncronous to anything, while
// bus_rst is expected to be synchronous w.r.t. to bus_clk. So it's synced.
always @(posedge S_AXI_ACLK)
begin
xillybus_bus_rst_n <= rst_sync;
rst_sync <= S_AXI_ARESETN;
end
// This module merely connects the AXI signals to the Xillybus core, which
// is external to the processor. This makes it possible to swap the Xillybus
// core without reimplementing the processor.
assign xillybus_bus_clk = S_AXI_ACLK ;
assign xillybus_S_AXI_AWADDR = S_AXI_AWADDR ;
assign xillybus_S_AXI_AWVALID = S_AXI_AWVALID ;
assign xillybus_S_AXI_WDATA = S_AXI_WDATA ;
assign xillybus_S_AXI_WSTRB = S_AXI_WSTRB ;
assign xillybus_S_AXI_WVALID = S_AXI_WVALID ;
assign xillybus_S_AXI_BREADY = S_AXI_BREADY ;
assign xillybus_S_AXI_ARADDR = S_AXI_ARADDR ;
assign xillybus_S_AXI_ARVALID = S_AXI_ARVALID ;
assign xillybus_S_AXI_RREADY = S_AXI_RREADY ;
assign S_AXI_ARREADY = xillybus_S_AXI_ARREADY ;
assign S_AXI_RDATA = xillybus_S_AXI_RDATA ;
assign S_AXI_RRESP = xillybus_S_AXI_RRESP ;
assign S_AXI_RVALID = xillybus_S_AXI_RVALID ;
assign S_AXI_WREADY = xillybus_S_AXI_WREADY ;
assign S_AXI_BRESP = xillybus_S_AXI_BRESP ;
assign S_AXI_BVALID = xillybus_S_AXI_BVALID ;
assign S_AXI_AWREADY = xillybus_S_AXI_AWREADY ;
assign xillybus_M_AXI_ACLK = m_axi_aclk ;
assign xillybus_M_AXI_ARESETN = m_axi_aresetn ;
assign xillybus_M_AXI_ARREADY = m_axi_arready ;
assign m_axi_arvalid = xillybus_M_AXI_ARVALID ;
assign m_axi_araddr = xillybus_M_AXI_ARADDR ;
assign m_axi_arlen = xillybus_M_AXI_ARLEN ;
assign m_axi_arsize = xillybus_M_AXI_ARSIZE ;
assign m_axi_arburst = xillybus_M_AXI_ARBURST ;
assign m_axi_arprot = xillybus_M_AXI_ARPROT ;
assign m_axi_arcache = xillybus_M_AXI_ARCACHE ;
assign m_axi_rready = xillybus_M_AXI_RREADY ;
assign xillybus_M_AXI_RVALID = m_axi_rvalid ;
assign xillybus_M_AXI_RDATA = m_axi_rdata ;
assign xillybus_M_AXI_RRESP = m_axi_rresp ;
assign xillybus_M_AXI_RLAST = m_axi_rlast ;
assign xillybus_M_AXI_AWREADY = m_axi_awready ;
assign m_axi_awvalid = xillybus_M_AXI_AWVALID ;
assign m_axi_awaddr = xillybus_M_AXI_AWADDR ;
assign m_axi_awlen = xillybus_M_AXI_AWLEN ;
assign m_axi_awsize = xillybus_M_AXI_AWSIZE ;
assign m_axi_awburst = xillybus_M_AXI_AWBURST ;
assign m_axi_awprot = xillybus_M_AXI_AWPROT ;
assign m_axi_awcache = xillybus_M_AXI_AWCACHE ;
assign xillybus_M_AXI_WREADY = m_axi_wready ;
assign m_axi_wvalid = xillybus_M_AXI_WVALID ;
assign m_axi_wdata = xillybus_M_AXI_WDATA ;
assign m_axi_wstrb = xillybus_M_AXI_WSTRB ;
assign m_axi_wlast = xillybus_M_AXI_WLAST ;
assign m_axi_bready = xillybus_M_AXI_BREADY ;
assign xillybus_M_AXI_BVALID = m_axi_bvalid ;
assign xillybus_M_AXI_BRESP = m_axi_bresp ;
assign Interrupt = xillybus_host_interrupt;
endmodule

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xillinux-syn/vivado-essentials/vivado-ip/xillybus_lite/component.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xillybus</spirit:vendor>
<spirit:library>xillybus</spirit:library>
<spirit:name>xillybus_lite</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>S_AXI</spirit:name>
<spirit:displayName>S_AXI</spirit:displayName>
<spirit:description>AXI Lite slave</spirit:description>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_ARREADY</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_RDATA</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_AWREADY</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_ARADDR</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_AWADDR</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_RRESP</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_WDATA</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_AWVALID</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_RREADY</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>BREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_BREADY</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>BVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_BVALID</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WSTRB</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_WSTRB</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>BRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_BRESP</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_WVALID</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_ARVALID</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_RVALID</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_WREADY</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>s_axi_clk</spirit:name>
<spirit:displayName>s_axi_clk</spirit:displayName>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_ACLK</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_CLK.ASSOCIATED_BUSIF">S_AXI</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_CLK.ASSOCIATED_RESET">S_AXI_ARESETN</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>s_axi_resetn</spirit:name>
<spirit:displayName>s_axi_resetn</spirit:displayName>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_ARESETN</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>POLARITY</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_RESETN.POLARITY">ACTIVE_LOW</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>host_interrupt</spirit:name>
<spirit:displayName>host_interrupt</spirit:displayName>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>INTERRUPT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>host_interrupt</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>SENSITIVITY</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.HOST_INTERRUPT.SENSITIVITY">EDGE_RISING</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:addressSpaces>
<spirit:addressSpace>
<spirit:name>user</spirit:name>
<spirit:range spirit:format="string" spirit:resolve="user">4G</spirit:range>
<spirit:width spirit:resolve="user">32</spirit:width>
</spirit:addressSpace>
</spirit:addressSpaces>
<spirit:memoryMaps>
<spirit:memoryMap>
<spirit:name>S_AXI</spirit:name>
<spirit:addressBlock>
<spirit:name>reg0</spirit:name>
<spirit:baseAddress spirit:format="bitString" spirit:resolve="user" spirit:bitStringLength="32">0</spirit:baseAddress>
<spirit:range spirit:format="long" spirit:resolve="user">4294967296</spirit:range>
<spirit:width spirit:format="long" spirit:resolve="user">32</spirit:width>
<spirit:usage>register</spirit:usage>
</spirit:addressBlock>
</spirit:memoryMap>
</spirit:memoryMaps>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
<spirit:displayName>Synthesis</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
<spirit:modelName>xillybus_lite</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_implementation</spirit:name>
<spirit:displayName>Implementation</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:implementation</spirit:envIdentifier>
<spirit:modelName>xillybus_lite</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_implementation_view_fileset</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_xpgui</spirit:name>
<spirit:displayName>UI Layout</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>S_AXI_ACLK</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_ARESETN</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_AWVALID</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_WVALID</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_BREADY</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_ARVALID</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_RREADY</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>user_irq</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_ARREADY</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_RVALID</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_WREADY</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_BVALID</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_AWREADY</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>host_interrupt</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>user_clk</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>user_wren</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>user_rden</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_AWADDR</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_WDATA</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_WSTRB</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>3</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_ARADDR</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>user_rd_data</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_RDATA</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_RRESP</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>1</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_BRESP</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>1</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>user_wstrb</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>3</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>user_wr_data</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>user_addr</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
</spirit:ports>
</spirit:model>
<spirit:choices>
<spirit:choice>
<spirit:name>choices_0</spirit:name>
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
</spirit:choice>
<spirit:choice>
<spirit:name>choices_1</spirit:name>
<spirit:enumeration>LEVEL_HIGH</spirit:enumeration>
<spirit:enumeration>LEVEL_LOW</spirit:enumeration>
<spirit:enumeration>EDGE_RISING</spirit:enumeration>
<spirit:enumeration>EDGE_FALLING</spirit:enumeration>
</spirit:choice>
<spirit:choice>
<spirit:name>choices_2</spirit:name>
<spirit:enumeration>LEVEL_HIGH</spirit:enumeration>
<spirit:enumeration>LEVEL_LOW</spirit:enumeration>
<spirit:enumeration>EDGE_RISING</spirit:enumeration>
<spirit:enumeration>EDGE_FALLING</spirit:enumeration>
</spirit:choice>
</spirit:choices>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
<spirit:file>
<spirit:name>$PPRDIR/../../../../system/pcores/xillybus_lite_v1_00_a/netlist/xillybus_lite.ngc</spirit:name>
<spirit:userFileType>ngc</spirit:userFileType>
<spirit:logicalName>work</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_implementation_view_fileset</spirit:name>
<spirit:file>
<spirit:name>$PPRDIR/../../../../system/pcores/xillybus_lite_v1_00_a/netlist/xillybus_lite.ngc</spirit:name>
<spirit:userFileType>ngc</spirit:userFileType>
<spirit:logicalName>work</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
<spirit:file>
<spirit:name>xgui/xillybus_lite_v1_0.tcl</spirit:name>
<spirit:fileType>tclSource</spirit:fileType>
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>Xillybus Lite</spirit:description>
<spirit:parameters>
<spirit:parameter>
<spirit:name>Component_Name</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">xillybus_lite_v1_0</spirit:value>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:coreExtensions>
<xilinx:supportedFamilies>
<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
</xilinx:supportedFamilies>
<xilinx:taxonomies>
<xilinx:taxonomy>/BaseIP</xilinx:taxonomy>
</xilinx:taxonomies>
<xilinx:displayName>xillybus_lite_v1_0</xilinx:displayName>
<xilinx:vendorDisplayName>Xillybus Ltd.</xilinx:vendorDisplayName>
<xilinx:vendorURL>http://xillybus.com</xilinx:vendorURL>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2014-04-03T15:18:56Z</xilinx:coreCreationDateTime>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2013.4</xilinx:xilinxVersion>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
</spirit:component>

1607
xillinux-syn/vivado-essentials/vivado-ip/xillyvga/component.xml Normal file
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124
xillinux-syn/vivado-essentials/vivado-ip/xillyvga/xillyvga.srcs/sources_1/imports/verilog/xillyvga.v Normal file
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@ -0,0 +1,124 @@
module xillyvga
(
input S_AXI_ACLK,
input [31:0] S_AXI_ARADDR,
input S_AXI_ARESETN,
input S_AXI_ARVALID,
input [31:0] S_AXI_AWADDR,
input S_AXI_AWVALID,
input S_AXI_BREADY,
input S_AXI_RREADY,
input [31:0] S_AXI_WDATA,
input [3:0] S_AXI_WSTRB,
input S_AXI_WVALID,
input clk_in,
input m_axi_aclk,
input m_axi_aresetn,
input m_axi_arready,
input m_axi_awready,
input [1:0] m_axi_bresp,
input m_axi_bvalid,
input [31:0] m_axi_rdata,
input m_axi_rlast,
input [1:0] m_axi_rresp,
input m_axi_rvalid,
input m_axi_wready,
output S_AXI_ARREADY,
output S_AXI_AWREADY,
output [1:0] S_AXI_BRESP,
output S_AXI_BVALID,
output [31:0] S_AXI_RDATA,
output [1:0] S_AXI_RRESP,
output S_AXI_RVALID,
output S_AXI_WREADY,
output [31:0] m_axi_araddr,
output [1:0] m_axi_arburst,
output [3:0] m_axi_arcache,
output [3:0] m_axi_arlen,
output [2:0] m_axi_arprot,
output [2:0] m_axi_arsize,
output m_axi_arvalid,
output [31:0] m_axi_awaddr,
output [1:0] m_axi_awburst,
output [3:0] m_axi_awcache,
output [3:0] m_axi_awlen,
output [2:0] m_axi_awprot,
output [2:0] m_axi_awsize,
output m_axi_awvalid,
output m_axi_bready,
output m_axi_rready,
output [31:0] m_axi_wdata,
output m_axi_wlast,
output [3:0] m_axi_wstrb,
output m_axi_wvalid,
output vga_clk,
output [7:0] vga_blue,
output [7:0] vga_green,
output vga_hsync,
output [7:0] vga_red,
output vga_vsync,
output vga_de
);
xillyvga_core xillyvga_core_ins (
.S_AXI_ACLK(S_AXI_ACLK),
.S_AXI_ARADDR(S_AXI_ARADDR),
.S_AXI_ARESETN(S_AXI_ARESETN),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_AWADDR(S_AXI_AWADDR),
.S_AXI_AWVALID(S_AXI_AWVALID),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_RREADY(S_AXI_RREADY),
.S_AXI_WDATA(S_AXI_WDATA),
.S_AXI_WSTRB(S_AXI_WSTRB),
.S_AXI_WVALID(S_AXI_WVALID),
.clk_in(clk_in),
.m_axi_aclk(m_axi_aclk),
.m_axi_aresetn(m_axi_aresetn),
.m_axi_arready(m_axi_arready),
.m_axi_awready(m_axi_awready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rlast(m_axi_rlast),
.m_axi_rresp(m_axi_rresp),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wready(m_axi_wready),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_AWREADY(S_AXI_AWREADY),
.S_AXI_BRESP(S_AXI_BRESP),
.S_AXI_BVALID(S_AXI_BVALID),
.S_AXI_RDATA(S_AXI_RDATA),
.S_AXI_RRESP(S_AXI_RRESP),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_WREADY(S_AXI_WREADY),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(m_axi_arburst),
.m_axi_arcache(m_axi_arcache),
.m_axi_arlen(m_axi_arlen),
.m_axi_arprot(m_axi_arprot),
.m_axi_arsize(m_axi_arsize),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(m_axi_awburst),
.m_axi_awcache(m_axi_awcache),
.m_axi_awlen(m_axi_awlen),
.m_axi_awprot(m_axi_awprot),
.m_axi_awsize(m_axi_awsize),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bready(m_axi_bready),
.m_axi_rready(m_axi_rready),
.m_axi_wdata(m_axi_wdata),
.m_axi_wlast(m_axi_wlast),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wvalid(m_axi_wvalid),
.vga_clk(vga_clk),
.vga_blue(vga_blue),
.vga_green(vga_green),
.vga_hsync(vga_hsync),
.vga_red(vga_red),
.vga_vsync(vga_vsync),
.vga_de(vga_de)
);
endmodule

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xillinux-syn/vivado-essentials/vivado-ip/xillyvga/xillyvga.srcs/sources_1/imports/verilog/xillyvga_core.v Normal file
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module xillyvga_core
(
input S_AXI_ACLK,
input [31:0] S_AXI_ARADDR,
input S_AXI_ARESETN,
input S_AXI_ARVALID,
input [31:0] S_AXI_AWADDR,
input S_AXI_AWVALID,
input S_AXI_BREADY,
input S_AXI_RREADY,
input [31:0] S_AXI_WDATA,
input [3:0] S_AXI_WSTRB,
input S_AXI_WVALID,
input clk_in,
input m_axi_aclk,
input m_axi_aresetn,
input m_axi_arready,
input m_axi_awready,
input [1:0] m_axi_bresp,
input m_axi_bvalid,
input [31:0] m_axi_rdata,
input m_axi_rlast,
input [1:0] m_axi_rresp,
input m_axi_rvalid,
input m_axi_wready,
output S_AXI_ARREADY,
output S_AXI_AWREADY,
output [1:0] S_AXI_BRESP,
output S_AXI_BVALID,
output [31:0] S_AXI_RDATA,
output [1:0] S_AXI_RRESP,
output S_AXI_RVALID,
output S_AXI_WREADY,
output [31:0] m_axi_araddr,
output [1:0] m_axi_arburst,
output [3:0] m_axi_arcache,
output [3:0] m_axi_arlen,
output [2:0] m_axi_arprot,
output [2:0] m_axi_arsize,
output m_axi_arvalid,
output [31:0] m_axi_awaddr,
output [1:0] m_axi_awburst,
output [3:0] m_axi_awcache,
output [3:0] m_axi_awlen,
output [2:0] m_axi_awprot,
output [2:0] m_axi_awsize,
output m_axi_awvalid,
output m_axi_bready,
output m_axi_rready,
output [31:0] m_axi_wdata,
output m_axi_wlast,
output [3:0] m_axi_wstrb,
output m_axi_wvalid,
output vga_clk,
output [7:0] vga_blue,
output [7:0] vga_green,
output vga_hsync,
output [7:0] vga_red,
output vga_de,
output vga_vsync
);
endmodule

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create_clock -name gclk -period 10 [get_ports "clk_100"]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets "clk_100"]
# Vivado constraints unrelated clocks. So set false paths.
set_false_path -from [get_clocks clk_fpga_1] -to [get_clocks vga_clk_ins/*]
set_false_path -from [get_clocks vga_clk_ins/*] -to [get_clocks clk_fpga_1]
# The VGA outputs are turned into an analog voltage by virtue of a resistor
# network, so the flip flops driving these must sit in the IOBs to minimize
# timing skew. The RTL code should handle this, but the constraint below
# is there to fail if something goes wrong about this.
set_output_delay 5.5 [get_ports {vga*}]
set_property -dict "PACKAGE_PIN Y9 IOSTANDARD LVCMOS33" [get_ports "clk_100"]
set_property -dict "PACKAGE_PIN T22 IOSTANDARD LVCMOS33" [get_ports "GPIO_LED[0]"]
set_property -dict "PACKAGE_PIN T21 IOSTANDARD LVCMOS33" [get_ports "GPIO_LED[1]"]
set_property -dict "PACKAGE_PIN U22 IOSTANDARD LVCMOS33" [get_ports "GPIO_LED[2]"]
set_property -dict "PACKAGE_PIN U21 IOSTANDARD LVCMOS33" [get_ports "GPIO_LED[3]"]
set_property -dict "PACKAGE_PIN Y21 IOSTANDARD LVCMOS33" [get_ports "vga4_blue[0]"]
set_property -dict "PACKAGE_PIN Y20 IOSTANDARD LVCMOS33" [get_ports "vga4_blue[1]"]
set_property -dict "PACKAGE_PIN AB20 IOSTANDARD LVCMOS33" [get_ports "vga4_blue[2]"]
set_property -dict "PACKAGE_PIN AB19 IOSTANDARD LVCMOS33" [get_ports "vga4_blue[3]"]
set_property -dict "PACKAGE_PIN AB22 IOSTANDARD LVCMOS33" [get_ports "vga4_green[0]"]
set_property -dict "PACKAGE_PIN AA22 IOSTANDARD LVCMOS33" [get_ports "vga4_green[1]"]
set_property -dict "PACKAGE_PIN AB21 IOSTANDARD LVCMOS33" [get_ports "vga4_green[2]"]
set_property -dict "PACKAGE_PIN AA21 IOSTANDARD LVCMOS33" [get_ports "vga4_green[3]"]
set_property -dict "PACKAGE_PIN V20 IOSTANDARD LVCMOS33" [get_ports "vga4_red[0]"]
set_property -dict "PACKAGE_PIN U20 IOSTANDARD LVCMOS33" [get_ports "vga4_red[1]"]
set_property -dict "PACKAGE_PIN V19 IOSTANDARD LVCMOS33" [get_ports "vga4_red[2]"]
set_property -dict "PACKAGE_PIN V18 IOSTANDARD LVCMOS33" [get_ports "vga4_red[3]"]
set_property -dict "PACKAGE_PIN Y19 IOSTANDARD LVCMOS33" [get_ports "vga_vsync"]
set_property -dict "PACKAGE_PIN AA19 IOSTANDARD LVCMOS33" [get_ports "vga_hsync"]
# IMPORTANT: Since four LEDs are taken by the Xillybus IP core, the pin
# placement doesn't match the one given by Digilent.
# GPIO pin to reset the USB OTG PHY
set_property -dict "PACKAGE_PIN G17 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[0]"]
# On-board OLED
set_property -dict "PACKAGE_PIN U11 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[1]"]
set_property -dict "PACKAGE_PIN U12 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[2]"]
set_property -dict "PACKAGE_PIN U9 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[3]"]
set_property -dict "PACKAGE_PIN U10 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[4]"]
set_property -dict "PACKAGE_PIN AB12 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[5]"]
set_property -dict "PACKAGE_PIN AA12 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[6]"]
# On-board LEDs. Note that only for LEDs are allocated, as opposed to
# Digilent's eight, and all placements that follow are shifted by four.
# There was no other choice, as the tools don't allow unplaced PS GPIO pins.
set_property -dict "PACKAGE_PIN V22 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[7]"]
set_property -dict "PACKAGE_PIN W22 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[8]"]
set_property -dict "PACKAGE_PIN U19 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[9]"]
set_property -dict "PACKAGE_PIN U14 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[10]"]
# On-board Slide Switches
set_property -dict "PACKAGE_PIN F22 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[11]"]
set_property -dict "PACKAGE_PIN G22 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[12]"]
set_property -dict "PACKAGE_PIN H22 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[13]"]
set_property -dict "PACKAGE_PIN F21 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[14]"]
set_property -dict "PACKAGE_PIN H19 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[15]"]
set_property -dict "PACKAGE_PIN H18 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[16]"]
set_property -dict "PACKAGE_PIN H17 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[17]"]
set_property -dict "PACKAGE_PIN M15 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[18]"]
# On-board Left, Right, Up, Down, and Select Pushbuttons
set_property -dict "PACKAGE_PIN N15 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[19]"]
set_property -dict "PACKAGE_PIN R18 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[20]"]
set_property -dict "PACKAGE_PIN T18 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[21]"]
set_property -dict "PACKAGE_PIN R16 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[22]"]
set_property -dict "PACKAGE_PIN P16 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[23]"]
# Pmod JA
set_property -dict "PACKAGE_PIN Y11 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[24]"]
set_property -dict "PACKAGE_PIN AA11 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[25]"]
set_property -dict "PACKAGE_PIN Y10 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[26]"]
set_property -dict "PACKAGE_PIN AA9 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[27]"]
set_property -dict "PACKAGE_PIN AB11 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[28]"]
set_property -dict "PACKAGE_PIN AB10 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[29]"]
set_property -dict "PACKAGE_PIN AB9 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[30]"]
set_property -dict "PACKAGE_PIN AA8 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[31]"]
# Pmod JB
set_property -dict "PACKAGE_PIN W12 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[32]"]
set_property -dict "PACKAGE_PIN W11 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[33]"]
set_property -dict "PACKAGE_PIN V10 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[34]"]
set_property -dict "PACKAGE_PIN W8 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[35]"]
set_property -dict "PACKAGE_PIN V12 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[36]"]
set_property -dict "PACKAGE_PIN W10 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[37]"]
set_property -dict "PACKAGE_PIN V9 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[38]"]
set_property -dict "PACKAGE_PIN V8 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[39]"]
# Pmod JC
set_property -dict "PACKAGE_PIN AB7 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[40]"]
set_property -dict "PACKAGE_PIN AB6 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[41]"]
set_property -dict "PACKAGE_PIN Y4 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[42]"]
set_property -dict "PACKAGE_PIN AA4 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[43]"]
set_property -dict "PACKAGE_PIN R6 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[44]"]
set_property -dict "PACKAGE_PIN T6 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[45]"]
set_property -dict "PACKAGE_PIN T4 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[46]"]
set_property -dict "PACKAGE_PIN U4 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[47]"]
# Pmod JD
set_property -dict "PACKAGE_PIN V7 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[48]"]
set_property -dict "PACKAGE_PIN W7 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[49]"]
set_property -dict "PACKAGE_PIN V5 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[50]"]
set_property -dict "PACKAGE_PIN V4 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[51]"]
set_property -dict "PACKAGE_PIN W6 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[52]"]
set_property -dict "PACKAGE_PIN W5 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[53]"]
set_property -dict "PACKAGE_PIN U6 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[54]"]
set_property -dict "PACKAGE_PIN U5 IOSTANDARD LVCMOS33" [get_ports "PS_GPIO[55]"]
# Pin for detecting USB OTG over-current condition
set_property -dict "PACKAGE_PIN L16 IOSTANDARD LVCMOS33" [get_ports "otg_oc"]
# Pins connected to sound chip
set_property -dict "PACKAGE_PIN AB1 IOSTANDARD LVCMOS33" [get_ports "smbus_addr[0]"]
set_property -dict "PACKAGE_PIN Y5 IOSTANDARD LVCMOS33" [get_ports "smbus_addr[1]"]
set_property -dict "PACKAGE_PIN AB4 IOSTANDARD LVCMOS33" [get_ports "smb_sclk"]
set_property -dict "PACKAGE_PIN AB5 IOSTANDARD LVCMOS33" [get_ports "smb_sdata"]
set_property -dict "PACKAGE_PIN Y8 IOSTANDARD LVCMOS33" [get_ports "audio_dac"]
set_property -dict "PACKAGE_PIN AA7 IOSTANDARD LVCMOS33" [get_ports "audio_adc"]
set_property -dict "PACKAGE_PIN AA6 IOSTANDARD LVCMOS33" [get_ports "audio_bclk"]
set_property -dict "PACKAGE_PIN Y6 IOSTANDARD LVCMOS33" [get_ports "audio_lrclk"]
set_property -dict "PACKAGE_PIN AB2 IOSTANDARD LVCMOS33" [get_ports "audio_mclk"]

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xillinux-syn/vivado/xillydemo.xpr Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2018.3.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="39" Path="C:/Users/JohnD/Desktop/labor-mst/xillinux-syn/vivado/xillydemo.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="4ea9794cae5e47e59b5a8a5fb59f663e"/>
<Option Name="Part" Val="xc7z020clg484-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="TargetLanguage" Val="VHDL"/>
<Option Name="BoardPart" Val=""/>
<Option Name="SourceMgmtMode" Val="DisplayOnly"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../vivado-essentials/vivado-ip"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSAVendor" Val="xilinx"/>
<Option Name="DSANumComputeUnits" Val="60"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="0"/>
<Option Name="WTModelSimExportSim" Val="0"/>
<Option Name="WTQuestaExportSim" Val="0"/>
<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="0"/>
<Option Name="WTRivieraExportSim" Val="0"/>
<Option Name="WTActivehdlExportSim" Val="0"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
<Option Name="SimTypes" Val="bfm"/>
<Option Name="SimTypes" Val="tlm"/>
<Option Name="SimTypes" Val="tlm_dpi"/>
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../vhdl/src/xillydemo.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../vhdl/src/smbus.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../vhdl/src/i2s_audio.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../vhdl/src/xillybus.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../vhdl/src/xillybus_core.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../vivado-essentials/system.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../vivado-essentials/vivado_system/vivado_system.bd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../cores/xillybus_core.ngc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../cores/xillyvga_core.ngc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="xillydemo"/>
<Option Name="ExtraSearchPath" Val="W:/xillinux-eval-zedboard-2.0c/cores"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PPRDIR/../vivado-essentials/xillydemo.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="unknown"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SrcSet" Val="sources_1"/>
<Option Name="xsim.simulate.runtime" Val="1000 ns"/>
<Option Name="xsim.simulate.uut" Val="UUT"/>
</Config>
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="vga_fifo" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vga_fifo">
<File Path="$PPRDIR/../vivado-essentials/vga_fifo/vga_fifo.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="vga_fifo"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="fifo_8x2048" Type="BlockSrcs" RelSrcDir="$PSRCDIR/fifo_8x2048">
<File Path="$PPRDIR/../vivado-essentials/fifo_8x2048/fifo_8x2048.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="fifo_8x2048"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="fifo_32x512" Type="BlockSrcs" RelSrcDir="$PSRCDIR/fifo_32x512">
<File Path="$PPRDIR/../vivado-essentials/fifo_32x512/fifo_32x512.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="fifo_32x512"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
<Simulator Name="ActiveHDL">
<Option Name="Description" Val="Active-HDL Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="vga_fifo_synth_1" Type="Ft3:Synth" SrcSet="vga_fifo" Part="xc7z020clg484-1" ConstrsSet="vga_fifo" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/vga_fifo_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="fifo_8x2048_synth_1" Type="Ft3:Synth" SrcSet="fifo_8x2048" Part="xc7z020clg484-1" ConstrsSet="fifo_8x2048" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/fifo_8x2048_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="fifo_32x512_synth_1" Type="Ft3:Synth" SrcSet="fifo_32x512" Part="xc7z020clg484-1" ConstrsSet="fifo_32x512" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/fifo_32x512_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design" PostStepTclHook="$PPRDIR/../vivado-essentials/showstopper.tcl"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="vga_fifo_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg484-1" ConstrsSet="vga_fifo" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="vga_fifo_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="fifo_8x2048_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg484-1" ConstrsSet="fifo_8x2048" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="fifo_8x2048_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="fifo_32x512_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg484-1" ConstrsSet="fifo_32x512" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="fifo_32x512_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
</Runs>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="BD 41-968"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="1"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="xillybus_S_AXI"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="Netlist 29-160"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="10"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="vivado_system_processing_system7"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="PSU-1"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="11"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="PSU-2"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="12"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="BD 41-968"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="2"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="xillybus_M_AXI"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="BD 41-967"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="3"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="xillybus_ip_0/xillybus_M_AXI"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="BD 41-967"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="4"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="xillybus_ip_0/xillybus_S_AXI"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="BD 41-678"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="5"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="xillybus_S_AXI/Reg"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="BD 41-1356"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="6"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="xillybus_S_AXI/Reg"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="BD 41-759"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="8"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="xlconcat_0/In"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="filemgmt 20-1440"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="9"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="xillybus_lite.ngc"/>
</MsgRule>
<Board/>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
<BootPmcSettings Version="1" Minor="0">
<Parameters/>
</BootPmcSettings>
</Project>

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xillinux-syn/xillydemo-vivado.tcl Normal file
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# Xillydemo project generation script for Vivado 2014.4 and up
set origin_dir [file dirname [info script]]
if {[string first { } $origin_dir] >= 0} {
send_msg_id xillydemo-1 error "The path to the the project directory contains white space(s): \"$origin_dir\". This is known to cause problems with Vivado. Please move the project to a path without white spaces, and try again."
}
set proj_name xillydemo
set proj_dir "[file normalize $origin_dir/vivado]"
set thepart "xc7z020clg484-1"
# Set the directory for essentials for Vivado
set essentials_dir "[file normalize "$origin_dir/vivado-essentials"]"
# Create project
create_project $proj_name "$proj_dir/"
# Set project properties
set obj [get_projects $proj_name]
set_property "default_lib" "xil_defaultlib" $obj
set_property "part" $thepart $obj
set_property "simulator_language" "Mixed" $obj
set_property "source_mgmt_mode" "DisplayOnly" $obj
set_property target_language VHDL $obj
set_property "ip_repo_paths" "$essentials_dir/vivado-ip" [current_fileset]
update_ip_catalog
# Create 'sources_1' fileset (if not found)
if {[string equal [get_filesets sources_1] ""]} {
create_fileset -srcset sources_1
}
# Set 'sources_1' fileset properties
set obj [get_filesets sources_1]
set_property "edif_extra_search_paths" "[file normalize "$origin_dir/cores"]" $obj
set_property "top" "xillydemo" $obj
# Add files to 'sources_1' fileset
set obj [get_filesets sources_1]
set files [list \
$origin_dir/vhdl/src/xillydemo.vhd \
$origin_dir/vhdl/src/smbus.v \
$origin_dir/vhdl/src/i2s_audio.v \
$origin_dir/vhdl/src/xillybus.v \
$origin_dir/vhdl/src/xillybus_core.v \
$essentials_dir/system.v \
$essentials_dir/vga_fifo/vga_fifo.xci \
$essentials_dir/fifo_8x2048/fifo_8x2048.xci \
$essentials_dir/fifo_32x512/fifo_32x512.xci \
$essentials_dir/vivado_system/vivado_system.bd \
]
add_files -norecurse -fileset $obj $files
upgrade_ip [get_ips]
# A bug in Vivado drops one slave interface on the AXI4-Lite to AXI3
# crossbar when vivado_system.bd is loaded. So AXI4-Lite slaves are
# connected with the Tcl commands below.
open_bd_design $essentials_dir/vivado_system/vivado_system.bd
startgroup
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/processing_system7_0/M_AXI_GP0" Clk "Auto" } [get_bd_intf_pins xillybus_ip_0/S_AXI]
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/processing_system7_0/M_AXI_GP0" Clk "Auto" } [get_bd_intf_pins xillyvga_0/S_AXI]
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/processing_system7_0/M_AXI_GP0" Clk "Auto" } [get_bd_intf_pins xillybus_lite_0/S_AXI]
set_property range 4K [get_bd_addr_segs {processing_system7_0/Data/SEG_xillybus_ip_0_reg0}]
set_property range 4K [get_bd_addr_segs {processing_system7_0/Data/SEG_xillyvga_0_reg0}]
set_property range 4K [get_bd_addr_segs {processing_system7_0/Data/SEG_xillybus_lite_0_reg0}]
set_property offset 0x50000000 [get_bd_addr_segs {processing_system7_0/Data/SEG_xillybus_ip_0_reg0}]
set_property offset 0x50001000 [get_bd_addr_segs {processing_system7_0/Data/SEG_xillyvga_0_reg0}]
set_property offset 0x50002000 [get_bd_addr_segs {processing_system7_0/Data/SEG_xillybus_lite_0_reg0}]
endgroup
save_bd_design
close_bd_design vivado_system
# Create 'constrs_1' fileset (if not found)
if {[string equal [get_filesets constrs_1] ""]} {
create_fileset -constrset constrs_1
}
# Add files to 'constrs_1' fileset
set obj [get_filesets constrs_1]
add_files -fileset $obj -norecurse $essentials_dir/xillydemo.xdc
# Set 'constrs_1' fileset properties
set obj [get_filesets constrs_1]
# Create 'sim_1' fileset (if not found)
if {[string equal [get_filesets sim_1] ""]} {
create_fileset -simset sim_1
}
# Add files to 'sim_1' fileset
set obj [get_filesets sim_1]
# Empty (no sources present)
# Set 'sim_1' fileset properties
set obj [get_filesets sim_1]
set_property "top" "unknown" $obj
set_property "xsim.simulate.runtime" "1000 ns" $obj
set_property "xsim.simulate.uut" "UUT" $obj
# Create 'synth_1' run (if not found)
if {[string equal [get_runs synth_1] ""]} {
create_run -name synth_1 -part $thepart -flow {Vivado Synthesis 2013} -strategy "Vivado Synthesis Defaults" -constrset constrs_1
}
set obj [get_runs synth_1]
set_property "part" $thepart $obj
# Create 'impl_1' run (if not found)
if {[string equal [get_runs impl_1] ""]} {
create_run -name impl_1 -part $thepart -flow {Vivado Implementation 2013} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1
}
set obj [get_runs impl_1]
set_property "part" $thepart $obj
set_property STEPS.ROUTE_DESIGN.TCL.POST "$essentials_dir/showstopper.tcl" $obj
# Calm down critical warnings for issues that are known to be OK
set_msg_config -new_severity "INFO" -id {BD 41-968} -string {{xillybus_S_AXI} }
set_msg_config -new_severity "INFO" -id {BD 41-968} -string {{xillybus_M_AXI} }
set_msg_config -new_severity "INFO" -id {BD 41-967} -string {{xillybus_ip_0/xillybus_M_AXI} }
set_msg_config -new_severity "INFO" -id {BD 41-967} -string {{xillybus_ip_0/xillybus_S_AXI} }
set_msg_config -new_severity "INFO" -id {BD 41-678} -string {{xillybus_S_AXI/Reg} }
set_msg_config -new_severity "INFO" -id {BD 41-1356} -string {{xillybus_S_AXI/Reg} }
set_msg_config -new_severity "INFO" -id {BD 41-759} -string {{xlconcat_0/In} }
set_msg_config -new_severity "INFO" -id {BD 41-759} -string {{xlconcat_0/In} }
set_msg_config -new_severity "INFO" -id {filemgmt 20-1440} -string {{xillybus_lite.ngc} }
# The processor's native pads are detached in the logic design to prevent
# Vivado from confusing itself. This causes a lot of critical warnings about
# meaningless contraints not being applied. So drop the warnings.
set_msg_config -new_severity "INFO" -id {Netlist 29-160} -string {{vivado_system_processing_system7} }
puts "INFO: Project created: $proj_name"
# Uncomment the two following lines for a full implementation
#launch_runs -jobs 8 impl_1 -to_step write_bitstream
#wait_on_run impl_1