1608 lines
67 KiB
XML
1608 lines
67 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>xillybus</spirit:vendor>
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<spirit:library>xillybus</spirit:library>
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<spirit:name>xillyvga</spirit:name>
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<spirit:version>1.0</spirit:version>
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<spirit:busInterfaces>
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<spirit:busInterface>
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<spirit:name>S_AXI</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
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<spirit:slave>
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<spirit:memoryMapRef spirit:memoryMapRef="S_AXI"/>
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</spirit:slave>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>AWADDR</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>S_AXI_AWADDR</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>AWVALID</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>S_AXI_AWVALID</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>AWREADY</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>S_AXI_AWREADY</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>WDATA</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>S_AXI_WDATA</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>WSTRB</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>S_AXI_WSTRB</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>WVALID</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>S_AXI_WVALID</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>WREADY</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>S_AXI_WREADY</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>BRESP</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>S_AXI_BRESP</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>BVALID</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>S_AXI_BVALID</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>BREADY</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>S_AXI_BREADY</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>ARADDR</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>S_AXI_ARADDR</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>ARVALID</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>S_AXI_ARVALID</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>ARREADY</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>S_AXI_ARREADY</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RDATA</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>S_AXI_RDATA</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RRESP</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>S_AXI_RRESP</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RVALID</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>S_AXI_RVALID</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RREADY</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>S_AXI_RREADY</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>OFFSET_BASE_PARAM</spirit:name>
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<spirit:value spirit:format="string" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>OFFSET_HIGH_PARAM</spirit:name>
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<spirit:value spirit:format="string" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>m_axi</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
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<spirit:master>
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<spirit:addressSpaceRef spirit:addressSpaceRef="m_axi"/>
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</spirit:master>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>AWADDR</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_awaddr</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>AWLEN</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_awlen</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>AWSIZE</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_awsize</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>AWBURST</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_awburst</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>AWCACHE</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_awcache</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>AWPROT</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_awprot</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>AWVALID</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_awvalid</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>AWREADY</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_awready</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>WDATA</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_wdata</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>WSTRB</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_wstrb</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>WLAST</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_wlast</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>WVALID</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_wvalid</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>WREADY</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_wready</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>BRESP</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_bresp</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>BVALID</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_bvalid</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>BREADY</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_bready</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>ARADDR</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_araddr</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>ARLEN</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_arlen</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>ARSIZE</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_arsize</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>ARBURST</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_arburst</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>ARCACHE</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_arcache</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>ARPROT</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_arprot</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>ARVALID</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_arvalid</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>ARREADY</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_arready</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RDATA</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_rdata</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RRESP</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_rresp</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RLAST</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_rlast</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RVALID</spirit:name>
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</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_rvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_rready</spirit:name>
|
|
</spirit:physicalPort>
|
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</spirit:portMap>
|
|
</spirit:portMaps>
|
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</spirit:busInterface>
|
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<spirit:busInterface>
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<spirit:name>S_AXI_signal_reset</spirit:name>
|
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>S_AXI_ARESETN</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>POLARITY</spirit:name>
|
|
<spirit:value spirit:format="string" spirit:resolve="immediate" spirit:id="BUSIFPARAM_VALUE.S_AXI_SIGNAL_RESET.POLARITY" spirit:choiceRef="choices_0">ACTIVE_LOW</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>m_axi_signal_reset</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>m_axi_aresetn</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>POLARITY</spirit:name>
|
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<spirit:value spirit:format="string" spirit:resolve="immediate" spirit:id="BUSIFPARAM_VALUE.M_AXI_SIGNAL_RESET.POLARITY" spirit:choiceRef="choices_1">ACTIVE_LOW</spirit:value>
|
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</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>S_AXI_signal_clock</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>S_AXI_ACLK</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
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<spirit:name>ASSOCIATED_BUSIF</spirit:name>
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<spirit:value spirit:format="string" spirit:resolve="immediate" spirit:id="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK.ASSOCIATED_BUSIF">S_AXI</spirit:value>
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<spirit:name>ASSOCIATED_RESET</spirit:name>
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<spirit:value spirit:format="string" spirit:resolve="immediate" spirit:id="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK.ASSOCIATED_RESET">S_AXI_ARESETN</spirit:value>
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<spirit:name>m_axi_signal_clock</spirit:name>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_aclk</spirit:name>
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<spirit:name>ASSOCIATED_BUSIF</spirit:name>
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<spirit:value spirit:format="string" spirit:resolve="immediate" spirit:id="BUSIFPARAM_VALUE.M_AXI_SIGNAL_CLOCK.ASSOCIATED_BUSIF">m_axi</spirit:value>
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</spirit:parameter>
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<spirit:name>ASSOCIATED_RESET</spirit:name>
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<spirit:value spirit:format="string" spirit:resolve="immediate" spirit:id="BUSIFPARAM_VALUE.M_AXI_SIGNAL_CLOCK.ASSOCIATED_RESET">m_axi_aresetn</spirit:value>
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<spirit:memoryMap>
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<spirit:name>S_AXI</spirit:name>
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<spirit:addressBlock>
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<spirit:name>reg0</spirit:name>
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<spirit:baseAddress spirit:format="bitString" spirit:resolve="user" spirit:bitStringLength="32">0</spirit:baseAddress>
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<spirit:usage>register</spirit:usage>
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<spirit:model>
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<spirit:view>
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<spirit:name>xilinx_verilogsynthesis</spirit:name>
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<spirit:displayName>Verilog Synthesis</spirit:displayName>
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<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
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<spirit:language>verilog</spirit:language>
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<spirit:modelName>xillyvga</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
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<spirit:displayName>Verilog Simulation</spirit:displayName>
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<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
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<spirit:language>verilog</spirit:language>
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<spirit:modelName>xillyvga</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_xpgui</spirit:name>
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<spirit:displayName>UI Layout</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
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<spirit:name>S_AXI_ACLK</spirit:name>
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<spirit:direction>in</spirit:direction>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:name>S_AXI_ARADDR</spirit:name>
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<spirit:direction>in</spirit:direction>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:name>S_AXI_ARESETN</spirit:name>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:name>S_AXI_ARVALID</spirit:name>
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<spirit:direction>in</spirit:direction>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:name>S_AXI_AWADDR</spirit:name>
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<spirit:direction>in</spirit:direction>
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<spirit:left spirit:format="long" spirit:resolve="immediate">31</spirit:left>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:name>S_AXI_WDATA</spirit:name>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:left spirit:format="long" spirit:resolve="immediate">31</spirit:left>
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|
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|
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|
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|
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|
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|
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|
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|
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|
<spirit:direction>out</spirit:direction>
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|
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|
<spirit:left spirit:format="long" spirit:resolve="immediate">31</spirit:left>
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|
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|
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|
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|
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|
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|
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|
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|
<spirit:name>m_axi_wlast</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axi_wstrb</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">3</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>m_axi_wvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>vga_clk</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>vga_blue</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">7</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>vga_green</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">7</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>vga_hsync</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>vga_red</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">7</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>vga_vsync</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>vga_de</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
</spirit:ports>
|
|
</spirit:model>
|
|
<spirit:choices>
|
|
<spirit:choice>
|
|
<spirit:name>choices_0</spirit:name>
|
|
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
|
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choices_1</spirit:name>
|
|
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
|
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
|
</spirit:choice>
|
|
</spirit:choices>
|
|
<spirit:fileSets>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name>
|
|
<spirit:file>
|
|
<spirit:name>xillyvga.srcs/sources_1/imports/verilog/xillyvga_core.v</spirit:name>
|
|
<spirit:fileType>verilogSource</spirit:fileType>
|
|
<spirit:logicalName>work</spirit:logicalName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>xillyvga.srcs/sources_1/imports/verilog/xillyvga.v</spirit:name>
|
|
<spirit:fileType>verilogSource</spirit:fileType>
|
|
<spirit:logicalName>work</spirit:logicalName>
|
|
</spirit:file>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
|
|
<spirit:file>
|
|
<spirit:name>xillyvga.srcs/sources_1/imports/verilog/xillyvga_core.v</spirit:name>
|
|
<spirit:fileType>verilogSource</spirit:fileType>
|
|
<spirit:logicalName>work</spirit:logicalName>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>xillyvga.srcs/sources_1/imports/verilog/xillyvga.v</spirit:name>
|
|
<spirit:fileType>verilogSource</spirit:fileType>
|
|
<spirit:logicalName>work</spirit:logicalName>
|
|
</spirit:file>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
|
|
<spirit:file>
|
|
<spirit:name>xgui/xillyvga_v1_0.tcl</spirit:name>
|
|
<spirit:fileType>tclSource</spirit:fileType>
|
|
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
|
|
</spirit:file>
|
|
</spirit:fileSet>
|
|
</spirit:fileSets>
|
|
<spirit:description>VGA adapter for Xillinux</spirit:description>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>C_NATIVE_DATA_WIDTH</spirit:name>
|
|
<spirit:displayName>C Native Data Width</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NATIVE_DATA_WIDTH" spirit:order="1100">32</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>C_MAX_BURST_LEN</spirit:name>
|
|
<spirit:displayName>C Max Burst Len</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MAX_BURST_LEN" spirit:order="1200">16</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>C_SLV_DWIDTH</spirit:name>
|
|
<spirit:displayName>C Slv Dwidth</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_SLV_DWIDTH" spirit:order="1300">32</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>C_SLV_AWIDTH</spirit:name>
|
|
<spirit:displayName>C Slv Awidth</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_SLV_AWIDTH" spirit:order="1400">32</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>C_HIGHADDR</spirit:name>
|
|
<spirit:displayName>C Highaddr</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_HIGHADDR" spirit:order="1500" spirit:bitStringLength="32">0x79C0FFFF</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>C_BASEADDR</spirit:name>
|
|
<spirit:displayName>C Baseaddr</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_BASEADDR" spirit:order="1600" spirit:bitStringLength="32">0x79C00000</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>C_DPHASE_TIMEOUT</spirit:name>
|
|
<spirit:displayName>C Dphase Timeout</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DPHASE_TIMEOUT" spirit:order="1700">8</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>C_USE_WSTRB</spirit:name>
|
|
<spirit:displayName>C Use Wstrb</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_WSTRB" spirit:order="1800">1</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>C_S_AXI_MIN_SIZE</spirit:name>
|
|
<spirit:displayName>C S Axi Min Size</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI_MIN_SIZE" spirit:order="1900" spirit:bitStringLength="32">0x000001FF</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>C_M_AXI_DATA_WIDTH</spirit:name>
|
|
<spirit:displayName>C M Axi Data Width</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_DATA_WIDTH" spirit:order="2000">32</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>C_M_AXI_ADDR_WIDTH</spirit:name>
|
|
<spirit:displayName>C M Axi Addr Width</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M_AXI_ADDR_WIDTH" spirit:order="2100">32</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>C_S_AXI_ADDR_WIDTH</spirit:name>
|
|
<spirit:displayName>C S Axi Addr Width</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI_ADDR_WIDTH" spirit:order="2200">32</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>C_S_AXI_DATA_WIDTH</spirit:name>
|
|
<spirit:displayName>C S Axi Data Width</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI_DATA_WIDTH" spirit:order="2300">32</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>Component_Name</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">xillyvga_v1_0</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:coreExtensions>
|
|
<xilinx:supportedFamilies>
|
|
<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
|
|
</xilinx:supportedFamilies>
|
|
<xilinx:taxonomies>
|
|
<xilinx:taxonomy>/BaseIP</xilinx:taxonomy>
|
|
</xilinx:taxonomies>
|
|
<xilinx:displayName>xillyvga_v1_0</xilinx:displayName>
|
|
<xilinx:vendorDisplayName>Xillybus</xilinx:vendorDisplayName>
|
|
<xilinx:vendorURL>http://xillybus.com/xillinux</xilinx:vendorURL>
|
|
<xilinx:coreRevision>1</xilinx:coreRevision>
|
|
<xilinx:coreCreationDateTime>2014-04-02T09:53:17Z</xilinx:coreCreationDateTime>
|
|
</xilinx:coreExtensions>
|
|
<xilinx:packagingInfo>
|
|
<xilinx:xilinxVersion>2013.4</xilinx:xilinxVersion>
|
|
</xilinx:packagingInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:component>
|