greek64/labor-mst
1
0
Fork 0
Code Issues Releases Activity

Fix Overflow/Underflow and Delay Line

Browse Source
This commit is contained in:
Greek 2021-03-26 23:56:28 +01:00
parent b1f3a5c0bc
commit 9d6838aca3
8 changed files with 362 additions and 45 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

59
modelsim/feedback.do Normal file
View File

@ -0,0 +1,59 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider SYSTEM
add wave -noupdate /feedback_loop_tb/clk
add wave -noupdate /feedback_loop_tb/reset
add wave -noupdate -divider ADC
add wave -noupdate /feedback_loop_tb/adc_data_in1
add wave -noupdate /feedback_loop_tb/adc_data_in2
add wave -noupdate /feedback_loop_tb/adc_cs_n
add wave -noupdate -divider CONFIG
add wave -noupdate /feedback_loop_tb/factor
add wave -noupdate /feedback_loop_tb/addsub_mode
add wave -noupdate /feedback_loop_tb/add_input_mux
add wave -noupdate -radix unsigned /feedback_loop_tb/delay
add wave -noupdate -divider INPUT
add wave -noupdate -radix hexadecimal /feedback_loop_tb/uut/adc_data1
add wave -noupdate -radix hexadecimal /feedback_loop_tb/uut/adc_data2
add wave -noupdate /feedback_loop_tb/uut/adc_done
add wave -noupdate -radix hexadecimal /feedback_loop_tb/input2
add wave -noupdate -divider OUTPUT
add wave -noupdate /feedback_loop_tb/uut/addsub_done
add wave -noupdate -radix hexadecimal /feedback_loop_tb/uut/addsub_out
add wave -noupdate -divider TESTBENCH
add wave -noupdate /feedback_loop_tb/adc_stage
add wave -noupdate /feedback_loop_tb/cnt1
add wave -noupdate /feedback_loop_tb/cnt2
add wave -noupdate -divider SIGNAL
add wave -noupdate -format Analog-Step -height 200 -max 4096.0 -radix unsigned /feedback_loop_tb/input1
add wave -noupdate -format Analog-Step -height 200 -max 4094.9999999999995 -radix unsigned /feedback_loop_tb/input2
add wave -noupdate -format Analog-Step -height 200 -max 65536.0 -radix unsigned /feedback_loop_tb/output
add wave -noupdate -divider MISC
add wave -noupdate -radix hexadecimal /feedback_loop_tb/uut/scaler_1_out
add wave -noupdate -radix hexadecimal /feedback_loop_tb/uut/scaler_2_out
add wave -noupdate -radix hexadecimal /feedback_loop_tb/uut/scaler_offset_1
add wave -noupdate -radix hexadecimal /feedback_loop_tb/uut/scaler_offset_2
add wave -noupdate -radix hexadecimal /feedback_loop_tb/uut/inputA_wide
add wave -noupdate -radix hexadecimal /feedback_loop_tb/uut/inputB_wide
add wave -noupdate -radix hexadecimal /feedback_loop_tb/uut/inputA
add wave -noupdate -radix hexadecimal /feedback_loop_tb/uut/inputB
add wave -noupdate -radix hexadecimal /feedback_loop_tb/uut/addsub_out
add wave -noupdate /feedback_loop_tb/uut/scaler_done
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {399500000000 fs} 0}
quietly wave cursor active 1
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {371218089984 fs} {506777995264 fs}

8
src/delay_line.vhd
View File

@ -45,7 +45,7 @@ architecture arch of delay_line is
end component;
--*****SIGNAl DECLARATION*****
signal cnt, cnt_next, cnt_max, cnt_max_next : integer range 0 to MAX_DELAY := 0;
signal cnt, cnt_next : integer range 0 to MAX_DELAY := 0;
signal memory_out : std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
begin
@ -69,15 +69,13 @@ begin
begin
-- DEFAULT VALUES
cnt_next <= cnt;
cnt_max_next <= cnt_max;
if(to_integer(unsigned(delay)) = 0) then
data_out <= data_in;
else
data_out <= memory_out;
-- COUNT GENERATION
cnt_max_next <= to_integer(unsigned(delay)) - 1;
if (cnt >= cnt_max) then
if (cnt >= (to_integer(unsigned(delay)) - 1)) then
cnt_next <= 0;
else
cnt_next <= cnt + 1;
@ -90,10 +88,8 @@ begin
if rising_edge(clk) then
if (reset = '1') then
cnt <= 0;
cnt_max <= 0;
else
cnt <= cnt_next;
cnt_max <= cnt_max_next;
end if;
end if;
end process;

126
src/feedback_loop.vhd
View File

@ -139,10 +139,11 @@ architecture arch of feedback_loop is
--*****CONSTANT DECLARATION*****
constant CONST_MAX : unsigned(DAC_DATA_WIDTH-1 downto 0) := (others => '1');
constant CONST_HALF : unsigned(DAC_DATA_WIDTH-1 downto 0) := (DAC_DATA_WIDTH-1 => '1', others => '0');
constant FACTOR_ONE : unsigned(FACTOR_WIDTH-1 downto 0) := (FACTOR_WIDTH-1 => '1', others => '0');
--*****SIGNAL DECLARATION*****
signal delay_out : std_logic_vector(ADC_DATA_WIDTH downto 0) := (others => '0');
signal latch_out : std_logic_vector(ADC_DATA_WIDTH-1 downto 0) := (others => '0');
signal tmp2 : std_logic_vector(ADC_DATA_WIDTH-1 downto 0) := (others => '0');
signal inputA_wide, inputB_wide : std_logic_vector(DAC_DATA_WIDTH downto 0) := (others => '0');
signal addsub_out, inputA, inputB : std_logic_vector(DAC_DATA_WIDTH-1 downto 0) := (others => '0');
signal scaler_1_out, scaler_2_out, scaler_offset_1, scaler_offset_2 : std_logic_vector(DAC_DATA_WIDTH downto 0) := (others => '0');
@ -186,6 +187,17 @@ begin
data_out => delay_out
);
latch_prc : process (all)
begin
if (delay = (delay'range => '0')) then
tmp2 <= adc_data2;
elsif rising_edge(clk) then
if (adc_done = '1') then
tmp2 <= adc_data2;
end if;
end if;
end process;
addsub_offset_inst : addsub
generic map(
PIPELINE_STAGES => 0,
@ -201,7 +213,6 @@ begin
RES => tmp
);
--TODO: Fix me
offset_factor <= tmp when (factor(FACTOR_WIDTH-1) = '0') else ("0" & factor(FACTOR_WIDTH-2 downto 0));
--*****STAGE III*****
@ -226,7 +237,7 @@ begin
)
port map(
clk => clk,
data_in => adc_data2,
data_in => tmp2,
factor => "10101", --1.32
data_out => scaler_2_out
);
@ -268,17 +279,6 @@ begin
end if;
end process;
latch : process(clk)
begin
if (rising_edge(clk)) then
if (reset = '1') then
latch_out <= (others => '0');
elsif (adc_done) then
latch_out <= adc_data2;
end if;
end if;
end process;
addsub_1_inst : addsub
generic map(
PIPELINE_STAGES => 0,
@ -312,7 +312,7 @@ begin
cap_B_prc : process(all)
begin
if (inputB_wide(DAC_DATA_WIDTH) = '1') then
if (factor(FACTOR_WIDTH-1) = '1') then
if (factor(FACTOR_WIDTH-1) = '1' and scaler_1_out(DAC_DATA_WIDTH) = '0') then
inputB <= (others => '0');
else
inputB <= (others => '1');
@ -322,28 +322,73 @@ begin
end if;
end process;
--*****STAGE IV*****
mux: process(all)
cap_A_prc : process(all)
begin
if (add_input_mux = '1') then
if (inputA_wide(DAC_DATA_WIDTH) = '1') then
--TODO: CAP Needed?
inputA <= (others => '0');
else
inputA <= inputA_wide(DAC_DATA_WIDTH-1 downto 0);
end if;
else
if (addsub_mode = '1') then
--if (factor(FACTOR_WIDTH-1) = '1' and scaler_2_out(DAC_DATA_WIDTH) = '0') then
if (scaler_2_out(DAC_DATA_WIDTH) = '0') then
inputA <= (others => '0');
else
inputA <= (others => '1');
end if;
else
inputA <= inputA_wide(DAC_DATA_WIDTH-1 downto 0);
end if;
end process;
--*****STAGE IV*****
--mux: process(all)
--begin
-- if (add_input_mux = '1') then
-- if (inputA_wide(DAC_DATA_WIDTH) = '1') then
-- --TODO: CAP Needed?
-- inputA <= (others => '0');
-- else
-- inputA <= inputA_wide(DAC_DATA_WIDTH-1 downto 0);
-- end if;
-- else
-- if (addsub_mode = '1') then
-- inputA <= (others => '0');
-- else
-- inputA <= (others => '1');
-- end if;
-- end if;
--end process;
--add_sub_prc : process (all)
-- variable tmp_res : unsigned(inputB'length-1 downto 0) := (others => '0');
--begin
-- if rising_edge(clk) then
-- if (reset = '1') then
-- addsub_out <= (others => '0');
-- else
-- -- Both Inputs
-- if (add_input_mux = '1') then
-- -- ADD
-- if (addsub_mode = '1') then
-- tmp_res := unsigned(inputB) + unsigned(inputA);
-- -- SUB
-- else
-- tmp_res := unsigned(inputB) - unsigned(inputA);
-- end if;
-- addsub_out <= std_logic_vector(tmp_res + CONST_HALF);
-- -- Single Input
-- else
-- -- ADD
-- if (addsub_mode = '1') then
-- addsub_out <= inputB;
-- -- SUB
-- else
-- addsub_out <= not inputB;--std_logic_vector(CONST_MAX - unsigned(inputB));
-- end if;
-- end if;
-- end if;
-- end if;
--end process;
add_sub_prc : process (all)
variable tmp_res : unsigned(inputB'length-1 downto 0) := (others => '0');
variable tmp_res : unsigned(DAC_DATA_WIDTH+1 downto 0) := (others => '0');
begin
if rising_edge(clk) then
if (reset = '1') then
@ -353,12 +398,31 @@ begin
if (add_input_mux = '1') then
-- ADD
if (addsub_mode = '1') then
tmp_res := unsigned(inputB) + unsigned(inputA);
tmp_res := unsigned("00" & inputB) + unsigned("00" & inputA);
tmp_res := tmp_res + ("00" & CONST_HALF);
-- Overflow
if (tmp_res(DAC_DATA_WIDTH+1) = '1') then
addsub_out <= (others => '1');
-- Underflow
elsif (tmp_res(DAC_DATA_WIDTH+1 downto DAC_DATA_WIDTH) = "00") then
addsub_out <= (others => '0');
else
addsub_out <= std_logic_vector(tmp_res(DAC_DATA_WIDTH-1 downto 0));
end if;
-- SUB
else
tmp_res := unsigned(inputB) - unsigned(inputA);
tmp_res := unsigned("00" & inputB) - unsigned("00" & inputA);
tmp_res := tmp_res + ("00" & CONST_HALF);
-- Underflow
if (tmp_res(DAC_DATA_WIDTH+1 downto DAC_DATA_WIDTH) = "11") then
addsub_out <= (others => '0');
-- Overflow
elsif (tmp_res(DAC_DATA_WIDTH) = '1') then
addsub_out <= (others => '1');
else
addsub_out <= std_logic_vector(tmp_res(DAC_DATA_WIDTH-1 downto 0));
end if;
end if;
addsub_out <= std_logic_vector(tmp_res + CONST_HALF);
-- Single Input
else
-- ADD
@ -366,7 +430,7 @@ begin
addsub_out <= inputB;
-- SUB
else
addsub_out <= std_logic_vector(CONST_MAX - unsigned(inputB));
addsub_out <= not inputB;--std_logic_vector(CONST_MAX - unsigned(inputB));
end if;
end if;
end if;

6
src/mult.vhd
View File

@ -25,7 +25,7 @@ end entity;
architecture arch of mult is
signal P_wide : std_logic_vector(A_WIDTH+B_WIDTH+1 downto 0) := (others => '0');
begin
mult_gen : if (UNSIGNED = true) generate
@ -36,14 +36,14 @@ begin
WIDTH_A => A_WIDTH+1, -- Multiplier A-input bus width, 1-25
WIDTH_B => B_WIDTH+1) -- Multiplier B-input bus width, 1-18
port map (
P(A_WIDTH+B_WIDTH+1 downto A_WIDTH+B_WIDTH) => open,
P(A_WIDTH+B_WIDTH-1 downto 0) => P,
P => P_wide,
A => "0" & A,
B => "0" & B,
CE => '1',
CLK => clk,
RST => '0'
);
P <= P_wide(A_WIDTH+B_WIDTH-1 downto 0);
else generate
MULT_MACRO_inst : MULT_MACRO
generic map (

2
src/sim/10kHz_half.vhd
View File

@ -4,5 +4,5 @@ use ieee.numeric_std.all;
package sine_package is
type SINE_ARRAY_TYPE is array (0 to 110) of std_logic_vector(11 downto 0);
constant sine : SINE_ARRAY_TYPE := (x"800", x"83A", x"874", x"8AD", x"8E6", x"91E", x"955", x"98B", x"9C0", x"9F3", x"A25", x"A55", x"A83", x"AAF", x"AD9", x"B01", x"B26", x"B48", x"B68", x"B85", x"B9F", x"BB6", x"BCA", x"BDB", x"BE9", x"BF4", x"BFB", x"BFF", x"C00", x"BFD", x"BF8", x"BEF", x"BE3", x"BD3", x"BC1", x"BAB", x"B92", x"B77", x"B58", x"B37", x"B14", x"AED", x"AC5", x"A9A", x"A6C", x"A3D", x"A0C", x"9DA", x"9A6", x"970", x"93A", x"902", x"8CA", x"890", x"857", x"81D", x"7E3", x"7A9", x"770", x"736", x"6FE", x"6C6", x"690", x"65A", x"626", x"5F4", x"5C3", x"594", x"566", x"53B", x"513", x"4EC", x"4C9", x"4A8", x"489", x"46E", x"455", x"43F", x"42D", x"41D", x"411", x"408", x"403", x"400", x"401", x"405", x"40C", x"417", x"425", x"436", x"44A", x"461", x"47B", x"498", x"4B8", x"4DA", x"4FF", x"527", x"551", x"57D", x"5AB", x"5DB", x"60D", x"640", x"675", x"6AB", x"6E2", x"71A", x"753", x"78C", x"7C6");
constant sine : SINE_ARRAY_TYPE := (x"800", x"83A", x"874", x"8AD", x"8E6", x"91E", x"955", x"98B", x"9C0", x"9F3", x"A25", x"A55", x"A83", x"AAF", x"AD9", x"B01", x"B26", x"B48", x"B68", x"B85", x"B9F", x"BB6", x"BCA", x"BDB", x"BE9", x"BF4", x"BFB", x"BFF", x"C00", x"BFD", x"BF8", x"BEF", x"BE3", x"BD3", x"BC1", x"BAB", x"B92", x"B77", x"B58", x"B37", x"B14", x"AED", x"AC5", x"A9A", x"A6C", x"A3D", x"A0C", x"9DA", x"9A6", x"970", x"93A", x"902", x"8CA", x"890", x"857", x"81D", x"7E3", x"7A9", x"770", x"736", x"6FE", x"6C6", x"690", x"65A", x"626", x"5F4", x"5C3", x"594", x"566", x"53B", x"513", x"4EC", x"4C9", x"4A8", x"489", x"46E", x"455", x"43F", x"42D", x"41D", x"411", x"408", x"403", x"400", x"401", x"405", x"40C", x"417", x"425", x"436", x"44A", x"461", x"47B", x"498", x"4B8", x"4DA", x"4FF", x"527", x"551", x"57D", x"5AB", x"5DB", x"60D", x"640", x"675", x"6AB", x"6E2", x"71A", x"753", x"78C", x"7C6");
end package;

5
src/sim/10kHz_max.vhd
View File

@ -4,5 +4,8 @@ use ieee.numeric_std.all;
package sine_package is
type SINE_ARRAY_TYPE is array (0 to 110) of std_logic_vector(11 downto 0);
constant sine : SINE_ARRAY_TYPE := (x"800", x"874", x"8E7", x"95A", x"9CC", x"A3C", x"AAA", x"B16", x"B80", x"BE6", x"C4A", x"CAA", x"D06", x"D5E", x"DB2", x"E01", x"E4B", x"E90", x"ECF", x"F09", x"F3D", x"F6B", x"F94", x"FB5", x"FD1", x"FE6", x"FF5", x"FFD", x"FFF", x"FFA", x"FEE", x"FDC", x"FC4", x"FA5", x"F80", x"F55", x"F24", x"EED", x"EB0", x"E6E", x"E26", x"DDA", x"D88", x"D33", x"CD8", x"C7A", x"C18", x"BB3", x"B4B", x"AE0", x"A73", x"A04", x"993", x"921", x"8AE", x"83A", x"7C6", x"752", x"6DF", x"66D", x"5FC", x"58D", x"520", x"4B5", x"44D", x"3E8", x"386", x"328", x"2CD", x"278", x"226", x"1DA", x"192", x"150", x"113", x"0DC", x"0AB", x"080", x"05B", x"03C", x"024", x"012", x"006", x"001", x"003", x"00B", x"01A", x"02F", x"04B", x"06C", x"095", x"0C3", x"0F7", x"131", x"170", x"1B5", x"1FF", x"24E", x"2A2", x"2FA", x"356", x"3B6", x"41A", x"480", x"4EA", x"556", x"5C4", x"634", x"6A6", x"719", x"78C");
-- OFFSET: 2048, AMPLITUDE: 2047, FREQUENCY: 10kHz
constant sine2 : SINE_ARRAY_TYPE := (x"800", x"874", x"8E7", x"95A", x"9CC", x"A3C", x"AAA", x"B16", x"B80", x"BE6", x"C4A", x"CAA", x"D06", x"D5E", x"DB2", x"E01", x"E4B", x"E90", x"ECF", x"F09", x"F3D", x"F6B", x"F94", x"FB5", x"FD1", x"FE6", x"FF5", x"FFD", x"FFF", x"FFA", x"FEE", x"FDC", x"FC4", x"FA5", x"F80", x"F55", x"F24", x"EED", x"EB0", x"E6E", x"E26", x"DDA", x"D88", x"D33", x"CD8", x"C7A", x"C18", x"BB3", x"B4B", x"AE0", x"A73", x"A04", x"993", x"921", x"8AE", x"83A", x"7C6", x"752", x"6DF", x"66D", x"5FC", x"58D", x"520", x"4B5", x"44D", x"3E8", x"386", x"328", x"2CD", x"278", x"226", x"1DA", x"192", x"150", x"113", x"0DC", x"0AB", x"080", x"05B", x"03C", x"024", x"012", x"006", x"001", x"003", x"00B", x"01A", x"02F", x"04B", x"06C", x"095", x"0C3", x"0F7", x"131", x"170", x"1B5", x"1FF", x"24E", x"2A2", x"2FA", x"356", x"3B6", x"41A", x"480", x"4EA", x"556", x"5C4", x"634", x"6A6", x"719", x"78C");
-- OFFSET: 2048, AMPLITUDE: 1024, FREQUENCY: 10kHz
constant sine1 : SINE_ARRAY_TYPE := (x"800", x"83A", x"874", x"8AD", x"8E6", x"91E", x"955", x"98B", x"9C0", x"9F3", x"A25", x"A55", x"A83", x"AAF", x"AD9", x"B01", x"B26", x"B48", x"B68", x"B85", x"B9F", x"BB6", x"BCA", x"BDB", x"BE9", x"BF4", x"BFB", x"BFF", x"C00", x"BFD", x"BF8", x"BEF", x"BE3", x"BD3", x"BC1", x"BAB", x"B92", x"B77", x"B58", x"B37", x"B14", x"AED", x"AC5", x"A9A", x"A6C", x"A3D", x"A0C", x"9DA", x"9A6", x"970", x"93A", x"902", x"8CA", x"890", x"857", x"81D", x"7E3", x"7A9", x"770", x"736", x"6FE", x"6C6", x"690", x"65A", x"626", x"5F4", x"5C3", x"594", x"566", x"53B", x"513", x"4EC", x"4C9", x"4A8", x"489", x"46E", x"455", x"43F", x"42D", x"41D", x"411", x"408", x"403", x"400", x"401", x"405", x"40C", x"417", x"425", x"436", x"44A", x"461", x"47B", x"498", x"4B8", x"4DA", x"4FF", x"527", x"551", x"57D", x"5AB", x"5DB", x"60D", x"640", x"675", x"6AB", x"6E2", x"71A", x"753", x"78C", x"7C6");
end package;

195
src/sim/feedback_loop_tb.vhd Normal file
View File

@ -0,0 +1,195 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.typedef_package.all;
use work.sine_package.all;
entity feedback_loop_tb is
end entity;
architecture beh of feedback_loop_tb is
--*****COMPONENT DECLARATION*****
component feedback_loop is
port (
clk : in std_logic;
reset : in std_logic;
adc_data_in1 : in std_logic; -- PMOD-AD1
adc_data_in2 : in std_logic; -- PMOD-AD1
adc_cs_n : out std_logic; -- PMOD-AD1
adc_sclk : out std_logic; -- PMOD-AD1
dac_data_out : out std_logic; -- PMOD-DA3
dac_cs_n : out std_logic; -- PMOD-DA3
dac_ldac : out std_logic; -- PMOD-DA3
dac_sclk : out std_logic; -- PMOD-DA3
-- DYNAMIC CONFIGURATION
addsub_mode : in std_logic; -- (1=ADD, 0=SUB)
add_input_mux : in std_logic; -- (1=ADC Input 2, 0=GND)
delay : in std_logic_vector(DELAY_WIDTH-1 downto 0); -- unsigned delay clock count
factor : in std_logic_vector(FACTOR_WIDTH-1 downto 0); -- 1Q3 Fixed Point
-- DEBUG
reset_debug : in std_logic;
adc_data1_max : out std_logic_vector(ADC_DATA_WIDTH-1 downto 0);
adc_data2_max : out std_logic_vector(ADC_DATA_WIDTH-1 downto 0);
scaler_max : out std_logic_vector(DAC_DATA_WIDTH-1 downto 0);
dac_max : out std_logic_vector(DAC_DATA_WIDTH-1 downto 0)
);
end component;
type ADC_STAGE_TYPE is (ZERO, DATA);
--*****SIGNAL DECLARATION*****
signal clk, reset : std_logic := '0';
signal adc_data_in1, adc_data_in2, adc_cs_n : std_logic := '0';
signal factor : std_logic_vector(FACTOR_WIDTH-1 downto 0) := (others => '0');
signal addsub_mode, add_input_mux : std_logic := '0';
signal delay : std_logic_vector(DELAY_WIDTH-1 downto 0) := (others => '0');
signal adc_stage : ADC_STAGE_TYPE := ZERO;
signal cnt1, cnt2 : integer := 0;
signal input1, input2 : std_logic_vector(ADC_DATA_WIDTH-1 downto 0) := (others => '0');
signal output : std_logic_vector(DAC_DATA_WIDTH-1 downto 0) := (others => '0');
signal sine_done : std_logic := '0';
begin
--*****COMPONENT INSTANTIATION*****
uut : feedback_loop
port map(
clk => clk,
reset => reset,
adc_data_in1 => adc_data_in1,
adc_data_in2 => adc_data_in2,
adc_cs_n => adc_cs_n,
adc_sclk => open,
dac_data_out => open,
dac_cs_n => open,
dac_ldac => open,
dac_sclk => open,
addsub_mode => addsub_mode,
add_input_mux => add_input_mux,
delay => delay,
factor => factor,
reset_debug => '0',
adc_data1_max => open,
adc_data2_max => open,
scaler_max => open,
dac_max => open
);
clk_prc : process
begin
clk <= '1';
wait for 25 ns;
clk <= '0';
wait for 25 ns;
end process;
process
begin
--INITIALISE SIGNALS
reset <= '1';
wait until rising_edge(clk);
wait until rising_edge(clk);
reset <= '0';
--report "Single Input, Positive Feedback, Scale 1.32, Delay 0";
--add_input_mux <= '0';
--addsub_mode <= '1';
--factor <= "10101"; --1.32
--delay <= std_logic_vector(to_unsigned(0,DELAY_WIDTH));
--wait until sine_done = '1';
--report "Single Input, Negative Feedback, Scale 1.32, Delay 0";
--add_input_mux <= '0';
--addsub_mode <= '0';
--factor <= "10101"; --1.32
--delay <= std_logic_vector(to_unsigned(0,DELAY_WIDTH));
--wait until sine_done = '1';
--report "Single Input, Positive Feedback, Scale 0.66, Delay 0";
--add_input_mux <= '0';
--addsub_mode <= '1';
--factor <= "01010"; --0.66
--delay <= std_logic_vector(to_unsigned(0,DELAY_WIDTH));
--wait until sine_done = '1';
--report "Single Input, Positive Feedback, Scale 1.32, Delay 500";
--add_input_mux <= '0';
--addsub_mode <= '1';
--factor <= "10101"; --1.32
--delay <= std_logic_vector(to_unsigned(500,DELAY_WIDTH));
--wait until sine_done = '1';
--report "Double Input, Positive Feedback, Scale 0.66, Delay 0";
--add_input_mux <= '1';
--addsub_mode <= '1';
--factor <= "01010"; --0.66
--delay <= std_logic_vector(to_unsigned(0,DELAY_WIDTH));
--wait until sine_done = '1';
report "Double Input, Negative Feedback, Scale 1.32, Delay 0";
add_input_mux <= '1';
addsub_mode <= '0';
--factor <= "01010"; --0.66
factor <= "10101"; --1.32
delay <= std_logic_vector(to_unsigned(500,DELAY_WIDTH));
wait until sine_done = '1';
wait;
end process;
adc_prc : process (all)
begin
if rising_edge(clk) then
sine_done <= '0';
case (adc_stage) is
when ZERO =>
if (adc_cs_n = '0') then
cnt1 <= cnt1 + 1;
if (cnt1 = 3) then
cnt1 <= 11;
adc_stage <= DATA;
end if;
end if;
when DATA =>
if (adc_cs_n = '0') then
cnt1 <= cnt1 - 1;
if (cnt1 = 0) then
if (cnt2 = sine1'length-1) then
cnt2 <= 0;
sine_done <= '1';
else
cnt2 <= cnt2 + 1;
end if;
cnt1 <= 0;
adc_stage <= ZERO;
end if;
end if;
end case;
end if;
case (adc_stage) is
when ZERO =>
adc_data_in1 <= '0';
adc_data_in2 <= '0';
when DATA =>
adc_data_in1 <= sine1(cnt2)(cnt1);
adc_data_in2 <= sine2(cnt2)(cnt1);
end case;
end process;
io_prc : process (all)
--alias in1 is <<signal uut.adc_data1 : std_logic_vector(ADC_DATA_WIDTH-1 downto 0)>>;
--alias in2 is <<signal uut.adc_data2 : std_logic_vector(ADC_DATA_WIDTH-1 downto 0)>>;
--alias in_done is <<signal uut.adc_done : std_logic>>;
alias in1 is <<signal uut.delay_out : std_logic_vector(ADC_DATA_WIDTH downto 0)>>;
alias in2 is <<signal uut.tmp2 : std_logic_vector(ADC_DATA_WIDTH-1 downto 0)>>;
alias out1 is <<signal uut.addsub_out : std_logic_vector(DAC_DATA_WIDTH-1 downto 0)>>;
alias out_done is <<signal uut.addsub_done : std_logic>>;
begin
if rising_edge(clk) then
if (in1(ADC_DATA_WIDTH) = '1') then
input1 <= in1(ADC_DATA_WIDTH-1 downto 0);
input2 <= in2;
end if;
if (out_done = '1') then
output <= out1;
end if;
end if;
end process;
end architecture;

4
src/typedef_package.vhd
View File

@ -15,8 +15,8 @@ package typedef_package is
constant ADC_DELAY_CLK_CNT : integer := 2;
constant DAC_TRANSFER_CLK_COUNT : integer := 16;
constant MAX_DELAY : integer := 200;
constant DELAY_WIDTH : integer := 8; --at least log2(MAX_DELAY)
constant MAX_DELAY : integer := 1024;
constant DELAY_WIDTH : integer := 10; --at least log2(MAX_DELAY)
constant FACTOR_WIDTH : integer := 5;
constant TIMESTAMP_WIDTH : integer := 32;