* Add documentation
- Zedboard Rev.D Errata * Add debug leds to top entity * Pin mapping
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doc/ZedBoard_RevD.2_Errata_151222.pdf
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doc/ZedBoard_RevD.2_Errata_151222.pdf
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@ -29,7 +29,9 @@ entity feedback_top is
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dac_data_out : out std_logic;
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dac_cs_n : out std_logic;
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dac_ldac : out std_logic;
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dac_sclk : out std_logic
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dac_sclk : out std_logic;
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--DEBUG
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leds : out std_logic_vector(LED_WIDTH-1 downto 0)
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);
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end entity;
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@ -262,4 +264,11 @@ begin
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dac_sclk <= clk_20;
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-- Connect standy to mem_full signal, to prevent simutanuoys read/writing on memory
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mem_full <= not standby;
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-- Connect leds
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led_prc : process(all)
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begin
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leds <= (others => '0');
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leds(LED_WIDTH-1) <= standby;
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end process;
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end architecture;
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@ -31,3 +31,4 @@ set_property PACKAGE_PIN W8 [get_ports dac_sclk]
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set_property IOSTANDARD LVCMOS33 [get_ports dac_sclk]
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set_property IOSTANDARD LVCMOS33 [get_ports areset]
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@ -41,6 +41,8 @@ package typedef_package is
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constant DEBUG_SEND_INTERVAL : integer := 20000000;
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constant LED_WIDTH : integer := 4;
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--TODO: 3-stage sync to delay write-mode 1 clk cycle
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--*****FUNCTION DECLARATIONS*****
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@ -1,134 +0,0 @@
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NET "clk_100" TNM_NET = "TN_gclk";
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TIMESPEC "TS_gclk" = PERIOD "TN_gclk" 10 ns HIGH 50 %;
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# The VGA outputs are turned into an analog voltage by virtue of a resistor
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# network, so the flip flops driving these must sit in the IOBs to minimize
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# timing skew. The RTL code should handle this, but the constraint below
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# is there to fail if something goes wrong about this.
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INST "xillybus_ins/vga_iob_ff[*]" TNM = "tgrp_vga_pads_ffs";
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TIMESPEC "TS_force_iob_ffs" = FROM "tgrp_vga_pads_ffs" 5.5 ns ;
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NET "clk_100" LOC = Y9 | IOSTANDARD=LVCMOS33; # "GCLK"
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NET "GPIO_LED[0]" LOC = T22 | IOSTANDARD=LVCMOS33; # "LD0"
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NET "GPIO_LED[1]" LOC = T21 | IOSTANDARD=LVCMOS33; # "LD1"
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NET "GPIO_LED[2]" LOC = U22 | IOSTANDARD=LVCMOS33; # "LD2"
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NET "GPIO_LED[3]" LOC = U21 | IOSTANDARD=LVCMOS33; # "LD3"
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NET "vga4_blue[0]" LOC = Y21 | IOSTANDARD=LVCMOS33; # "VGA-B1"
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NET "vga4_blue[1]" LOC = Y20 | IOSTANDARD=LVCMOS33; # "VGA-B2"
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NET "vga4_blue[2]" LOC = AB20 | IOSTANDARD=LVCMOS33; # "VGA-B3"
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NET "vga4_blue[3]" LOC = AB19 | IOSTANDARD=LVCMOS33; # "VGA-B4"
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NET "vga4_green[0]" LOC = AB22 | IOSTANDARD=LVCMOS33; # "VGA-G1"
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NET "vga4_green[1]" LOC = AA22 | IOSTANDARD=LVCMOS33; # "VGA-G2"
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NET "vga4_green[2]" LOC = AB21 | IOSTANDARD=LVCMOS33; # "VGA-G3"
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NET "vga4_green[3]" LOC = AA21 | IOSTANDARD=LVCMOS33; # "VGA-G4"
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NET "vga4_red[0]" LOC = V20 | IOSTANDARD=LVCMOS33; # "VGA-R1"
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NET "vga4_red[1]" LOC = U20 | IOSTANDARD=LVCMOS33; # "VGA-R2"
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NET "vga4_red[2]" LOC = V19 | IOSTANDARD=LVCMOS33; # "VGA-R3"
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NET "vga4_red[3]" LOC = V18 | IOSTANDARD=LVCMOS33; # "VGA-R4"
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NET "vga_vsync" LOC = Y19 | IOSTANDARD=LVCMOS33; # "VGA-VS"
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NET "vga_hsync" LOC = AA19 | IOSTANDARD=LVCMOS33; # "VGA-HS"
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# IMPORTANT: Since four LEDs are taken by the Xillybus IP core, the pin
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# placement doesn't match the one given by Digilent.
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# GPIO pin to reset the USB OTG PHY
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NET PS_GPIO[0] LOC = G17 | IOSTANDARD = LVCMOS33; # USB-Reset
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# On-board OLED
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NET PS_GPIO[1] LOC = U11 | IOSTANDARD = LVCMOS33; # OLED-VBAT
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NET PS_GPIO[2] LOC = U12 | IOSTANDARD = LVCMOS33; # OLED-VDD
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NET PS_GPIO[3] LOC = U9 | IOSTANDARD = LVCMOS33; # OLED-RES
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NET PS_GPIO[4] LOC = U10 | IOSTANDARD = LVCMOS33; # OLED-DC
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NET PS_GPIO[5] LOC = AB12 | IOSTANDARD = LVCMOS33; # OLED-SCLK
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NET PS_GPIO[6] LOC = AA12 | IOSTANDARD = LVCMOS33; # OLED-SDIN
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# On-board LEDs. Note that only for LEDs are allocated, as opposed to
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# Digilent's eight, and all placements that follow are shifted by four.
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# There was no other choice, as the tools don't allow unplaced PS GPIO pins.
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NET PS_GPIO[7] LOC = V22 | IOSTANDARD = LVCMOS33; # LD4
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NET PS_GPIO[8] LOC = W22 | IOSTANDARD = LVCMOS33; # LD5
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NET PS_GPIO[9] LOC = U19 | IOSTANDARD = LVCMOS33; # LD6
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NET PS_GPIO[10] LOC = U14 | IOSTANDARD = LVCMOS33; # LD7
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# On-board Slide Switches
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NET PS_GPIO[11] LOC = F22 | IOSTANDARD = LVCMOS33; # SW0
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NET PS_GPIO[12] LOC = G22 | IOSTANDARD = LVCMOS33; # SW1
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NET PS_GPIO[13] LOC = H22 | IOSTANDARD = LVCMOS33; # SW2
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NET PS_GPIO[14] LOC = F21 | IOSTANDARD = LVCMOS33; # SW3
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NET PS_GPIO[15] LOC = H19 | IOSTANDARD = LVCMOS33; # SW4
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NET PS_GPIO[16] LOC = H18 | IOSTANDARD = LVCMOS33; # SW5
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NET PS_GPIO[17] LOC = H17 | IOSTANDARD = LVCMOS33; # SW6
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NET PS_GPIO[18] LOC = M15 | IOSTANDARD = LVCMOS33; # SW7
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# On-board Left, Right, Up, Down, and Select Pushbuttons
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NET PS_GPIO[19] LOC = N15 | IOSTANDARD = LVCMOS33; # BTNL
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NET PS_GPIO[20] LOC = R18 | IOSTANDARD = LVCMOS33; # BTNR
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NET PS_GPIO[21] LOC = T18 | IOSTANDARD = LVCMOS33; # BTNU
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NET PS_GPIO[22] LOC = R16 | IOSTANDARD = LVCMOS33; # BTND
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NET PS_GPIO[23] LOC = P16 | IOSTANDARD = LVCMOS33; # BTNS
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# Pmod JA
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NET PS_GPIO[24] LOC = Y11 | IOSTANDARD = LVCMOS33; # JA1
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NET PS_GPIO[25] LOC = AA11 | IOSTANDARD = LVCMOS33; # JA2
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NET PS_GPIO[26] LOC = Y10 | IOSTANDARD = LVCMOS33; # JA3
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NET PS_GPIO[27] LOC = AA9 | IOSTANDARD = LVCMOS33; # JA4
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NET PS_GPIO[28] LOC = AB11 | IOSTANDARD = LVCMOS33; # JA7
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NET PS_GPIO[29] LOC = AB10 | IOSTANDARD = LVCMOS33; # JA8
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NET PS_GPIO[30] LOC = AB9 | IOSTANDARD = LVCMOS33; # JA9
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NET PS_GPIO[31] LOC = AA8 | IOSTANDARD = LVCMOS33; # JA10
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# Pmod JB
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NET PS_GPIO[32] LOC = W12 | IOSTANDARD = LVCMOS33; # JB1
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NET PS_GPIO[33] LOC = W11 | IOSTANDARD = LVCMOS33; # JB2
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NET PS_GPIO[34] LOC = V10 | IOSTANDARD = LVCMOS33; # JB3
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NET PS_GPIO[35] LOC = W8 | IOSTANDARD = LVCMOS33; # JB4
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NET PS_GPIO[36] LOC = V12 | IOSTANDARD = LVCMOS33; # JB7
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NET PS_GPIO[37] LOC = W10 | IOSTANDARD = LVCMOS33; # JB8
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NET PS_GPIO[38] LOC = V9 | IOSTANDARD = LVCMOS33; # JB9
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NET PS_GPIO[39] LOC = V8 | IOSTANDARD = LVCMOS33; # JB10
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# Pmod JC
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NET PS_GPIO[40] LOC = AB7 | IOSTANDARD = LVCMOS33; # JC1_P (JC1)
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NET PS_GPIO[41] LOC = AB6 | IOSTANDARD = LVCMOS33; # JC1_N (JC2)
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NET PS_GPIO[42] LOC = Y4 | IOSTANDARD = LVCMOS33; # JC2_P (JC3)
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NET PS_GPIO[43] LOC = AA4 | IOSTANDARD = LVCMOS33; # JC2_N (JC4)
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NET PS_GPIO[44] LOC = R6 | IOSTANDARD = LVCMOS33; # JC3_P (JC7)
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NET PS_GPIO[45] LOC = T6 | IOSTANDARD = LVCMOS33; # JC3_N (JC8)
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NET PS_GPIO[46] LOC = T4 | IOSTANDARD = LVCMOS33; # JC4_P (JC9)
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NET PS_GPIO[47] LOC = U4 | IOSTANDARD = LVCMOS33; # JC4_N (JC10)
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# Pmod JD
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NET PS_GPIO[48] LOC = V7 | IOSTANDARD = LVCMOS33; # JD1_P (JD1)
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NET PS_GPIO[49] LOC = W7 | IOSTANDARD = LVCMOS33; # JD1_N (JD2)
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NET PS_GPIO[50] LOC = V5 | IOSTANDARD = LVCMOS33; # JD2_P (JD3)
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NET PS_GPIO[51] LOC = V4 | IOSTANDARD = LVCMOS33; # JD2_N (JD4)
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NET PS_GPIO[52] LOC = W6 | IOSTANDARD = LVCMOS33; # JD3_P (JD7)
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NET PS_GPIO[53] LOC = W5 | IOSTANDARD = LVCMOS33; # JD3_N (JD8)
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NET PS_GPIO[54] LOC = U6 | IOSTANDARD = LVCMOS33; # JD4_P (JD9)
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NET PS_GPIO[55] LOC = U5 | IOSTANDARD = LVCMOS33; # JD4_N (JD10)
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# Pin for detecting USB OTG over-current condition
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NET otg_oc LOC = L16 | IOSTANDARD="LVCMOS33";
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# Pins connected to sound chip
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NET smbus_addr[0] LOC = AB1 | IOSTANDARD=LVCMOS33; # "AC-ADR0"
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NET smbus_addr[1] LOC = Y5 | IOSTANDARD=LVCMOS33; # "AC-ADR1"
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NET smb_sclk LOC = AB4 | IOSTANDARD=LVCMOS33; # "AC-SCK"
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NET smb_sdata LOC = AB5 | IOSTANDARD=LVCMOS33; # "AC-SDA"
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NET audio_dac LOC = Y8 | IOSTANDARD=LVCMOS33; # "AC-GPIO0"
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NET audio_adc LOC = AA7 | IOSTANDARD=LVCMOS33; # "AC-GPIO1"
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NET audio_bclk LOC = AA6 | IOSTANDARD=LVCMOS33; # "AC-GPIO2"
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NET audio_lrclk LOC = Y6 | IOSTANDARD=LVCMOS33; # "AC-GPIO3"
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NET audio_mclk LOC = AB2 | IOSTANDARD=LVCMOS33; # "AC-MCLK"
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@ -36,7 +36,8 @@ entity xillydemo is
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dac_data_out : out std_logic;
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dac_cs_n : out std_logic;
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dac_ldac : out std_logic;
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dac_sclk : out std_logic
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dac_sclk : out std_logic;
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leds : out std_logic_vector(LED_WIDTH-1 downto 0)
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);
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end xillydemo;
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@ -177,7 +178,8 @@ architecture sample_arch of xillydemo is
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dac_data_out : out std_logic;
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dac_cs_n : out std_logic;
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dac_ldac : out std_logic;
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dac_sclk : out std_logic
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dac_sclk : out std_logic;
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leds : out std_logic_vector(LED_WIDTH-1 downto 0)
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);
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end component;
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@ -343,7 +345,7 @@ begin
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mem_wen => user_w_config_wren,
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mem_full => user_w_config_full,
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--FPGA
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clk_in => clk_ext,
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clk_in => clk_100,
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areset => areset,
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areset_debug => areset_debug,
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async_pulse => async_pulse,
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@ -355,7 +357,8 @@ begin
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dac_data_out => dac_data_out,
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dac_cs_n => dac_cs_n,
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dac_ldac => dac_ldac,
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dac_sclk => dac_sclk
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dac_sclk => dac_sclk,
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leds => leds
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);
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audio_ins : i2s_audio
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@ -1,5 +1,5 @@
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create_clock -name gclk -period 10 [get_ports "clk_100"]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets "clk_100"]
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create_clock -period 10.000 -name gclk [get_ports clk_100]
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#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_100]
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# Vivado constraints unrelated clocks. So set false paths.
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set_false_path -from [get_clocks clk_fpga_1] -to [get_clocks vga_clk_ins/*]
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@ -9,42 +9,91 @@ set_false_path -from [get_clocks vga_clk_ins/*] -to [get_clocks clk_fpga_1]
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# network, so the flip flops driving these must sit in the IOBs to minimize
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# timing skew. The RTL code should handle this, but the constraint below
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# is there to fail if something goes wrong about this.
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set_output_delay 5.5 [get_ports {vga*}]
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set_output_delay 5.500 [get_ports vga*]
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set_property -dict "PACKAGE_PIN Y9 IOSTANDARD LVCMOS33" [get_ports "clk_100"]
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set_property -dict "PACKAGE_PIN T22 IOSTANDARD LVCMOS33" [get_ports "GPIO_LED[0]"]
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set_property -dict "PACKAGE_PIN T21 IOSTANDARD LVCMOS33" [get_ports "GPIO_LED[1]"]
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set_property -dict "PACKAGE_PIN U22 IOSTANDARD LVCMOS33" [get_ports "GPIO_LED[2]"]
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set_property -dict "PACKAGE_PIN U21 IOSTANDARD LVCMOS33" [get_ports "GPIO_LED[3]"]
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set_property -dict "PACKAGE_PIN Y21 IOSTANDARD LVCMOS33" [get_ports "vga4_blue[0]"]
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set_property -dict "PACKAGE_PIN Y20 IOSTANDARD LVCMOS33" [get_ports "vga4_blue[1]"]
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set_property -dict "PACKAGE_PIN AB20 IOSTANDARD LVCMOS33" [get_ports "vga4_blue[2]"]
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set_property -dict "PACKAGE_PIN AB19 IOSTANDARD LVCMOS33" [get_ports "vga4_blue[3]"]
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set_property -dict "PACKAGE_PIN AB22 IOSTANDARD LVCMOS33" [get_ports "vga4_green[0]"]
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set_property -dict "PACKAGE_PIN AA22 IOSTANDARD LVCMOS33" [get_ports "vga4_green[1]"]
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set_property -dict "PACKAGE_PIN AB21 IOSTANDARD LVCMOS33" [get_ports "vga4_green[2]"]
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set_property -dict "PACKAGE_PIN AA21 IOSTANDARD LVCMOS33" [get_ports "vga4_green[3]"]
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set_property -dict "PACKAGE_PIN V20 IOSTANDARD LVCMOS33" [get_ports "vga4_red[0]"]
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set_property -dict "PACKAGE_PIN U20 IOSTANDARD LVCMOS33" [get_ports "vga4_red[1]"]
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set_property -dict "PACKAGE_PIN V19 IOSTANDARD LVCMOS33" [get_ports "vga4_red[2]"]
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set_property -dict "PACKAGE_PIN V18 IOSTANDARD LVCMOS33" [get_ports "vga4_red[3]"]
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set_property -dict "PACKAGE_PIN Y19 IOSTANDARD LVCMOS33" [get_ports "vga_vsync"]
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set_property -dict "PACKAGE_PIN AA19 IOSTANDARD LVCMOS33" [get_ports "vga_hsync"]
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set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS33} [get_ports clk_100]
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set_property -dict {PACKAGE_PIN T22 IOSTANDARD LVCMOS33} [get_ports {GPIO_LED[0]}]
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set_property -dict {PACKAGE_PIN T21 IOSTANDARD LVCMOS33} [get_ports {GPIO_LED[1]}]
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set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS33} [get_ports {GPIO_LED[2]}]
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set_property -dict {PACKAGE_PIN U21 IOSTANDARD LVCMOS33} [get_ports {GPIO_LED[3]}]
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set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS33} [get_ports {vga4_blue[0]}]
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set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports {vga4_blue[1]}]
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set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS33} [get_ports {vga4_blue[2]}]
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set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS33} [get_ports {vga4_blue[3]}]
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set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS33} [get_ports {vga4_green[0]}]
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set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS33} [get_ports {vga4_green[1]}]
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set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS33} [get_ports {vga4_green[2]}]
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set_property -dict {PACKAGE_PIN AA21 IOSTANDARD LVCMOS33} [get_ports {vga4_green[3]}]
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set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS33} [get_ports {vga4_red[0]}]
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set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVCMOS33} [get_ports {vga4_red[1]}]
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set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS33} [get_ports {vga4_red[2]}]
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set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports {vga4_red[3]}]
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set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33} [get_ports vga_vsync]
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set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS33} [get_ports vga_hsync]
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# IMPORTANT: Since four LEDs are taken by the Xillybus IP core, the pin
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# placement doesn't match the one given by Digilent.
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# Pin for detecting USB OTG over-current condition
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set_property -dict "PACKAGE_PIN L16 IOSTANDARD LVCMOS33" [get_ports "otg_oc"]
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set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports otg_oc]
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# Pins connected to sound chip
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set_property -dict "PACKAGE_PIN AB1 IOSTANDARD LVCMOS33" [get_ports "smbus_addr[0]"]
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set_property -dict "PACKAGE_PIN Y5 IOSTANDARD LVCMOS33" [get_ports "smbus_addr[1]"]
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set_property -dict "PACKAGE_PIN AB4 IOSTANDARD LVCMOS33" [get_ports "smb_sclk"]
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set_property -dict "PACKAGE_PIN AB5 IOSTANDARD LVCMOS33" [get_ports "smb_sdata"]
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set_property -dict {PACKAGE_PIN AB1 IOSTANDARD LVCMOS33} [get_ports {smbus_addr[0]}]
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set_property -dict {PACKAGE_PIN Y5 IOSTANDARD LVCMOS33} [get_ports {smbus_addr[1]}]
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set_property -dict {PACKAGE_PIN AB4 IOSTANDARD LVCMOS33} [get_ports smb_sclk]
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set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS33} [get_ports smb_sdata]
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set_property -dict "PACKAGE_PIN Y8 IOSTANDARD LVCMOS33" [get_ports "audio_dac"]
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set_property -dict "PACKAGE_PIN AA7 IOSTANDARD LVCMOS33" [get_ports "audio_adc"]
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set_property -dict "PACKAGE_PIN AA6 IOSTANDARD LVCMOS33" [get_ports "audio_bclk"]
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set_property -dict "PACKAGE_PIN Y6 IOSTANDARD LVCMOS33" [get_ports "audio_lrclk"]
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set_property -dict "PACKAGE_PIN AB2 IOSTANDARD LVCMOS33" [get_ports "audio_mclk"]
|
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set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVCMOS33} [get_ports audio_dac]
|
||||
set_property -dict {PACKAGE_PIN AA7 IOSTANDARD LVCMOS33} [get_ports audio_adc]
|
||||
set_property -dict {PACKAGE_PIN AA6 IOSTANDARD LVCMOS33} [get_ports audio_bclk]
|
||||
set_property -dict {PACKAGE_PIN Y6 IOSTANDARD LVCMOS33} [get_ports audio_lrclk]
|
||||
set_property -dict {PACKAGE_PIN AB2 IOSTANDARD LVCMOS33} [get_ports audio_mclk]
|
||||
|
||||
|
||||
create_clock -period 100.000 -name sys_clk -waveform {0.000 50.000} [get_ports clk_ext]
|
||||
create_clock -period 50.000 -name VIRTUAL_dac_sclk_OBUF -waveform {0.000 25.000}
|
||||
set_input_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -clock_fall -min -add_delay -10.000 [get_ports adc_data_in1]
|
||||
set_input_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -clock_fall -max -add_delay 10.000 [get_ports adc_data_in1]
|
||||
set_input_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -clock_fall -min -add_delay -10.000 [get_ports adc_data_in2]
|
||||
set_input_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -clock_fall -max -add_delay 10.000 [get_ports adc_data_in2]
|
||||
set_output_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -clock_fall -min -add_delay -5.000 [get_ports adc_cs_n]
|
||||
set_output_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -clock_fall -max -add_delay 10.000 [get_ports adc_cs_n]
|
||||
set_output_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -min -add_delay -5.000 [get_ports dac_cs_n]
|
||||
set_output_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -max -add_delay 5.000 [get_ports dac_cs_n]
|
||||
set_output_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -min -add_delay -5.000 [get_ports dac_data_out]
|
||||
set_output_delay -clock [get_clocks VIRTUAL_dac_sclk_OBUF] -max -add_delay 10.000 [get_ports dac_data_out]
|
||||
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports adc_cs_n]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports adc_data_in1]
|
||||
set_property PACKAGE_PIN AB7 [get_ports adc_cs_n]
|
||||
set_property PACKAGE_PIN AB6 [get_ports adc_data_in1]
|
||||
set_property PACKAGE_PIN Y4 [get_ports adc_data_in2]
|
||||
set_property PACKAGE_PIN AA4 [get_ports adc_sclk]
|
||||
set_property PACKAGE_PIN V7 [get_ports dac_cs_n]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports dac_cs_n]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports adc_data_in2]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports adc_sclk]
|
||||
set_property PACKAGE_PIN W7 [get_ports dac_data_out]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports dac_data_out]
|
||||
set_property PACKAGE_PIN V5 [get_ports dac_ldac]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports dac_ldac]
|
||||
set_property PACKAGE_PIN V4 [get_ports dac_sclk]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports dac_sclk]
|
||||
set_property PACKAGE_PIN AA9 [get_ports clk_ext]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports clk_ext]
|
||||
set_property PACKAGE_PIN Y11 [get_ports async_pulse]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports async_pulse]
|
||||
set_property PACKAGE_PIN U14 [get_ports {leds[3]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {leds[3]}]
|
||||
set_property PACKAGE_PIN U19 [get_ports {leds[2]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {leds[2]}]
|
||||
set_property PACKAGE_PIN W22 [get_ports {leds[1]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {leds[1]}]
|
||||
set_property PACKAGE_PIN V22 [get_ports {leds[0]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {leds[0]}]
|
||||
set_property PACKAGE_PIN M15 [get_ports astandby]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports astandby]
|
||||
set_property PACKAGE_PIN P16 [get_ports areset]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports areset]
|
||||
set_property PACKAGE_PIN T18 [get_ports areset_debug]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports areset_debug]
|
||||
|
||||
@ -247,6 +247,7 @@
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TargetConstrsFile" Val="$PPRDIR/../vivado-essentials/xillydemo.xdc"/>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
@ -319,7 +320,7 @@
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
|
||||
<Step Id="init_design"/>
|
||||
@ -332,6 +333,7 @@
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
|
||||
Loading…
Reference in New Issue
Block a user