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Day 1 Labor Fixes

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This commit is contained in:
John Ring 2021-03-22 18:17:08 +01:00
parent ad89405df7
commit abe34fd0fc
2 changed files with 55 additions and 7 deletions
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45
src/feedback_loop.vhd
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@ -139,7 +139,7 @@ architecture arch of feedback_loop is
--*****SIGNAL DECLARATION*****
signal delay_out : std_logic_vector(ADC_DATA_WIDTH downto 0) := (others => '0');
signal latch_out : std_logic_vector(ADC_DATA_WIDTH-1 downto 0) := (others => '0');
signal scaler_out, addsub_out, inputA : std_logic_vector(DAC_DATA_WIDTH-1 downto 0) := (others => '0');
signal scaler_out, addsub_out, inputA, inputB, scaler_offset : std_logic_vector(DAC_DATA_WIDTH-1 downto 0) := (others => '0');
signal scaler_done, addsub_done : std_logic := '0';
begin
@ -180,7 +180,7 @@ begin
);
--*****STAGE III*****
scaler_inst : scaler
scaler_A_inst : scaler
generic map(
DATA_WIDTH => ADC_DATA_WIDTH,
FACTOR_WIDTH => FACTOR_WIDTH,
@ -194,6 +194,20 @@ begin
data_out(DAC_DATA_WIDTH-1 downto 0) => scaler_out
);
scaler_offset_inst : scaler
generic map(
DATA_WIDTH => ADC_DATA_WIDTH,
FACTOR_WIDTH => FACTOR_WIDTH,
PIPELINE_STAGES => 1
)
port map(
clk => clk,
data_in => (ADC_DATA_WIDTH-1 => '0', others => '1'),
factor => "0" & factor(FACTOR_WIDTH-2 downto 0),
data_out(DAC_DATA_WIDTH) => open, --Truncate result
data_out(DAC_DATA_WIDTH-1 downto 0) => scaler_offset
);
process(clk)
begin
if (rising_edge(clk)) then
@ -216,6 +230,21 @@ begin
end if;
end process;
addsub_instB : addsub
generic map(
PIPELINE_STAGES => 0,
DATA_WIDTH => DAC_DATA_WIDTH
)
port map(
clk => clk,
reset => reset,
mode => '0',
cap => '0',
A => scaler_out,
B => scaler_offset,
RES => inputB
);
--*****STAGE IV*****
mux: process(all)
@ -223,11 +252,15 @@ begin
if (add_input_mux = '1') then
inputA <= latch_out & "0000";
else
inputA <= (others => '0');
if (addsub_mode = '1') then
inputA <= (others => '0');
else
inputA <= (others => '1');
end if;
end if;
end process;
addsub_inst : addsub
addsub_instA : addsub
generic map(
PIPELINE_STAGES => 1,
DATA_WIDTH => DAC_DATA_WIDTH
@ -238,7 +271,7 @@ begin
mode => addsub_mode,
cap => add_input_mux,
A => inputA,
B => scaler_out,
B => inputB,
RES => addsub_out
);
@ -303,4 +336,4 @@ begin
end architecture;
end architecture;

17
src/feedback_top.vhd
View File

@ -148,6 +148,7 @@ architecture arch of feedback_top is
signal config_addr : std_logic_vector(CONFIG_MEM_ADDR_WIDTH-1 downto 0) := (others => '0');
signal config_ren : std_logic := '0';
signal config_data : std_logic_vector(CONFIG_DATA_WIDTH-1 downto 0) := (others => '0');
signal sync_led : std_logic := '0';
begin
@ -270,6 +271,20 @@ begin
begin
leds <= (others => '0');
leds(LED_WIDTH-1) <= standby;
leds(LED_WIDTH-2) <= sync_led;
end process;
end architecture;
sync_debug : process(all)
begin
if rising_edge(clk_20) then
if (reset = '1') then
sync_led <= '0';
else
if (sync_pulse = '1') then
sync_led <= '1';
end if;
end if;
end if;
end process;
end architecture;