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Fix Scaling Offset

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Greek 2021-03-23 02:16:23 +01:00 committed by Greek64
parent abe34fd0fc
commit b6357a993e
1 changed files with 30 additions and 14 deletions
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44
src/feedback_loop.vhd
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@ -139,8 +139,10 @@ architecture arch of feedback_loop is
--*****SIGNAL DECLARATION***** --*****SIGNAL DECLARATION*****
signal delay_out : std_logic_vector(ADC_DATA_WIDTH downto 0) := (others => '0'); signal delay_out : std_logic_vector(ADC_DATA_WIDTH downto 0) := (others => '0');
signal latch_out : std_logic_vector(ADC_DATA_WIDTH-1 downto 0) := (others => '0'); signal latch_out : std_logic_vector(ADC_DATA_WIDTH-1 downto 0) := (others => '0');
signal scaler_out, addsub_out, inputA, inputB, scaler_offset : std_logic_vector(DAC_DATA_WIDTH-1 downto 0) := (others => '0'); signal addsub_out, inputA, inputB : std_logic_vector(DAC_DATA_WIDTH-1 downto 0) := (others => '0');
signal scaler_out, scaler_offset : std_logic_vector(DAC_DATA_WIDTH downto 0) := (others => '0');
signal scaler_done, addsub_done : std_logic := '0'; signal scaler_done, addsub_done : std_logic := '0';
signal offset_factor : std_logic_vector(FACTOR_WIDTH-1 downto 0) := (others => '0');
begin begin
@ -179,6 +181,21 @@ begin
data_out => delay_out data_out => delay_out
); );
addsub_offset_inst : addsub
generic map(
PIPELINE_STAGES => 1,
DATA_WIDTH => FACTOR_WIDTH
)
port map(
clk => clk,
reset => reset,
mode => '0',
cap => '0',
A => (FACTOR_WIDTH-1 => '1', others => '0'),
B => factor,
RES => offset_factor
);
--*****STAGE III***** --*****STAGE III*****
scaler_A_inst : scaler scaler_A_inst : scaler
generic map( generic map(
@ -187,11 +204,10 @@ begin
PIPELINE_STAGES => 1 PIPELINE_STAGES => 1
) )
port map( port map(
clk => clk, clk => clk,
data_in => delay_out(ADC_DATA_WIDTH-1 downto 0), data_in => delay_out(ADC_DATA_WIDTH-1 downto 0),
factor => factor, factor => factor,
data_out(DAC_DATA_WIDTH) => open, --Truncate result data_out => scaler_out
data_out(DAC_DATA_WIDTH-1 downto 0) => scaler_out
); );
scaler_offset_inst : scaler scaler_offset_inst : scaler
@ -201,11 +217,10 @@ begin
PIPELINE_STAGES => 1 PIPELINE_STAGES => 1
) )
port map( port map(
clk => clk, clk => clk,
data_in => (ADC_DATA_WIDTH-1 => '0', others => '1'), data_in => (ADC_DATA_WIDTH-1 => '0', others => '1'),
factor => "0" & factor(FACTOR_WIDTH-2 downto 0), factor => offset_factor,
data_out(DAC_DATA_WIDTH) => open, --Truncate result data_out => scaler_offset
data_out(DAC_DATA_WIDTH-1 downto 0) => scaler_offset
); );
process(clk) process(clk)
@ -233,16 +248,17 @@ begin
addsub_instB : addsub addsub_instB : addsub
generic map( generic map(
PIPELINE_STAGES => 0, PIPELINE_STAGES => 0,
DATA_WIDTH => DAC_DATA_WIDTH DATA_WIDTH => DAC_DATA_WIDTH+1
) )
port map( port map(
clk => clk, clk => clk,
reset => reset, reset => reset,
mode => '0', mode => not factor(FACTOR_WIDTH-1),
cap => '0', cap => '0',
A => scaler_out, A => scaler_out,
B => scaler_offset, B => scaler_offset,
RES => inputB RES(DAC_DATA_WIDTH) => open, --Truncate Carry Bit
RES(DAC_DATA_WIDTH-1 downto 0) => inputB
); );
--*****STAGE IV***** --*****STAGE IV*****