greek64/labor-mst
1
0
Fork 0
Code Issues Releases Activity

* Modify xillinux vivado project

Browse Source 
- Add custom xillybus IP core to vivado design
	- Add feedback_top
TODO: Remove PS_GPIO and connect custom pins
This commit is contained in:
Greek 2020-04-26 17:36:25 +02:00
parent 4fc3cfb9a3
commit bb07d0a072
5 changed files with 332 additions and 495 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
xillinux-syn/cores/xillybus_core.ngc
View File

File diff suppressed because one or more lines are too long

171
xillinux-syn/vhdl/src/xillybus.v
View File

@ -5,21 +5,15 @@ module xillybus(GPIO_LED, quiesce, MIO, PS_SRSTB, PS_CLK, PS_PORB, DDR_Clk,
DDR_Addr, DDR_ODT, DDR_DRSTB, DDR_DQ, DDR_DM, DDR_DQS, DDR_DQS_n, DDR_VRN,
DDR_VRP, bus_clk, PS_GPIO, otg_oc, clk_100, vga4_red, vga4_green, vga4_blue,
vga_hsync, vga_vsync, user_clk, user_wren, user_wstrb, user_rden,
user_rd_data, user_wr_data, user_addr, user_irq, user_r_smb_rden,
user_r_smb_data, user_r_smb_empty, user_r_smb_eof, user_r_smb_open,
user_w_smb_wren, user_w_smb_data, user_w_smb_full, user_w_smb_open,
user_rd_data, user_wr_data, user_addr, user_irq, user_r_debug_rden,
user_r_debug_data, user_r_debug_empty, user_r_debug_eof, user_r_debug_open,
user_w_config_wren, user_w_config_data, user_w_config_full,
user_w_config_open, user_config_addr, user_config_addr_update,
user_r_audio_rden, user_r_audio_data, user_r_audio_empty, user_r_audio_eof,
user_r_audio_open, user_w_audio_wren, user_w_audio_data, user_w_audio_full,
user_w_audio_open, user_r_read_32_rden, user_r_read_32_data,
user_r_read_32_empty, user_r_read_32_eof, user_r_read_32_open,
user_w_write_32_wren, user_w_write_32_data, user_w_write_32_full,
user_w_write_32_open, user_r_read_8_rden, user_r_read_8_data,
user_r_read_8_empty, user_r_read_8_eof, user_r_read_8_open,
user_w_write_8_wren, user_w_write_8_data, user_w_write_8_full,
user_w_write_8_open, user_r_mem_8_rden, user_r_mem_8_data,
user_r_mem_8_empty, user_r_mem_8_eof, user_r_mem_8_open, user_w_mem_8_wren,
user_w_mem_8_data, user_w_mem_8_full, user_w_mem_8_open, user_mem_8_addr,
user_mem_8_addr_update);
user_w_audio_open, user_r_smb_rden, user_r_smb_data, user_r_smb_empty,
user_r_smb_eof, user_r_smb_open, user_w_smb_wren, user_w_smb_data,
user_w_smb_full, user_w_smb_open);
input PS_SRSTB;
input PS_CLK;
@ -28,26 +22,18 @@ module xillybus(GPIO_LED, quiesce, MIO, PS_SRSTB, PS_CLK, PS_PORB, DDR_Clk,
input clk_100;
input [31:0] user_rd_data;
input user_irq;
input [7:0] user_r_smb_data;
input user_r_smb_empty;
input user_r_smb_eof;
input user_w_smb_full;
input [31:0] user_r_debug_data;
input user_r_debug_empty;
input user_r_debug_eof;
input user_w_config_full;
input [31:0] user_r_audio_data;
input user_r_audio_empty;
input user_r_audio_eof;
input user_w_audio_full;
input [31:0] user_r_read_32_data;
input user_r_read_32_empty;
input user_r_read_32_eof;
input user_w_write_32_full;
input [7:0] user_r_read_8_data;
input user_r_read_8_empty;
input user_r_read_8_eof;
input user_w_write_8_full;
input [7:0] user_r_mem_8_data;
input user_r_mem_8_empty;
input user_r_mem_8_eof;
input user_w_mem_8_full;
input [7:0] user_r_smb_data;
input user_r_smb_empty;
input user_r_smb_eof;
input user_w_smb_full;
output [3:0] GPIO_LED;
output quiesce;
output DDR_WEB;
@ -63,33 +49,23 @@ module xillybus(GPIO_LED, quiesce, MIO, PS_SRSTB, PS_CLK, PS_PORB, DDR_Clk,
output user_rden;
output [31:0] user_wr_data;
output [31:0] user_addr;
output user_r_smb_rden;
output user_r_smb_open;
output user_w_smb_wren;
output [7:0] user_w_smb_data;
output user_w_smb_open;
output user_r_debug_rden;
output user_r_debug_open;
output user_w_config_wren;
output [31:0] user_w_config_data;
output user_w_config_open;
output [15:0] user_config_addr;
output user_config_addr_update;
output user_r_audio_rden;
output user_r_audio_open;
output user_w_audio_wren;
output [31:0] user_w_audio_data;
output user_w_audio_open;
output user_r_read_32_rden;
output user_r_read_32_open;
output user_w_write_32_wren;
output [31:0] user_w_write_32_data;
output user_w_write_32_open;
output user_r_read_8_rden;
output user_r_read_8_open;
output user_w_write_8_wren;
output [7:0] user_w_write_8_data;
output user_w_write_8_open;
output user_r_mem_8_rden;
output user_r_mem_8_open;
output user_w_mem_8_wren;
output [7:0] user_w_mem_8_data;
output user_w_mem_8_open;
output [4:0] user_mem_8_addr;
output user_mem_8_addr_update;
output user_r_smb_rden;
output user_r_smb_open;
output user_w_smb_wren;
output [7:0] user_w_smb_data;
output user_w_smb_open;
inout [53:0] MIO;
inout DDR_Clk;
inout DDR_Clk_n;
@ -163,10 +139,6 @@ module xillybus(GPIO_LED, quiesce, MIO, PS_SRSTB, PS_CLK, PS_PORB, DDR_Clk,
wire vga_vsync_w;
wire USB0_VBUS_PWRFAULT;
// This perl snippet turns the input/output ports to wires, so only
// those that really connect something become real ports (input/output
// keywords are used to create global variables)
assign USB0_VBUS_PWRFAULT = !otg_oc;
// synthesis attribute IOB of vga_iob_ff is "TRUE"
@ -275,57 +247,46 @@ module xillybus(GPIO_LED, quiesce, MIO, PS_SRSTB, PS_CLK, PS_PORB, DDR_Clk,
.xillybus_lite_0_user_irq_pin ( user_irq )
);
xillybus_core xillybus_core_ins(.user_r_mem_8_rden_w(user_r_mem_8_rden),
.user_r_mem_8_data_w(user_r_mem_8_data), .user_r_mem_8_empty_w(user_r_mem_8_empty),
.user_r_mem_8_eof_w(user_r_mem_8_eof), .user_r_mem_8_open_w(user_r_mem_8_open),
.user_w_mem_8_wren_w(user_w_mem_8_wren), .user_w_mem_8_data_w(user_w_mem_8_data),
.user_w_mem_8_full_w(user_w_mem_8_full), .user_w_mem_8_open_w(user_w_mem_8_open),
.user_mem_8_addr_w(user_mem_8_addr), .user_mem_8_addr_update_w(user_mem_8_addr_update),
.GPIO_LED_w(GPIO_LED), .bus_clk_w(bus_clk), .bus_rst_n_w(bus_rst_n),
.S_AXI_AWADDR_w(S_AXI_AWADDR), .S_AXI_AWVALID_w(S_AXI_AWVALID),
.S_AXI_WDATA_w(S_AXI_WDATA), .quiesce_w(quiesce),
.S_AXI_WSTRB_w(S_AXI_WSTRB), .S_AXI_WVALID_w(S_AXI_WVALID),
.S_AXI_BREADY_w(S_AXI_BREADY), .S_AXI_ARADDR_w(S_AXI_ARADDR),
.S_AXI_ARVALID_w(S_AXI_ARVALID), .S_AXI_RREADY_w(S_AXI_RREADY),
.S_AXI_ARREADY_w(S_AXI_ARREADY), .S_AXI_RDATA_w(S_AXI_RDATA),
.S_AXI_RRESP_w(S_AXI_RRESP), .S_AXI_RVALID_w(S_AXI_RVALID),
.S_AXI_WREADY_w(S_AXI_WREADY), .S_AXI_BRESP_w(S_AXI_BRESP),
.S_AXI_BVALID_w(S_AXI_BVALID), .S_AXI_AWREADY_w(S_AXI_AWREADY),
.M_AXI_ACP_ARREADY_w(M_AXI_ACP_ARREADY), .M_AXI_ACP_ARVALID_w(M_AXI_ACP_ARVALID),
.M_AXI_ACP_ARADDR_w(M_AXI_ACP_ARADDR), .M_AXI_ACP_ARLEN_w(M_AXI_ACP_ARLEN),
.M_AXI_ACP_ARSIZE_w(M_AXI_ACP_ARSIZE), .M_AXI_ACP_ARBURST_w(M_AXI_ACP_ARBURST),
.M_AXI_ACP_ARPROT_w(M_AXI_ACP_ARPROT), .M_AXI_ACP_ARCACHE_w(M_AXI_ACP_ARCACHE),
.M_AXI_ACP_RREADY_w(M_AXI_ACP_RREADY), .M_AXI_ACP_RVALID_w(M_AXI_ACP_RVALID),
.M_AXI_ACP_RDATA_w(M_AXI_ACP_RDATA), .user_r_smb_rden_w(user_r_smb_rden),
.user_r_smb_data_w(user_r_smb_data), .user_r_smb_empty_w(user_r_smb_empty),
.user_r_smb_eof_w(user_r_smb_eof), .M_AXI_ACP_RRESP_w(M_AXI_ACP_RRESP),
.user_r_smb_open_w(user_r_smb_open), .M_AXI_ACP_RLAST_w(M_AXI_ACP_RLAST),
.M_AXI_ACP_AWREADY_w(M_AXI_ACP_AWREADY), .M_AXI_ACP_AWVALID_w(M_AXI_ACP_AWVALID),
.M_AXI_ACP_AWADDR_w(M_AXI_ACP_AWADDR), .M_AXI_ACP_AWLEN_w(M_AXI_ACP_AWLEN),
.M_AXI_ACP_AWSIZE_w(M_AXI_ACP_AWSIZE), .user_w_smb_wren_w(user_w_smb_wren),
.user_w_smb_data_w(user_w_smb_data), .user_w_smb_full_w(user_w_smb_full),
.user_w_smb_open_w(user_w_smb_open), .M_AXI_ACP_AWBURST_w(M_AXI_ACP_AWBURST),
.M_AXI_ACP_AWPROT_w(M_AXI_ACP_AWPROT), .M_AXI_ACP_AWCACHE_w(M_AXI_ACP_AWCACHE),
.M_AXI_ACP_WREADY_w(M_AXI_ACP_WREADY), .user_r_audio_rden_w(user_r_audio_rden),
xillybus_core xillybus_core_ins(.GPIO_LED_w(GPIO_LED), .bus_clk_w(bus_clk),
.bus_rst_n_w(bus_rst_n), .S_AXI_AWADDR_w(S_AXI_AWADDR),
.S_AXI_AWVALID_w(S_AXI_AWVALID), .S_AXI_WDATA_w(S_AXI_WDATA),
.quiesce_w(quiesce), .S_AXI_WSTRB_w(S_AXI_WSTRB),
.S_AXI_WVALID_w(S_AXI_WVALID), .S_AXI_BREADY_w(S_AXI_BREADY),
.S_AXI_ARADDR_w(S_AXI_ARADDR), .S_AXI_ARVALID_w(S_AXI_ARVALID),
.S_AXI_RREADY_w(S_AXI_RREADY), .S_AXI_ARREADY_w(S_AXI_ARREADY),
.S_AXI_RDATA_w(S_AXI_RDATA), .S_AXI_RRESP_w(S_AXI_RRESP),
.S_AXI_RVALID_w(S_AXI_RVALID), .S_AXI_WREADY_w(S_AXI_WREADY),
.S_AXI_BRESP_w(S_AXI_BRESP), .S_AXI_BVALID_w(S_AXI_BVALID),
.S_AXI_AWREADY_w(S_AXI_AWREADY), .M_AXI_ACP_ARREADY_w(M_AXI_ACP_ARREADY),
.M_AXI_ACP_ARVALID_w(M_AXI_ACP_ARVALID), .M_AXI_ACP_ARADDR_w(M_AXI_ACP_ARADDR),
.M_AXI_ACP_ARLEN_w(M_AXI_ACP_ARLEN), .M_AXI_ACP_ARSIZE_w(M_AXI_ACP_ARSIZE),
.M_AXI_ACP_ARBURST_w(M_AXI_ACP_ARBURST), .M_AXI_ACP_ARPROT_w(M_AXI_ACP_ARPROT),
.M_AXI_ACP_ARCACHE_w(M_AXI_ACP_ARCACHE), .M_AXI_ACP_RREADY_w(M_AXI_ACP_RREADY),
.M_AXI_ACP_RVALID_w(M_AXI_ACP_RVALID), .M_AXI_ACP_RDATA_w(M_AXI_ACP_RDATA),
.user_r_debug_rden_w(user_r_debug_rden), .user_r_debug_data_w(user_r_debug_data),
.user_r_debug_empty_w(user_r_debug_empty), .user_r_debug_eof_w(user_r_debug_eof),
.M_AXI_ACP_RRESP_w(M_AXI_ACP_RRESP), .user_r_debug_open_w(user_r_debug_open),
.M_AXI_ACP_RLAST_w(M_AXI_ACP_RLAST), .M_AXI_ACP_AWREADY_w(M_AXI_ACP_AWREADY),
.M_AXI_ACP_AWVALID_w(M_AXI_ACP_AWVALID), .M_AXI_ACP_AWADDR_w(M_AXI_ACP_AWADDR),
.M_AXI_ACP_AWLEN_w(M_AXI_ACP_AWLEN), .M_AXI_ACP_AWSIZE_w(M_AXI_ACP_AWSIZE),
.user_w_config_wren_w(user_w_config_wren), .user_w_config_data_w(user_w_config_data),
.user_w_config_full_w(user_w_config_full), .M_AXI_ACP_AWBURST_w(M_AXI_ACP_AWBURST),
.user_w_config_open_w(user_w_config_open), .M_AXI_ACP_AWPROT_w(M_AXI_ACP_AWPROT),
.M_AXI_ACP_AWCACHE_w(M_AXI_ACP_AWCACHE), .M_AXI_ACP_WREADY_w(M_AXI_ACP_WREADY),
.M_AXI_ACP_WVALID_w(M_AXI_ACP_WVALID), .user_config_addr_w(user_config_addr),
.user_config_addr_update_w(user_config_addr_update),
.M_AXI_ACP_WDATA_w(M_AXI_ACP_WDATA), .user_r_audio_rden_w(user_r_audio_rden),
.user_r_audio_data_w(user_r_audio_data), .user_r_audio_empty_w(user_r_audio_empty),
.user_r_audio_eof_w(user_r_audio_eof), .M_AXI_ACP_WVALID_w(M_AXI_ACP_WVALID),
.user_r_audio_open_w(user_r_audio_open), .M_AXI_ACP_WDATA_w(M_AXI_ACP_WDATA),
.M_AXI_ACP_WSTRB_w(M_AXI_ACP_WSTRB), .M_AXI_ACP_WLAST_w(M_AXI_ACP_WLAST),
.M_AXI_ACP_WSTRB_w(M_AXI_ACP_WSTRB), .user_r_audio_eof_w(user_r_audio_eof),
.user_r_audio_open_w(user_r_audio_open), .M_AXI_ACP_WLAST_w(M_AXI_ACP_WLAST),
.M_AXI_ACP_BREADY_w(M_AXI_ACP_BREADY), .M_AXI_ACP_BVALID_w(M_AXI_ACP_BVALID),
.M_AXI_ACP_BRESP_w(M_AXI_ACP_BRESP), .user_w_audio_wren_w(user_w_audio_wren),
.user_w_audio_data_w(user_w_audio_data), .user_w_audio_full_w(user_w_audio_full),
.host_interrupt_w(host_interrupt), .user_w_audio_open_w(user_w_audio_open),
.user_r_read_32_rden_w(user_r_read_32_rden), .user_r_read_32_data_w(user_r_read_32_data),
.user_r_read_32_empty_w(user_r_read_32_empty),
.user_r_read_32_eof_w(user_r_read_32_eof), .user_r_read_32_open_w(user_r_read_32_open),
.user_w_write_32_wren_w(user_w_write_32_wren),
.user_w_write_32_data_w(user_w_write_32_data),
.user_w_write_32_full_w(user_w_write_32_full),
.user_w_write_32_open_w(user_w_write_32_open),
.user_r_read_8_rden_w(user_r_read_8_rden), .user_r_read_8_data_w(user_r_read_8_data),
.user_r_read_8_empty_w(user_r_read_8_empty), .user_r_read_8_eof_w(user_r_read_8_eof),
.user_r_read_8_open_w(user_r_read_8_open), .user_w_write_8_wren_w(user_w_write_8_wren),
.user_w_write_8_data_w(user_w_write_8_data), .user_w_write_8_full_w(user_w_write_8_full),
.user_w_write_8_open_w(user_w_write_8_open));
.M_AXI_ACP_BRESP_w(M_AXI_ACP_BRESP), .host_interrupt_w(host_interrupt),
.user_w_audio_wren_w(user_w_audio_wren), .user_w_audio_data_w(user_w_audio_data),
.user_w_audio_full_w(user_w_audio_full), .user_w_audio_open_w(user_w_audio_open),
.user_r_smb_rden_w(user_r_smb_rden), .user_r_smb_data_w(user_r_smb_data),
.user_r_smb_empty_w(user_r_smb_empty), .user_r_smb_eof_w(user_r_smb_eof),
.user_r_smb_open_w(user_r_smb_open), .user_w_smb_wren_w(user_w_smb_wren),
.user_w_smb_data_w(user_w_smb_data), .user_w_smb_full_w(user_w_smb_full),
.user_w_smb_open_w(user_w_smb_open));
endmodule

42
xillinux-syn/vhdl/src/xillybus_core.v
View File

@ -23,23 +23,15 @@ module xillybus_core
input [31:0] user_r_audio_data_w,
input user_r_audio_empty_w,
input user_r_audio_eof_w,
input [7:0] user_r_mem_8_data_w,
input user_r_mem_8_empty_w,
input user_r_mem_8_eof_w,
input [31:0] user_r_read_32_data_w,
input user_r_read_32_empty_w,
input user_r_read_32_eof_w,
input [7:0] user_r_read_8_data_w,
input user_r_read_8_empty_w,
input user_r_read_8_eof_w,
input [31:0] user_r_debug_data_w,
input user_r_debug_empty_w,
input user_r_debug_eof_w,
input [7:0] user_r_smb_data_w,
input user_r_smb_empty_w,
input user_r_smb_eof_w,
input user_w_audio_full_w,
input user_w_mem_8_full_w,
input user_w_config_full_w,
input user_w_smb_full_w,
input user_w_write_32_full_w,
input user_w_write_8_full_w,
output [3:0] GPIO_LED_w,
output [31:0] M_AXI_ACP_ARADDR_w,
output [1:0] M_AXI_ACP_ARBURST_w,
@ -71,32 +63,22 @@ module xillybus_core
output S_AXI_WREADY_w,
output host_interrupt_w,
output quiesce_w,
output user_mem_8_addr_update_w,
output [4:0] user_mem_8_addr_w,
output user_config_addr_update_w,
output [15:0] user_config_addr_w,
output user_r_audio_open_w,
output user_r_audio_rden_w,
output user_r_mem_8_open_w,
output user_r_mem_8_rden_w,
output user_r_read_32_open_w,
output user_r_read_32_rden_w,
output user_r_read_8_open_w,
output user_r_read_8_rden_w,
output user_r_debug_open_w,
output user_r_debug_rden_w,
output user_r_smb_open_w,
output user_r_smb_rden_w,
output [31:0] user_w_audio_data_w,
output user_w_audio_open_w,
output user_w_audio_wren_w,
output [7:0] user_w_mem_8_data_w,
output user_w_mem_8_open_w,
output user_w_mem_8_wren_w,
output [31:0] user_w_config_data_w,
output user_w_config_open_w,
output user_w_config_wren_w,
output [7:0] user_w_smb_data_w,
output user_w_smb_open_w,
output user_w_smb_wren_w,
output [31:0] user_w_write_32_data_w,
output user_w_write_32_open_w,
output user_w_write_32_wren_w,
output [7:0] user_w_write_8_data_w,
output user_w_write_8_open_w,
output user_w_write_8_wren_w
output user_w_smb_wren_w
);
endmodule

405
xillinux-syn/vhdl/src/xillydemo.vhd
View File

@ -3,34 +3,46 @@ use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.typedef_package.all;
entity xillydemo is
port (
-- For Vivado, delete the port declarations for PS_CLK, PS_PORB and
-- PS_SRSTB, and uncomment their declarations as signals further below.
PS_CLK : IN std_logic;
PS_PORB : IN std_logic;
PS_SRSTB : IN std_logic;
clk_100 : IN std_logic;
otg_oc : IN std_logic;
PS_GPIO : INOUT std_logic_vector(55 DOWNTO 0);
GPIO_LED : OUT std_logic_vector(3 DOWNTO 0);
vga4_blue : OUT std_logic_vector(3 DOWNTO 0);
vga4_green : OUT std_logic_vector(3 DOWNTO 0);
vga4_red : OUT std_logic_vector(3 DOWNTO 0);
vga_hsync : OUT std_logic;
vga_vsync : OUT std_logic;
audio_mclk : OUT std_logic;
audio_dac : OUT std_logic;
audio_adc : IN std_logic;
audio_bclk : IN std_logic;
audio_lrclk : IN std_logic;
smb_sclk : OUT std_logic;
smb_sdata : INOUT std_logic;
smbus_addr : OUT std_logic_vector(1 DOWNTO 0));
end xillydemo;
clk_100 : IN std_logic;
otg_oc : IN std_logic;
PS_GPIO : INOUT std_logic_vector(55 DOWNTO 0);
GPIO_LED : OUT std_logic_vector(3 DOWNTO 0);
vga4_blue : OUT std_logic_vector(3 DOWNTO 0);
vga4_green : OUT std_logic_vector(3 DOWNTO 0);
vga4_red : OUT std_logic_vector(3 DOWNTO 0);
vga_hsync : OUT std_logic;
vga_vsync : OUT std_logic;
audio_mclk : OUT std_logic;
audio_dac : OUT std_logic;
audio_adc : IN std_logic;
audio_bclk : IN std_logic;
audio_lrclk : IN std_logic;
smb_sclk : OUT std_logic;
smb_sdata : INOUT std_logic;
smbus_addr : OUT std_logic_vector(1 DOWNTO 0);
--FEEDBACK_TOP
clk_ext : in std_logic;
areset : in std_logic;
areset_debug : in std_logic;
async_pulse : in std_logic;
astandby : in std_logic;
adc_data_in1 : in std_logic;
adc_data_in2 : in std_logic;
adc_cs_n : out std_logic;
adc_sclk : out std_logic;
dac_data_out : out std_logic;
dac_cs_n : out std_logic;
dac_ldac : out std_logic;
dac_sclk : out std_logic
);
end xillydemo;
architecture sample_arch of xillydemo is
component xillybus
port (
PS_CLK : IN std_logic;
@ -65,35 +77,6 @@ architecture sample_arch of xillydemo is
vga4_red : OUT std_logic_vector(3 DOWNTO 0);
vga_hsync : OUT std_logic;
vga_vsync : OUT std_logic;
user_r_mem_8_rden : OUT std_logic;
user_r_mem_8_empty : IN std_logic;
user_r_mem_8_data : IN std_logic_vector(7 DOWNTO 0);
user_r_mem_8_eof : IN std_logic;
user_r_mem_8_open : OUT std_logic;
user_w_mem_8_wren : OUT std_logic;
user_w_mem_8_full : IN std_logic;
user_w_mem_8_data : OUT std_logic_vector(7 DOWNTO 0);
user_w_mem_8_open : OUT std_logic;
user_mem_8_addr : OUT std_logic_vector(4 DOWNTO 0);
user_mem_8_addr_update : OUT std_logic;
user_r_read_32_rden : OUT std_logic;
user_r_read_32_empty : IN std_logic;
user_r_read_32_data : IN std_logic_vector(31 DOWNTO 0);
user_r_read_32_eof : IN std_logic;
user_r_read_32_open : OUT std_logic;
user_r_read_8_rden : OUT std_logic;
user_r_read_8_empty : IN std_logic;
user_r_read_8_data : IN std_logic_vector(7 DOWNTO 0);
user_r_read_8_eof : IN std_logic;
user_r_read_8_open : OUT std_logic;
user_w_write_32_wren : OUT std_logic;
user_w_write_32_full : IN std_logic;
user_w_write_32_data : OUT std_logic_vector(31 DOWNTO 0);
user_w_write_32_open : OUT std_logic;
user_w_write_8_wren : OUT std_logic;
user_w_write_8_full : IN std_logic;
user_w_write_8_data : OUT std_logic_vector(7 DOWNTO 0);
user_w_write_8_open : OUT std_logic;
user_r_audio_rden : OUT std_logic;
user_r_audio_empty : IN std_logic;
user_r_audio_data : IN std_logic_vector(31 DOWNTO 0);
@ -103,6 +86,17 @@ architecture sample_arch of xillydemo is
user_w_audio_full : IN std_logic;
user_w_audio_data : OUT std_logic_vector(31 DOWNTO 0);
user_w_audio_open : OUT std_logic;
user_w_config_wren : OUT std_logic;
user_w_config_full : IN std_logic;
user_w_config_data : OUT std_logic_vector(31 DOWNTO 0);
user_w_config_open : OUT std_logic;
user_config_addr : OUT std_logic_vector(15 DOWNTO 0);
user_config_addr_update : OUT std_logic;
user_r_debug_rden : OUT std_logic;
user_r_debug_empty : IN std_logic;
user_r_debug_data : IN std_logic_vector(31 DOWNTO 0);
user_r_debug_eof : IN std_logic;
user_r_debug_open : OUT std_logic;
user_r_smb_rden : OUT std_logic;
user_r_smb_empty : IN std_logic;
user_r_smb_data : IN std_logic_vector(7 DOWNTO 0);
@ -114,38 +108,14 @@ architecture sample_arch of xillydemo is
user_w_smb_open : OUT std_logic;
user_clk : OUT std_logic;
user_wren : OUT std_logic;
user_wstrb : OUT std_logic_vector(3 DOWNTO 0);
user_rden : OUT std_logic;
user_wstrb : OUT std_logic_vector(3 DOWNTO 0);
user_addr : OUT std_logic_vector(31 DOWNTO 0);
user_rd_data : IN std_logic_vector(31 DOWNTO 0);
user_wr_data : OUT std_logic_vector(31 DOWNTO 0);
user_addr : OUT std_logic_vector(31 DOWNTO 0);
user_irq : IN std_logic);
end component;
component fifo_8x2048
port (
clk: IN std_logic;
srst: IN std_logic;
din: IN std_logic_VECTOR(7 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
full: OUT std_logic;
empty: OUT std_logic);
end component;
component fifo_32x512
port (
clk: IN std_logic;
srst: IN std_logic;
din: IN std_logic_VECTOR(31 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(31 downto 0);
full: OUT std_logic;
empty: OUT std_logic);
end component;
component i2s_audio
port (
bus_clk : IN std_logic;
@ -185,56 +155,37 @@ architecture sample_arch of xillydemo is
user_w_smb_open : IN std_logic);
end component;
-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of fifo_32x512: component is true;
attribute syn_black_box of fifo_8x2048: component is true;
type demo_mem is array(0 TO 31) of std_logic_vector(7 DOWNTO 0);
signal demoarray : demo_mem;
signal litearray0 : demo_mem;
signal litearray1 : demo_mem;
signal litearray2 : demo_mem;
signal litearray3 : demo_mem;
component feedback_top is
port (
--XILLYBUS
xillybus_clk : in std_logic;
fifo_rd_data : out std_logic_vector(DEBUG_FIFO_DATA_WIDTH-1 downto 0);
fifo_ren : in std_logic;
fifo_empty : out std_logic;
mem_addr : in std_logic_vector(CONFIG_MEM_ADDR_WIDTH downto 0);
mem_wr_data : in std_logic_vector(CONFIG_MEM_DATA_WIDTH-1 downto 0);
mem_wen : in std_logic;
mem_full : out std_logic;
--FPGA
clk_in : in std_logic;
areset : in std_logic;
areset_debug : in std_logic;
async_pulse : in std_logic;
astandby : in std_logic;
adc_data_in1 : in std_logic;
adc_data_in2 : in std_logic;
adc_cs_n : out std_logic;
adc_sclk : out std_logic;
dac_data_out : out std_logic;
dac_cs_n : out std_logic;
dac_ldac : out std_logic;
dac_sclk : out std_logic
);
end component;
signal bus_clk : std_logic;
signal quiesce : std_logic;
signal reset_8 : std_logic;
signal reset_32 : std_logic;
signal ram_addr : integer range 0 to 31;
signal lite_addr : integer range 0 to 31;
signal user_r_mem_8_rden : std_logic;
signal user_r_mem_8_empty : std_logic;
signal user_r_mem_8_data : std_logic_vector(7 DOWNTO 0);
signal user_r_mem_8_eof : std_logic;
signal user_r_mem_8_open : std_logic;
signal user_w_mem_8_wren : std_logic;
signal user_w_mem_8_full : std_logic;
signal user_w_mem_8_data : std_logic_vector(7 DOWNTO 0);
signal user_w_mem_8_open : std_logic;
signal user_mem_8_addr : std_logic_vector(4 DOWNTO 0);
signal user_mem_8_addr_update : std_logic;
signal user_r_read_32_rden : std_logic;
signal user_r_read_32_empty : std_logic;
signal user_r_read_32_data : std_logic_vector(31 DOWNTO 0);
signal user_r_read_32_eof : std_logic;
signal user_r_read_32_open : std_logic;
signal user_r_read_8_rden : std_logic;
signal user_r_read_8_empty : std_logic;
signal user_r_read_8_data : std_logic_vector(7 DOWNTO 0);
signal user_r_read_8_eof : std_logic;
signal user_r_read_8_open : std_logic;
signal user_w_write_32_wren : std_logic;
signal user_w_write_32_full : std_logic;
signal user_w_write_32_data : std_logic_vector(31 DOWNTO 0);
signal user_w_write_32_open : std_logic;
signal user_w_write_8_wren : std_logic;
signal user_w_write_8_full : std_logic;
signal user_w_write_8_data : std_logic_vector(7 DOWNTO 0);
signal user_w_write_8_open : std_logic;
signal user_r_audio_rden : std_logic;
signal user_r_audio_empty : std_logic;
signal user_r_audio_data : std_logic_vector(31 DOWNTO 0);
@ -253,14 +204,6 @@ architecture sample_arch of xillydemo is
signal user_w_smb_full : std_logic;
signal user_w_smb_data : std_logic_vector(7 DOWNTO 0);
signal user_w_smb_open : std_logic;
signal user_clk : std_logic;
signal user_wren : std_logic;
signal user_wstrb : std_logic_vector(3 DOWNTO 0);
signal user_rden : std_logic;
signal user_rd_data : std_logic_vector(31 DOWNTO 0);
signal user_wr_data : std_logic_vector(31 DOWNTO 0);
signal user_addr : std_logic_vector(31 DOWNTO 0);
signal user_irq : std_logic;
-- Note that none of the ARM processor's direct connections to pads is
-- defined as I/O on this module. Normally, they should be connected
@ -270,9 +213,9 @@ architecture sample_arch of xillydemo is
-- implementation, but has no practical significance, as these pads are
-- completely unrelated to the FPGA bitstream.
-- signal PS_CLK : std_logic;
-- signal PS_PORB : std_logic;
-- signal PS_SRSTB : std_logic;
signal PS_CLK : std_logic;
signal PS_PORB : std_logic;
signal PS_SRSTB : std_logic;
signal DDR_Addr : std_logic_vector(14 DOWNTO 0);
signal DDR_BankAddr : std_logic_vector(2 DOWNTO 0);
signal DDR_CAS_n : std_logic;
@ -292,64 +235,43 @@ architecture sample_arch of xillydemo is
signal MIO : std_logic_vector(53 DOWNTO 0);
signal DDR_WEB : std_logic;
signal user_r_debug_data : std_logic_vector(DEBUG_FIFO_DATA_WIDTH-1 downto 0) := (others => '0');
signal user_r_debug_rden, user_r_debug_empty : std_logic := '0';
signal user_config_addr : std_logic_vector(CONFIG_MEM_ADDR_WIDTH downto 0) := (others => '0');
signal user_w_config_data : std_logic_vector(CONFIG_MEM_DATA_WIDTH-1 downto 0) := (others => '0');
signal user_w_config_wren, user_w_config_full : std_logic := '0';
begin
xillybus_ins : xillybus
port map (
-- Ports related to /dev/xillybus_mem_8
-- FPGA to CPU signals:
user_r_mem_8_rden => user_r_mem_8_rden,
user_r_mem_8_empty => user_r_mem_8_empty,
user_r_mem_8_data => user_r_mem_8_data,
user_r_mem_8_eof => user_r_mem_8_eof,
user_r_mem_8_open => user_r_mem_8_open,
-- Ports related to /dev/xillybus_config
-- CPU to FPGA signals:
user_w_mem_8_wren => user_w_mem_8_wren,
user_w_mem_8_full => user_w_mem_8_full,
user_w_mem_8_data => user_w_mem_8_data,
user_w_mem_8_open => user_w_mem_8_open,
user_w_config_wren => user_w_config_wren,
user_w_config_full => user_w_config_full,
user_w_config_data => user_w_config_data,
user_w_config_open => open,
-- Address signals:
user_mem_8_addr => user_mem_8_addr,
user_mem_8_addr_update => user_mem_8_addr_update,
user_config_addr => user_config_addr,
user_config_addr_update => open,
-- Ports related to /dev/xillybus_read_32
-- Ports related to /dev/xillybus_debug
-- FPGA to CPU signals:
user_r_read_32_rden => user_r_read_32_rden,
user_r_read_32_empty => user_r_read_32_empty,
user_r_read_32_data => user_r_read_32_data,
user_r_read_32_eof => user_r_read_32_eof,
user_r_read_32_open => user_r_read_32_open,
-- Ports related to /dev/xillybus_read_8
-- FPGA to CPU signals:
user_r_read_8_rden => user_r_read_8_rden,
user_r_read_8_empty => user_r_read_8_empty,
user_r_read_8_data => user_r_read_8_data,
user_r_read_8_eof => user_r_read_8_eof,
user_r_read_8_open => user_r_read_8_open,
-- Ports related to /dev/xillybus_write_32
-- CPU to FPGA signals:
user_w_write_32_wren => user_w_write_32_wren,
user_w_write_32_full => user_w_write_32_full,
user_w_write_32_data => user_w_write_32_data,
user_w_write_32_open => user_w_write_32_open,
-- Ports related to /dev/xillybus_write_8
-- CPU to FPGA signals:
user_w_write_8_wren => user_w_write_8_wren,
user_w_write_8_full => user_w_write_8_full,
user_w_write_8_data => user_w_write_8_data,
user_w_write_8_open => user_w_write_8_open,
user_r_debug_rden => user_r_debug_rden,
user_r_debug_empty => user_r_debug_empty,
user_r_debug_data => user_r_debug_data,
user_r_debug_eof => '0',
user_r_debug_open => open,
-- Ports related to Xillybus Lite
user_clk => user_clk,
user_wren => user_wren,
user_wstrb => user_wstrb,
user_rden => user_rden,
user_rd_data => user_rd_data,
user_wr_data => user_wr_data,
user_addr => user_addr,
user_irq => user_irq,
-- UNUSED
user_clk => open,
user_wren => open,
user_wstrb => open,
user_rden => open,
user_rd_data => (others => '0'),
user_wr_data => open,
user_addr => open,
user_irq => '0',
-- Ports related to /dev/xillybus_audio
-- FPGA to CPU signals:
@ -412,93 +334,32 @@ begin
vga_vsync => vga_vsync
);
-- Xillybus Lite
user_irq <= '0'; -- No interrupts for now
lite_addr <= conv_integer(user_addr(6 DOWNTO 2));
process (user_clk)
begin
if (user_clk'event and user_clk = '1') then
if (user_wstrb(0) = '1') then
litearray0(lite_addr) <= user_wr_data(7 DOWNTO 0);
end if;
if (user_wstrb(1) = '1') then
litearray1(lite_addr) <= user_wr_data(15 DOWNTO 8);
end if;
if (user_wstrb(2) = '1') then
litearray2(lite_addr) <= user_wr_data(23 DOWNTO 16);
end if;
if (user_wstrb(3) = '1') then
litearray3(lite_addr) <= user_wr_data(31 DOWNTO 24);
end if;
if (user_rden = '1') then
user_rd_data <= litearray3(lite_addr) & litearray2(lite_addr) &
litearray1(lite_addr) & litearray0(lite_addr);
end if;
end if;
end process;
-- A simple inferred RAM
ram_addr <= conv_integer(user_mem_8_addr);
process (bus_clk)
begin
if (bus_clk'event and bus_clk = '1') then
if (user_w_mem_8_wren = '1') then
demoarray(ram_addr) <= user_w_mem_8_data;
end if;
if (user_r_mem_8_rden = '1') then
user_r_mem_8_data <= demoarray(ram_addr);
end if;
end if;
end process;
user_r_mem_8_empty <= '0';
user_r_mem_8_eof <= '0';
user_w_mem_8_full <= '0';
-- 32-bit loopback
fifo_32 : fifo_32x512
port map(
clk => bus_clk,
srst => reset_32,
din => user_w_write_32_data,
wr_en => user_w_write_32_wren,
rd_en => user_r_read_32_rden,
dout => user_r_read_32_data,
full => user_w_write_32_full,
empty => user_r_read_32_empty
);
reset_32 <= not (user_w_write_32_open or user_r_read_32_open);
user_r_read_32_eof <= '0';
-- 8-bit loopback
fifo_8 : fifo_8x2048
port map(
clk => bus_clk,
srst => reset_8,
din => user_w_write_8_data,
wr_en => user_w_write_8_wren,
rd_en => user_r_read_8_rden,
dout => user_r_read_8_data,
full => user_w_write_8_full,
empty => user_r_read_8_empty
);
reset_8 <= not (user_w_write_8_open or user_r_read_8_open);
user_r_read_8_eof <= '0';
feedback_inst : feedback_top
port map (
--XILLYBUS
xillybus_clk => bus_clk,
fifo_rd_data => user_r_debug_data,
fifo_ren => user_r_debug_rden,
fifo_empty => user_r_debug_empty,
mem_addr => user_config_addr,
mem_wr_data => user_w_config_data,
mem_wen => user_w_config_wren,
mem_full => user_w_config_full,
--FPGA
clk_in => clk_ext,
areset => areset,
areset_debug => areset_debug,
async_pulse => async_pulse,
astandby => astandby,
adc_data_in1 => adc_data_in1,
adc_data_in2 => adc_data_in2,
adc_cs_n => adc_cs_n,
adc_sclk => adc_sclk,
dac_data_out => dac_data_out,
dac_cs_n => dac_cs_n,
dac_ldac => dac_ldac,
dac_sclk => dac_sclk
);
audio_ins : i2s_audio
port map(

205
xillinux-syn/vivado/xillydemo.xpr
View File

@ -41,13 +41,13 @@
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="0"/>
<Option Name="WTModelSimExportSim" Val="0"/>
<Option Name="WTQuestaExportSim" Val="0"/>
<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="0"/>
<Option Name="WTRivieraExportSim" Val="0"/>
<Option Name="WTActivehdlExportSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="2"/>
<Option Name="WTModelSimExportSim" Val="2"/>
<Option Name="WTQuestaExportSim" Val="2"/>
<Option Name="WTIesExportSim" Val="2"/>
<Option Name="WTVcsExportSim" Val="2"/>
<Option Name="WTRivieraExportSim" Val="2"/>
<Option Name="WTActivehdlExportSim" Val="2"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
@ -63,7 +63,7 @@
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../vhdl/src/xillydemo.vhd">
<FileInfo>
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
@ -122,6 +122,116 @@
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/mult.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/single_port_ram.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/clockgen.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/pmod_da3_ctrl.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/addsub.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/typedef_package.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/scaler.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/feedback_top.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/feedback_controller.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/synchronizer.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/delay_line.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/async_fifo.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/dual_port_ram.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/feedback_loop.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/pmod_ad1_ctrl.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/xillybus_link.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../vivado-essentials/fifo_32x512/fifo_32x512.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../vivado-essentials/fifo_8x2048/fifo_8x2048.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="xillydemo"/>
@ -171,32 +281,6 @@
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="fifo_8x2048" Type="BlockSrcs" RelSrcDir="$PSRCDIR/fifo_8x2048">
<File Path="$PPRDIR/../vivado-essentials/fifo_8x2048/fifo_8x2048.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="fifo_8x2048"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="fifo_32x512" Type="BlockSrcs" RelSrcDir="$PSRCDIR/fifo_32x512">
<File Path="$PPRDIR/../vivado-essentials/fifo_32x512/fifo_32x512.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="fifo_32x512"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
@ -235,25 +319,7 @@
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="fifo_8x2048_synth_1" Type="Ft3:Synth" SrcSet="fifo_8x2048" Part="xc7z020clg484-1" ConstrsSet="fifo_8x2048" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/fifo_8x2048_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="fifo_32x512_synth_1" Type="Ft3:Synth" SrcSet="fifo_32x512" Part="xc7z020clg484-1" ConstrsSet="fifo_32x512" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/fifo_32x512_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
<Step Id="init_design"/>
@ -266,7 +332,6 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
@ -286,38 +351,6 @@
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="fifo_8x2048_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg484-1" ConstrsSet="fifo_8x2048" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="fifo_8x2048_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="fifo_32x512_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg484-1" ConstrsSet="fifo_32x512" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="fifo_32x512_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
</Runs>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>