greek64/labor-mst
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Labor Microsystemtechnik
10 Commits 2 Branches 3 Tags 1.2 GiB
VHDL 58.6%
Verilog 23.4%
Tcl 6.4%
Coq 5.7%
Stata 2.8%
Other 3.1%
bb07d0a072
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Greek bb07d0a072 * Modify xillinux vivado project 
- Add custom xillybus IP core to vivado design
	- Add feedback_top
TODO: Remove PS_GPIO and connect custom pins
2020-04-26 17:36:25 +02:00
doc * Update docs 2020-04-26 14:34:34 +02:00
modelsim * Added Zynq 7 documentation 2020-04-01 14:12:04 +02:00
src * Update docs 2020-04-26 14:34:34 +02:00
syn * Update docs 2020-04-26 14:34:34 +02:00
xillinux-syn * Modify xillinux vivado project 2020-04-26 17:36:25 +02:00
.gitattributes * Initial Commit 2020-03-12 15:38:06 +01:00
.gitignore * Update doc 2020-04-26 00:34:08 +02:00