greek64/labor-mst
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17 Commits 2 Branches 3 Tags 1.2 GiB
89182e8060
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4 Commits

Author SHA1 Message Date
Greek
89182e8060 * Route sclk for ADC/DAC through controller entity itself 
* Remove ADC/DAC input/outputs constraints
* Fix PMOD-AS1 Controller
	- Invert SCLK
 2020-04-29 14:01:01 +02:00
Greek
4fc3cfb9a3 * Update docs 
- Download correct 7-series reference
* Add design top entity
* Add synchronizer
* Fix syntax, synth errors
 2020-04-26 14:34:34 +02:00
Greek
779cd73e8d * Moved config/constants to central package 
* Made cap of addsub selectable via signal
* Added debug reporting
    - MAX ADC Input 1
    - MAX ADC Input 2
    - MAX Scaler output
    - MAX DAC Output
* Added Async FIFO
* Added Simple Dual Port RAM
* Added Feedback Controller
* Added Xillybus Link
* Moved testbenches to seperate directory
 2020-04-26 11:35:46 +02:00
Greek
7392d9f72f * Add library/macro relevant documentation 
* Implemented closed feedback loop
	- Scaler
	- Dealy Line
	- Add Sub
 2020-04-03 17:50:25 +02:00