greek64/labor-mst
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  • 365e95d3a0 Update 'Readme.md' master v2.0.0 dev John Ring 2021-03-28 15:24:00 +0200
  • 71a6ddcf3b Add BIAS Configuration Greek 2021-03-28 14:11:15 +0200
  • 8658ac24db Update SW Greek 2021-03-28 13:36:44 +0200
  • 2f3e03827a Update Diagrams Greek 2021-03-28 13:26:22 +0200
  • e6b05276d8 Major Rewrite of feedback_loop Greek 2021-03-28 12:32:56 +0200
  • 9d6838aca3 Fix Overflow/Underflow and Delay Line Greek 2021-03-26 23:56:28 +0100
  • b1f3a5c0bc Fix gen_sine.sh Greek64 2021-03-25 13:06:30 +0100
  • 336a393655 Add pre-generated sine arrays Greek64 2021-03-25 11:58:07 +0100
  • 19aadb159e Add gen_sine.sh Greek64 2021-03-25 11:22:17 +0100
  • 3f111508c1 Day 2 Labor Fixes labor-version Greek64 2021-03-24 10:52:36 +0100
  • b6357a993e Fix Scaling Offset Greek 2021-03-23 02:16:23 +0100
  • abe34fd0fc Day 1 Labor Fixes Greek64 2021-03-22 18:17:08 +0100
  • ad89405df7 Update README Greek 2021-03-22 00:21:32 +0100
  • c638cb7191 * Update diagram (No transparency) * Fix Markdown table Greek 2020-04-29 23:53:49 +0200
  • 922c7cdb83 * Add Project Description and Documentation (Readme.md) * Add diagram * Modify counters of PMOD-AD1 and PMOD-DA3 controllers to use less bits * Increase factor width to 5 bits - Highest bit is truncated * Add download directory to git repo Greek 2020-04-29 20:59:35 +0200
  • 29036ded6f * Fix scaler - Add generic to select between signed and unsigned Greek 2020-04-29 17:34:16 +0200
  • 89182e8060 * Route sclk for ADC/DAC through controller entity itself * Remove ADC/DAC input/outputs constraints * Fix PMOD-AS1 Controller - Invert SCLK Greek 2020-04-29 14:01:01 +0200
  • 131a9b3a6e * Modify PMOD-AS1 testbench * Add reference PMOD AD1 controller - Including testbench Greek 2020-04-29 13:28:41 +0200
  • ae928c116b * Fix xillybus-FPGA data ordering * Add file explaining custom mapping Greek 2020-04-28 15:12:31 +0200
  • cd49506685 * Added C program to read debug info Greek64 2020-04-28 13:31:08 +0200
  • c60bcd97f6 * Add C Program to write configuration Greek64 2020-04-28 12:18:08 +0200
  • a5c68d1fea * Add documentation - Zedboard Rev.D Errata * Add debug leds to top entity * Pin mapping Greek 2020-04-27 13:41:10 +0200
  • 11532daee2 * Modify xillinux vivado project - Remove PS-GPIO Greek 2020-04-26 17:53:15 +0200
  • bb07d0a072 * Modify xillinux vivado project - Add custom xillybus IP core to vivado design - Add feedback_top TODO: Remove PS_GPIO and connect custom pins Greek 2020-04-26 17:36:25 +0200
  • 4fc3cfb9a3 * Update docs - Download correct 7-series reference * Add design top entity * Add synchronizer * Fix syntax, synth errors Greek 2020-04-26 14:34:34 +0200
  • 9818d0d27a * Added Xillybus demo project Greek 2020-04-26 11:42:06 +0200
  • 779cd73e8d * Moved config/constants to central package * Made cap of addsub selectable via signal * Added debug reporting - MAX ADC Input 1 - MAX ADC Input 2 - MAX Scaler output - MAX DAC Output * Added Async FIFO * Added Simple Dual Port RAM * Added Feedback Controller * Added Xillybus Link * Moved testbenches to seperate directory Greek 2020-04-26 11:35:46 +0200
  • aa53591056 * Update doc - Add Xillybus doc - Add additional 7-series doc Greek 2020-04-26 00:34:08 +0200
  • 7392d9f72f * Add library/macro relevant documentation * Implemented closed feedback loop - Scaler - Dealy Line - Add Sub Greek 2020-04-03 17:50:25 +0200
  • e1ffa99874 * Added clock generator for 20Mhz sclk * Added top entiry * Added constraints file open_loop-v1 Greek 2020-04-01 14:14:14 +0200
  • a28aab25fa * Added Zynq 7 documentation * Updated sync processes for async reset * Implemented simple open loop design - Added testbench and .do file Greek 2020-04-01 14:12:04 +0200
  • 2beb7f4b4d * .gitignore update * Added implementation for PMOD-AD1 Controller including testbench * Added implementation for PMOD-DA3 Controller including testbench Greek 2020-03-12 20:20:35 +0100
  • d82505b819 * Initial Commit Greek 2020-03-12 15:38:06 +0100