Commit Graph

4 Commits

Author SHA1 Message Date
Greek
e6b05276d8 Major Rewrite of feedback_loop
Another scaling factor was added and both input signals can now be
independenly scaled. In Single Input Mode only Input 1 is passed to the
output (negated if configured as negative feddback). In double input
mode Input 2 is added/subtracted from Input 1 (in1 +/- in2). The delay
line is only applied to Input 2.
Addsub was removed from the design (all Additions and Subtractions are
directly implemented in VHDL code).
Config signals were latched to follow the data flow path and prevent
glitches on certain events.
Vivado Project updated.
Single Package containing all needed pre-calculated sine arrays.
General Code Cleanup.
2021-03-28 12:32:56 +02:00
Greek
a5c68d1fea * Add documentation
- Zedboard Rev.D Errata
* Add debug leds to top entity
* Pin mapping
2020-04-27 13:41:10 +02:00
Greek
bb07d0a072 * Modify xillinux vivado project
- Add custom xillybus IP core to vivado design
	- Add feedback_top
TODO: Remove PS_GPIO and connect custom pins
2020-04-26 17:36:25 +02:00
Greek
9818d0d27a * Added Xillybus demo project 2020-04-26 11:42:06 +02:00