greek64/labor-mst
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Labor Microsystemtechnik
7 Commits 2 Branches 3 Tags 1.2 GiB
VHDL 58.6%
Verilog 23.4%
Tcl 6.4%
Coq 5.7%
Stata 2.8%
Other 3.1%
779cd73e8d
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Greek 779cd73e8d * Moved config/constants to central package 
* Made cap of addsub selectable via signal
* Added debug reporting
    - MAX ADC Input 1
    - MAX ADC Input 2
    - MAX Scaler output
    - MAX DAC Output
* Added Async FIFO
* Added Simple Dual Port RAM
* Added Feedback Controller
* Added Xillybus Link
* Moved testbenches to seperate directory
2020-04-26 11:35:46 +02:00
doc * Update doc 2020-04-26 00:34:08 +02:00
modelsim * Added Zynq 7 documentation 2020-04-01 14:12:04 +02:00
src * Moved config/constants to central package 2020-04-26 11:35:46 +02:00
syn * Add library/macro relevant documentation 2020-04-03 17:50:25 +02:00
.gitattributes * Initial Commit 2020-03-12 15:38:06 +01:00
.gitignore * Update doc 2020-04-26 00:34:08 +02:00