Greek
779cd73e8d
* Moved config/constants to central package
...
* Made cap of addsub selectable via signal
* Added debug reporting
- MAX ADC Input 1
- MAX ADC Input 2
- MAX Scaler output
- MAX DAC Output
* Added Async FIFO
* Added Simple Dual Port RAM
* Added Feedback Controller
* Added Xillybus Link
* Moved testbenches to seperate directory
2020-04-26 11:35:46 +02:00
Greek
aa53591056
* Update doc
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- Add Xillybus doc
- Add additional 7-series doc
2020-04-26 00:34:08 +02:00
Greek
7392d9f72f
* Add library/macro relevant documentation
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* Implemented closed feedback loop
- Scaler
- Dealy Line
- Add Sub
2020-04-03 17:50:25 +02:00
Greek
e1ffa99874
* Added clock generator for 20Mhz sclk
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* Added top entiry
* Added constraints file
2020-04-01 14:14:14 +02:00
Greek
a28aab25fa
* Added Zynq 7 documentation
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* Updated sync processes for async reset
* Implemented simple open loop design
- Added testbench and .do file
2020-04-01 14:12:04 +02:00
Greek
2beb7f4b4d
* .gitignore update
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* Added implementation for PMOD-AD1 Controller including testbench
* Added implementation for PMOD-DA3 Controller including testbench
2020-03-12 20:20:35 +01:00
Greek
d82505b819
* Initial Commit
2020-03-12 15:38:06 +01:00
