Greek 9818d0d27a * Added Xillybus demo project		2020-04-26 11:42:06 +02:00
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xillyvga.srcs/sources_1/imports/verilog	* Added Xillybus demo project	2020-04-26 11:42:06 +02:00
component.xml	* Added Xillybus demo project	2020-04-26 11:42:06 +02:00