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Greek ae928c116b * Fix xillybus-FPGA data ordering
* Add file explaining custom mapping
2020-04-28 15:12:31 +02:00
doc * Add documentation 2020-04-27 13:41:10 +02:00
modelsim * Added Zynq 7 documentation 2020-04-01 14:12:04 +02:00
src * Fix xillybus-FPGA data ordering 2020-04-28 15:12:31 +02:00
sw * Fix xillybus-FPGA data ordering 2020-04-28 15:12:31 +02:00
syn * Update docs 2020-04-26 14:34:34 +02:00
xillinux-syn * Add documentation 2020-04-27 13:41:10 +02:00
.gitattributes * Initial Commit 2020-03-12 15:38:06 +01:00
.gitignore * Update doc 2020-04-26 00:34:08 +02:00
mapping.txt * Fix xillybus-FPGA data ordering 2020-04-28 15:12:31 +02:00