32 lines
610 B
XML
32 lines
610 B
XML
#Please do not modify this file by hand
|
|
XmpVersion: 14.2
|
|
VerMgmt: 14.2
|
|
IntStyle: default
|
|
Flow: ise
|
|
MHS File: system.mhs
|
|
Architecture: zynq
|
|
Device: xc7z020
|
|
Package: clg484
|
|
SpeedGrade: -1
|
|
UserCmd1:
|
|
UserCmd1Type: 0
|
|
UserCmd2:
|
|
UserCmd2Type: 0
|
|
GenSimTB: 0
|
|
SdkExportBmmBit: 0
|
|
SdkExportDir: SDK/SDK_Export
|
|
InsertNoPads: 1
|
|
WarnForEAArch: 1
|
|
HdlLang: verilog
|
|
SimModel: BEHAVIORAL
|
|
ExternalMemSim: 0
|
|
UcfFile: data/system.ucf
|
|
EnableParTimingError: 1
|
|
ShowLicenseDialog: 1
|
|
LockAddr: xillybus_0,C_BASEADDR
|
|
LockAddr: xillyvga_0,C_BASEADDR
|
|
LockAddr: xillybus_lite_0,C_BASEADDR
|
|
Processor: processing_system7_0
|
|
ElfImp:
|
|
ElfSim:
|