Add test entities to test PL-PS communication

src/Tests/testbench.pro

@@ -8,8 +8,10 @@ analyze test_config2.vhd
 analyze ../rtps_config_package.vhd
 analyze ../rtps_test_package.vhd
 analyze ../single_port_ram.vhd
+analyze ../single_port_ram_Altera.vhd
 analyze single_port_ram_cfg.vhd
 analyze ../FWFT_FIFO.vhd
+analyze ../FWFT_FIFO_Altera.vhd
 analyze FWFT_FIFO_cfg.vhd
 analyze ../mem_ctrl.vhd
 analyze ../rtps_handler.vhd
@@ -36,8 +38,10 @@ analyze test_config3.vhd
 analyze ../rtps_config_package.vhd
 analyze ../rtps_test_package.vhd
 analyze ../single_port_ram.vhd
+analyze ../single_port_ram_Altera.vhd
 analyze single_port_ram_cfg.vhd
 analyze ../FWFT_FIFO.vhd
+analyze ../FWFT_FIFO_Altera.vhd
 analyze FWFT_FIFO_cfg.vhd
 analyze ../mem_ctrl.vhd
 analyze ../rtps_handler.vhd

src/single_port_ram.vhd

@@ -2,8 +2,6 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
-use work.rtps_test_package.all;
-
 entity single_port_ram is
         generic (
             ADDR_WIDTH      : natural := 8;

syn/DE10-Nano/top.qsf

@@ -39,7 +39,7 @@
 
 set_global_assignment -name FAMILY "Cyclone V"
 set_global_assignment -name DEVICE 5CSEBA6U23I7
-set_global_assignment -name TOP_LEVEL_ENTITY dds_reader_syn
+set_global_assignment -name TOP_LEVEL_ENTITY test_top
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:33:09  NOVEMBER 02, 2020"
 set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
@@ -50,6 +50,9 @@ set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name VHDL_FILE ../test_top.vhd -hdl_version VHDL_2008
+set_global_assignment -name VHDL_FILE ../test_fpga.vhd -hdl_version VHDL_2008
+set_global_assignment -name VHDL_FILE ../../src/Avalon_MM_wrapper.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../dds_reader_syn.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/dds_reader.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../dds_writer_syn.vhd -hdl_version VHDL_2008
@@ -63,8 +66,6 @@ set_global_assignment -name VHDL_FILE ../rtps_reader_syn.vhd -hdl_version VHDL_2
 set_global_assignment -name VHDL_FILE ../../src/rtps_reader.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../rtps_writer_syn.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/rtps_writer.vhd -hdl_version VHDL_2008
-set_global_assignment -name VHDL_FILE ../../src/FWFT_FIFO.vhd -hdl_version VHDL_2008
-set_global_assignment -name VHDL_FILE ../../src/mem_ctrl.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/rtps_builtin_endpoint.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/rtps_handler.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../test5.vhd -hdl_version VHDL_2008
@@ -73,9 +74,15 @@ set_global_assignment -name VHDL_FILE ../test3.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../test2.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../test.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../test_package.vhd -hdl_version VHDL_2008
+set_global_assignment -name VHDL_FILE ../../src/mem_ctrl.vhd -hdl_version VHDL_2008
+set_global_assignment -name VHDL_FILE ../../src/FWFT_FIFO_cfg.vhd -hdl_version VHDL_2008
+set_global_assignment -name VHDL_FILE ../../src/FWFT_FIFO_Altera.vhd -hdl_version VHDL_2008
+set_global_assignment -name VHDL_FILE ../../src/FWFT_FIFO.vhd -hdl_version VHDL_2008
+set_global_assignment -name VHDL_FILE ../../src/single_port_ram_cfg.vhd -hdl_version VHDL_2008
+set_global_assignment -name VHDL_FILE ../../src/single_port_ram_Altera.vhd -hdl_version VHDL_2008
+set_global_assignment -name VHDL_FILE ../../src/single_port_ram.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/rtps_config_package.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../syn_config.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/rtps_package.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/math_pkg.vhd -hdl_version VHDL_2008
-set_global_assignment -name VHDL_FILE ../../src/single_port_ram.vhd -hdl_version VHDL_2008
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

syn/test_fpga.vhd

@@ -0,0 +1,169 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.rtps_package.all;
+
+entity test_fpga is
+    port (
+        -- SYSTEM
+        clk         : in std_logic;
+        reset       : in std_logic;
+        -- INPUT
+        empty       : in std_logic;
+        read        : out std_logic;
+        data_in     : in std_logic_vector(WORD_WIDTH-1 downto 0);
+        -- OUTPUT
+        full        : in std_logic;
+        write       : out std_logic;
+        data_out    : out std_logic_vector(WORD_WIDTH-1 downto 0)
+    );
+end entity;
+
+architecture arch of test_fpga is
+    
+    --*****TYPE DECLARATION*****
+    type STAGE_TYPE is (SRC_ADDR_IN,DEST_ADDR_IN,UDP_PORTS_IN,PACKET_LEN_IN,SRC_ADDR_OUT,DEST_ADDR_OUT,UDP_PORTS_OUT,PACKET_LEN_OUT,WRITE_MAGIC_WORD,WRITE_PACKET);
+    
+    --*****CONSTANT DECLARATION*****
+    constant RES_IPv4_ADDRESS   : std_logic_vector(IPv4_ADDRESS_WIDTH-1 downto 0) := x"C0A8000A"; --192.168.0.10
+    constant MAGIC_WORD         : std_logic_vector(WORD_WIDTH-1 downto 0) := x"DEADBEEF";
+    
+    --*****SIGNAL DECLARATION*****
+    signal stage, stage_next : STAGE_TYPE;
+    signal src_addr, src_addr_next : std_logic_vector(IPv4_ADDRESS_WIDTH-1 downto 0);
+    signal dest_addr, dest_addr_next : std_logic_vector(IPv4_ADDRESS_WIDTH-1 downto 0);
+    signal src_port, src_port_next : std_logic_vector(UDP_PORT_WIDTH-1 downto 0);
+    signal dest_port, dest_port_next : std_logic_vector(UDP_PORT_WIDTH-1 downto 0);
+    signal len, len_next : unsigned(WORD_WIDTH-1 downto 0);
+    
+begin
+    
+    main_prc : process(all)
+    begin
+        -- DEFAULT
+        stage_next      <= stage;
+        src_addr_next   <= src_addr;
+        dest_addr_next  <= dest_addr;
+        src_port_next   <= src_port;
+        dest_port_next  <= dest_port;
+        len_next        <= len;
+        read            <= '0';
+        write           <= '0';
+        data_out        <= (others => '0');
+        
+        case (stage) is
+            when SRC_ADDR_IN =>
+                -- Input Guard
+                if (empty = '0') then
+                    read            <= '1';
+                    src_addr_next   <= data_in;
+                    
+                    stage_next  <= DEST_ADDR_IN;
+                end if;
+            when DEST_ADDR_IN =>
+                -- Input Guard
+                if (empty = '0') then
+                    read            <= '1';
+                    dest_addr_next  <= data_in;
+                    
+                    stage_next  <= UDP_PORTS_IN;
+                end if;
+            when UDP_PORTS_IN =>
+                -- Input Guard
+                if (empty = '0') then
+                    read            <= '1';
+                    src_port_next   <= data_in(WORD_WIDTH-1 downto WORD_WIDTH-UDP_PORT_WIDTH);
+                    dest_port_next  <= data_in(UDP_PORT_WIDTH-1 downto 0);
+                    
+                    stage_next  <= PACKET_LEN_IN;
+                end if;
+            when PACKET_LEN_IN =>
+                -- Input Guard
+                if (empty = '0') then
+                    read        <= '1';
+                    len_next    <= unsigned(data_in) + 1;
+                    
+                    stage_next  <= SRC_ADDR_OUT;
+                end if;
+            when SRC_ADDR_OUT =>
+                -- Output Guard
+                if (full = '0') then
+                    write       <= '1';
+                    data_out    <= dest_addr;
+                    
+                    stage_next  <= DEST_ADDR_OUT;
+                end if;
+            when DEST_ADDR_OUT =>
+                -- Output Guard
+                if (full = '0') then
+                    write       <= '1';
+                    data_out    <= RES_IPv4_ADDRESS;
+                    
+                    stage_next  <= UDP_PORTS_OUT;
+                end if;
+            when UDP_PORTS_OUT =>
+                -- Output Guard
+                if (full = '0') then
+                    write       <= '1';
+                    data_out    <= dest_port & src_port;
+                    
+                    stage_next  <= PACKET_LEN_OUT;
+                end if;
+            when PACKET_LEN_OUT =>
+                -- Output Guard
+                if (full = '0') then
+                    write       <= '1';
+                    data_out    <= std_logic_vector(len);
+                    
+                    stage_next  <= WRITE_MAGIC_WORD;
+                end if;
+            when WRITE_MAGIC_WORD =>
+                -- Output Guard
+                if (full = '0') then
+                    write       <= '1';
+                    data_out    <= MAGIC_WORD;
+                    len_next    <= len - 1;
+                    
+                    stage_next  <= WRITE_PACKET;
+                end if;
+            when WRITE_PACKET =>
+                if (len = 0) then
+                    stage_next  <= SRC_ADDR_IN;
+                else
+                    -- I/O Guard
+                    if (empty = '0' and full = '0') then
+                        -- Passthrough
+                        read        <= '1';
+                        write       <= '1';
+                        data_out    <= data_in;
+                        len_next    <= len - 1;
+                    end if;
+                end if;
+            when others =>
+                null;
+        end case;
+    end process;
+    
+    sync_prc : process(clk)
+    begin
+        if rising_edge(clk) then
+            if (reset = '1') then
+                stage       <= SRC_ADDR_IN;
+                src_addr    <= IPv4_ADDRESS_INVALID;
+                dest_addr   <= IPv4_ADDRESS_INVALID;
+                src_port    <= UDP_PORT_INVALID;
+                dest_port   <= UDP_PORT_INVALID;
+                len         <= (others => '0');
+            else
+                stage       <= stage_next;
+                src_addr    <= src_addr_next;
+                dest_addr   <= dest_addr_next;
+                src_port    <= src_port_next;
+                dest_port   <= dest_port_next;
+                len         <= len_next;
+            end if;
+        end if;
+    end process;
+    
+end architecture;

syn/test_top.vhd

@@ -0,0 +1,94 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.rtps_package.all;
+
+entity test_top is
+    port (
+        -- SYSTEM
+        clk         : in std_logic;
+        reset       : in std_logic;
+        -- AVALON MM INTERFACE
+        address     : in std_logic_vector(1 downto 0);
+        read        : in std_logic;
+        write       : in std_logic;
+        readdata    : out std_logic_vector(WORD_WIDTH-1 downto 0);
+        writedata   : in std_logic_vector(WORD_WIDTH-1 downto 0);
+        waitrequest : out std_logic
+    );
+end entity;
+
+architecture arch of test_top is
+    
+    signal full_fi_wr, write_wr_fi, empty_fo_wr, read_wr_fo, empty_fi_test, read_test_fi, full_fo_test, write_test_fo : std_logic;
+    signal data_wr_fi, data_fo_wr, data_fi_test, data_test_fo : std_logic_vector(WORD_WIDTH-1 downto 0);
+    
+begin
+    
+    Avalon_MM_wrapper_inst : entity work.Avalon_MM_wrapper(arch)
+        port map (
+            clk         => clk,
+            reset       => reset,
+            address     => address,
+            read        => read,
+            write       => write,
+            readdata    => readdata,
+            writedata   => writedata,
+            waitrequest => waitrequest,
+            full_ri     => full_fi_wr,
+            write_ri    => write_wr_fi,
+            data_ri     => data_wr_fi,
+            empty_ro    => empty_fo_wr,
+            read_ro     => read_wr_fo,
+            data_ro     => data_fo_wr
+        );
+    
+    FIFO_IN_inst : configuration work.FWFT_FIFO_cfg
+        generic map (
+            FIFO_DEPTH  => 16384,
+            DATA_WIDTH  => 32
+        )
+        port map (
+            clk         => clk,
+            reset       => reset,
+            data_in     => data_wr_fi,
+            write       => write_wr_fi,
+            read        => read_test_fi,
+            data_out    => data_fi_test,
+            empty       => empty_fi_test,
+            full        => full_fi_wr,
+            free        => open
+        );
+    
+    FIFO_OUT_inst : configuration work.FWFT_FIFO_cfg
+        generic map (
+            FIFO_DEPTH  => 16384,
+            DATA_WIDTH  => 32
+        )
+        port map (
+            clk         => clk,
+            reset       => reset,
+            data_in     => data_test_fo,
+            write       => write_test_fo,
+            read        => read_wr_fo,
+            data_out    => data_fo_wr,
+            empty       => empty_fo_wr,
+            full        => full_fo_test,
+            free        => open
+        );
+    
+    test_fpga_inst : entity work.test_fpga(arch)
+        port map (
+            clk         => clk,
+            reset       => reset,
+            empty       => empty_fi_test,
+            read        => read_test_fi,
+            data_in     => data_fi_test,
+            full        => full_fo_test,
+            write       => write_test_fo,
+            data_out    => data_test_fo
+        );
+    
+    
+end architecture;