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Add Level 1 Test 1 of TYPE2 key_holder

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The writer_wrapper is used to push normal payloads, and the serialized
key is hardcoded and compared to the output.
This commit is contained in:
Greek 2021-11-07 13:12:13 +01:00
parent 57128bcea3
commit 27aa801e74
11 changed files with 633 additions and 50 deletions
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47
sim/L1_Type2_key_holder.do Normal file
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@ -0,0 +1,47 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider SYSTEM
add wave -noupdate /l1_type2_key_holder_test1/uut/clk
add wave -noupdate /l1_type2_key_holder_test1/uut/reset
add wave -noupdate /l1_type2_key_holder_test1/uut/start
add wave -noupdate /l1_type2_key_holder_test1/uut/opcode
add wave -noupdate /l1_type2_key_holder_test1/uut/ack
add wave -noupdate /l1_type2_key_holder_test1/uut/decode_error
add wave -noupdate -divider INPUT
add wave -noupdate -radix hexadecimal /l1_type2_key_holder_test1/uut/data_in
add wave -noupdate /l1_type2_key_holder_test1/uut/valid_in
add wave -noupdate /l1_type2_key_holder_test1/uut/ready_in
add wave -noupdate /l1_type2_key_holder_test1/uut/last_word_in
add wave -noupdate -divider OUTPUT
add wave -noupdate -radix hexadecimal /l1_type2_key_holder_test1/uut/data_out
add wave -noupdate /l1_type2_key_holder_test1/uut/valid_out
add wave -noupdate /l1_type2_key_holder_test1/uut/ready_out
add wave -noupdate /l1_type2_key_holder_test1/uut/last_word_out
add wave -noupdate -divider INTERNAL
add wave -noupdate /l1_type2_key_holder_test1/uut/stage
add wave -noupdate /l1_type2_key_holder_test1/uut/stage_next
add wave -noupdate /l1_type2_key_holder_test1/uut/decode_stage
add wave -noupdate /l1_type2_key_holder_test1/uut/decode_stage_next
add wave -noupdate /l1_type2_key_holder_test1/uut/encode_stage
add wave -noupdate /l1_type2_key_holder_test1/uut/encode_stage_next
add wave -noupdate /l1_type2_key_holder_test1/uut/cnt
add wave -noupdate -divider MISC
add wave -noupdate /l1_type2_key_holder_test1/uut/align_offset
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {13838438 ps} 0}
quietly wave cursor active 1
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {13547400 ps} {14571400 ps}

430
src/Tests/Level_1/L1_Type2_key_holder_test1.vhd Normal file
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@ -0,0 +1,430 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library osvvm; -- Utility Library
context osvvm.OsvvmContext;
use work.rtps_package.all;
use work.user_config.all;
use work.rtps_config_package.all;
use work.rtps_test_package.all;
use work.Type2_package.all;
entity L1_Type2_key_holder_test1 is
end entity;
architecture testbench of L1_Type2_key_holder_test1 is
signal clk, reset : std_logic := '0';
signal ready_sk, ready_w, ready_kh_in, ready_kh_out, valid_sk, valid_w, valid_kh_in, valid_kh_out, last_word_sk, last_word_w, last_word_kh_in, last_word_kh_out : std_logic := '0';
signal data_sk, data_w, data_kh_in, data_kh_out : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal start_w, ack_w, start_kh, ack_kh, decode_error, encode_done : std_logic := '0';
signal opcode_kh : KEY_HOLDER_OPCODE_TYPE := NOP;
shared variable SB_out : osvvm.ScoreBoardPkg_slv.ScoreBoardPType;
shared variable serialized_key : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
signal key_hash, key_hash_latch : KEY_HASH_TYPE := HANDLE_NIL;
signal id_in : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_len_in, TestSequence_addr_in: std_logic_vector(TESTSEQUENCE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_ready_in, TestSequence_wen_in : std_logic := '0';
signal TestSequence_TestArray_addr_in : std_logic_vector(TESTSEQUENCE_TESTARRAY_ADDR_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_TestArray_ready_in, TestSequence_TestArray_wen_in : std_logic := '0';
signal TestSequence_TestArray_w_in : std_logic_vector(CDR_OCTET_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_TestChar_w_in : std_logic_vector(CDR_CHAR_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_TestWChar_w_in : std_logic_vector(CDR_WCHAR_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_TestLongLong_w_in : std_logic_vector(CDR_LONG_LONG_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_TestLongDouble_w_in : std_logic_vector(CDR_LONG_DOUBLE_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_TestLongDouble_valid_w_in : std_logic := '0';
signal TestMap_len_in, TestMap_addr_in : std_logic_vector(TESTMAP_ADDR_WIDTH-1 downto 0) := (others => '0');
signal TestMap_ready_in, TestMap_wen_in : std_logic := '0';
signal TestMap_key_w_in : std_logic_vector(CDR_OCTET_WIDTH-1 downto 0) := (others => '0');
signal TestMap_value_w_in : std_logic_vector(CDR_SHORT_WIDTH-1 downto 0) := (others => '0');
signal TestEnum_in : std_logic_vector(TESTENUM_WIDTH-1 downto 0) := (others => '0');
signal TestUnion_valid_in : std_logic := '0';
signal TestUnion_d_in : std_logic_vector(CDR_CHAR_WIDTH-1 downto 0) := (others => '0');
signal TestUnion_LongU_in : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0');
signal TestUnion_OctetU_in : std_logic_vector(CDR_OCTET_WIDTH-1 downto 0) := (others => '0');
signal TestBitmask_in : std_logic_vector(TESTBITMASK_WIDTH-1 downto 0) := (others => '0');
signal TestString_len_in, TestString_addr_in : std_logic_vector(TESTSTRING_ADDR_WIDTH-1 downto 0) := (others => '0');
signal TestString_ready_in, TestString_wen_in : std_logic := '0';
signal TestString_w_in : std_logic_vector(CDR_CHAR_WIDTH-1 downto 0) := (others => '0');
begin
Type2_writer_wrapper_inst : entity work.Type2_writer_wrapper(arch)
port map (
clk => clk,
reset => reset,
start_dds => open,
ack_dds => '1',
opcode_dds => open,
instance_handle_dds => open,
source_ts_dds => open,
max_wait_dds => open,
done_dds => '1',
return_code_dds => RETCODE_OK,
ready_out_dds => ready_w,
valid_out_dds => valid_w,
data_out_dds => data_w,
last_word_out_dds => last_word_w,
ready_in_dds => open,
valid_in_dds => '0',
data_in_dds => (others => '0'),
last_word_in_dds => '0',
status_dds => (others => '0'),
start_user => start_w,
ack_user => ack_w,
opcode_user => WRITE,
instance_handle_user => HANDLE_NIL,
source_ts_user => TIME_ZERO,
max_wait_user => TIME_INFINITE,
done_user => open,
return_code_user => open,
ready_out_user => '1',
valid_out_user => open,
data_out_user => open,
last_word_out_user => open,
status_user => open,
encode_done => encode_done,
id => id_in,
TestSequence_len => TestSequence_len_in,
TestSequence_addr => TestSequence_addr_in,
TestSequence_ready => TestSequence_ready_in,
TestSequence_ren => '0',
TestSequence_wen => TestSequence_wen_in,
TestSequence_valid => open,
TestSequence_ack => '0',
TestSequence_TestArray_addr => TestSequence_TestArray_addr_in,
TestSequence_TestArray_ready => TestSequence_TestArray_ready_in,
TestSequence_TestArray_ren => '0',
TestSequence_TestArray_wen => TestSequence_TestArray_wen_in,
TestSequence_TestArray_valid => open,
TestSequence_TestArray_ack => '0',
TestSequence_TestArray_r => open,
TestSequence_TestArray_w => TestSequence_TestArray_w_in,
TestSequence_TestChar_r => open,
TestSequence_TestChar_w => TestSequence_TestChar_w_in,
TestSequence_TestWChar_r => open,
TestSequence_TestWChar_w => TestSequence_TestWChar_w_in,
TestSequence_TestLongLong_r => open,
TestSequence_TestLongLong_w => TestSequence_TestLongLong_w_in,
TestSequence_TestLongDouble_r => open,
TestSequence_TestLongDouble_w => TestSequence_TestLongDouble_w_in,
TestSequence_TestLongDouble_valid_r => open,
TestSequence_TestLongDouble_valid_w => TestSequence_TestLongDouble_valid_w_in,
TestMap_len => TestMap_len_in,
TestMap_addr => TestMap_addr_in,
TestMap_ready => TestMap_ready_in,
TestMap_ren => '0',
TestMap_wen => TestMap_wen_in,
TestMap_valid => open,
TestMap_ack => '0',
TestMap_key_r => open,
TestMap_key_w => TestMap_key_w_in,
TestMap_value_r => open,
TestMap_value_w => TestMap_value_w_in,
TestEnum => TestEnum_in,
TestUnion_valid => TestUnion_valid_in,
TestUnion_d => TestUnion_d_in,
TestUnion_LongU => TestUnion_LongU_in,
TestUnion_OctetU => TestUnion_OctetU_in,
TestBitmask => TestBitmask_in,
TestString_len => TestString_len_in,
TestString_addr => TestString_addr_in,
TestString_ready => TestString_ready_in,
TestString_ren => '0',
TestString_wen => TestString_wen_in,
TestString_valid => open,
TestString_ack => '0',
TestString_r => open,
TestString_w => TestString_w_in
);
uut : entity work.key_holder(TYPE2)
port map (
clk => clk,
reset => reset,
start => start_kh,
opcode => opcode_kh,
ack => ack_kh,
decode_error => decode_error,
data_in => data_kh_in,
valid_in => valid_kh_in,
ready_in => ready_kh_in,
last_word_in => last_word_kh_in,
data_out => data_kh_out,
valid_out => valid_kh_out,
ready_out => ready_kh_out,
last_word_out => last_word_kh_out
);
stimulus_prc : process
variable RV : RandomPType;
variable align_offset : unsigned(MAX_ALIGN_OFFSET_WIDTH-1 downto 0) := (others => '0');
variable SK, KH : AlertLogIDType;
procedure wait_on_sig(signal sig : std_logic) is
begin
if (sig /= '1') then
wait on sig until sig = '1';
end if;
end procedure;
procedure push_sk is
begin
for i in 0 to serialized_key.length-1 loop
SB_out.Push(serialized_key.data(i));
end loop;
end procedure;
begin
SetAlertLogName("Type2_key_holder - Level 1");
SetAlertEnable(FAILURE, TRUE);
SetAlertEnable(ERROR, TRUE);
SetAlertEnable(WARNING, TRUE);
SetLogEnable(DEBUG, FALSE);
SetLogEnable(PASSED, FALSE);
SetLogEnable(INFO, TRUE);
RV.InitSeed(RV'instance_name);
SK := GetAlertLogID("SerializedKey", ALERTLOG_BASE_ID);
KH := GetAlertLogID("KeyHash", ALERTLOG_BASE_ID);
Log("Setting Data in Writer Side", INFO);
start_w <= '0';
wait until rising_edge(clk);
-- Static
id_in <= RV.RandSlv(id_in'length);
TestEnum_in <= RV.RandSlv(TestEnum_in'length);
TestUnion_valid_in <= '1';
TestUnion_d_in <= (others => '0');
TestUnion_LongU_in <= RV.RandSlv(TestUnion_LongU_in'length);
TestUnion_OctetU_in <= RV.RandSlv(TestUnion_OctetU_in'length);
TestBitmask_in <= RV.RandSlv(TestBitmask_in'length);
wait for 0 ns;
gen_CDR(id_in, ALIGN_4, align_offset, serialized_key);
TestSequence_len_in <= int(2,TestSequence_len_in'length);
gen_CDR(int(2,CDR_LONG_WIDTH), ALIGN_4, align_offset, serialized_key);
-- Memory
for i in 0 to 1 loop
TestSequence_addr_in <= int(i,TestSequence_addr_in'length);
TestSequence_TestChar_w_in <= RV.RandSlv(TestSequence_TestChar_w_in'length);
TestSequence_TestWChar_w_in <= RV.RandSlv(TestSequence_TestWChar_w_in'length);
TestSequence_TestLongLong_w_in <= RV.RandSlv(TestSequence_TestLongLong_w_in'length);
TestSequence_TestLongDouble_w_in <= RV.RandSlv(TestSequence_TestLongDouble_w_in'length);
TestSequence_TestLongDouble_valid_w_in <= RV.RandSlv(1)(1);
for j in 0 to 4 loop
TestSequence_TestArray_addr_in <= int(j,TestSequence_TestArray_addr_in'length);
TestSequence_TestArray_w_in <= RV.RandSlv(TestSequence_TestArray_w_in'length);
wait_on_sig(TestSequence_TestArray_ready_in);
TestSequence_TestArray_wen_in <= '1';
wait until rising_edge(clk);
TestSequence_TestArray_wen_in <= '0';
gen_CDR(TestSequence_TestArray_w_in, ALIGN_1, align_offset, serialized_key);
end loop;
wait_on_sig(TestSequence_ready_in);
TestSequence_wen_in <= '1';
wait until rising_edge(clk);
TestSequence_wen_in <= '0';
end loop;
for i in 0 to 0 loop
TestMap_len_in <= int(1,TestMap_len_in'length);
TestMap_addr_in <= int(i,TestMap_addr_in'length);
TestMap_key_w_in <= RV.RandSlv(TestMap_key_w_in'length);
TestMap_value_w_in <= RV.RandSlv(TestMap_value_w_in'length);
wait_on_sig(TestMap_ready_in);
TestMap_wen_in <= '1';
wait until rising_edge(clk);
TestMap_wen_in <= '0';
end loop;
for i in 0 to 9 loop
TestString_len_in <= int(10,TestString_len_in'length);
TestString_addr_in <= int(i,TestString_addr_in'length);
TestString_w_in <= RV.RandSlv(TestString_w_in'length);
wait_on_sig(TestString_ready_in);
TestString_wen_in <= '1';
wait until rising_edge(clk);
TestString_wen_in <= '0';
end loop;
-- Finalize Serialized Key
if (align_offset(1 downto 0) /= "00") then
serialized_key.length := serialized_key.length + 1;
end if;
push_sk;
Log("Push DATA", INFO);
opcode_kh <= PUSH_DATA;
start_w <= '1';
wait_on_sig(ack_w);
wait until rising_edge(clk);
start_w <= '0';
start_kh <= '1';
wait_on_sig(ack_kh);
wait until rising_edge(clk);
start_kh <= '0';
wait_on_sig(last_word_kh_in);
wait_on_sig(ready_kh_in);
wait until rising_edge(clk);
Log("Read and Compare Serialized Key", INFO);
opcode_kh <= READ_SERIALIZED_KEY;
start_kh <= '1';
wait_on_sig(ack_kh);
wait until rising_edge(clk);
start_kh <= '0';
wait_on_sig(last_word_kh_out);
wait_on_sig(ready_kh_out);
wait until rising_edge(clk);
Log("Read Key Hash", INFO);
opcode_kh <= READ_KEY_HASH;
start_kh <= '1';
wait_on_sig(ack_kh);
wait until rising_edge(clk);
start_kh <= '0';
wait_on_sig(last_word_kh_out);
wait_on_sig(ready_kh_out);
wait until rising_edge(clk);
Log("Push Serialized Key", INFO);
opcode_kh <= PUSH_SERIALIZED_KEY;
start_kh <= '1';
wait_on_sig(ack_kh);
wait until rising_edge(clk);
start_kh <= '0';
wait_on_sig(last_word_sk);
wait_on_sig(ready_sk);
wait until rising_edge(clk);
push_sk;
Log("Read and Compare Serialized Key", INFO);
opcode_kh <= READ_SERIALIZED_KEY;
start_kh <= '1';
wait_on_sig(ack_kh);
wait until rising_edge(clk);
start_kh <= '0';
wait_on_sig(last_word_kh_out);
wait_on_sig(ready_kh_out);
wait until rising_edge(clk);
-- Latch previous read Key Hash
key_hash_latch <= key_hash;
Log("Read and Compare Key Hash", INFO);
opcode_kh <= READ_KEY_HASH;
start_kh <= '1';
wait_on_sig(ack_kh);
wait until rising_edge(clk);
start_kh <= '0';
wait_on_sig(last_word_kh_out);
wait_on_sig(ready_kh_out);
wait until rising_edge(clk);
AffirmIfEqual(KH, to_unsigned(key_hash), to_unsigned(key_hash_latch));
TranscriptOpen(RESULTS_FILE, APPEND_MODE);
SetTranscriptMirror;
ReportAlerts;
TranscriptClose;
std.env.stop;
wait;
end process;
clock_prc : process
begin
clk <= '0';
wait for TEST_CLOCK_PERIOD/2;
clk <= '1';
wait for TEST_CLOCK_PERIOD/2;
end process;
alert_prc : process(all)
begin
if rising_edge(clk) then
Alertif(decode_error = '1', "The Reader signals a DECODE Error", ERROR);
end if;
end process;
switch_prc : process(all)
begin
case (opcode_kh) is
when PUSH_SERIALIZED_KEY =>
ready_sk <= ready_kh_in;
valid_kh_in <= valid_sk;
data_kh_in <= data_sk;
last_word_kh_in <= last_word_sk;
ready_w <= '0';
when others =>
ready_w <= ready_kh_in;
valid_kh_in <= valid_w;
data_kh_in <= data_w;
last_word_kh_in <= last_word_w;
ready_sk <= '0';
end case;
end process;
sk_prc : process(all)
variable cnt : natural := 0;
begin
if rising_edge(clk) then
valid_sk <= '1';
data_sk <= serialized_key.data(cnt);
if (cnt = serialized_key.length-1) then
last_word_sk <= '1';
end if;
if (ready_sk = '1') then
if (cnt = serialized_key.length-1) then
cnt := 0;
else
cnt := cnt + 1;
end if;
end if;
end if;
end process;
output_check_prc : process(all)
variable cnt : natural range 0 to 3 := 0;
begin
if rising_edge(clk) then
case (opcode_kh) is
when READ_KEY_HASH =>
ready_kh_out <= '1';
if (valid_kh_out = '1') then
key_hash(cnt) <= data_kh_out;
if (cnt = 3) then
cnt := 0;
Alertif(last_word_kh_out = '0', "last_word_in is 0");
else
cnt := cnt + 1;
end if;
end if;
when READ_SERIALIZED_KEY =>
ready_kh_out <= '1';
if (valid_kh_out = '1') then
SB_out.Check(data_kh_out);
if (SB_out.empty) then
Alertif(last_word_kh_out = '0', "last_word_in is 0");
end if;
end if;
when others =>
ready_kh_out <= '0';
end case;
end if;
end process;
watchdog : process
begin
wait for 1 ms;
Alert("Test timeout", FAILURE);
std.env.stop;
end process;
end architecture;

32
src/Tests/Type2_key_holder.vhd
View File

@ -142,6 +142,7 @@ begin
target_align_next <= target_align; target_align_next <= target_align;
optional_next <= optional; optional_next <= optional;
data_in_latch_next <= data_in_latch; data_in_latch_next <= data_in_latch;
data_out_latch_next <= data_out_latch;
opcode_latch_next <= opcode_latch; opcode_latch_next <= opcode_latch;
key_hash_next <= key_hash; key_hash_next <= key_hash;
align_op_next <= align_op; align_op_next <= align_op;
@ -151,6 +152,9 @@ begin
ready_in_sig <= '0'; ready_in_sig <= '0';
last_word_out <= '0'; last_word_out <= '0';
valid_out <= '0'; valid_out <= '0';
start_md5 <= '0';
valid_in_md5 <= '0';
data_in_md5 <= (others => '0');
data_out <= (others => '0'); data_out <= (others => '0');
-- ###GENERATED START### -- ###GENERATED START###
id_latch_next <= id_latch; id_latch_next <= id_latch;
@ -188,6 +192,8 @@ begin
endian_flag_next <= '0'; endian_flag_next <= '0';
stage_next <= FETCH; stage_next <= FETCH;
decode_stage_next <= GET_ID; decode_stage_next <= GET_ID;
-- Alignment Reset
align_offset_next <= (others => '0');
when READ_KEY_HASH => when READ_KEY_HASH =>
ack <= '1'; ack <= '1';
-- Key Hash not calculated -- Key Hash not calculated
@ -202,6 +208,9 @@ begin
ack <= '1'; ack <= '1';
stage_next <= SERIALIZE_KEY; stage_next <= SERIALIZE_KEY;
encode_stage_next <= WRITE_ID; encode_stage_next <= WRITE_ID;
-- Alignment Reset
align_offset_next <= (others => '0');
data_out_latch_next <= (others => '0');
when others => when others =>
null; null;
end case; end case;
@ -267,7 +276,7 @@ begin
end if; end if;
end if; end if;
when SKIP_PAYLOAD => when SKIP_PAYLOAD =>
if (last_word_in_latch = '0' and last_word_in = '0') then if (last_word_in_latch = '0') then
-- Skip Read -- Skip Read
ready_in_sig <= '1'; ready_in_sig <= '1';
else else
@ -319,7 +328,7 @@ begin
target_align_next <= ALIGN_1; target_align_next <= ALIGN_1;
stage_next <= ALIGN_IN_STREAM; stage_next <= ALIGN_IN_STREAM;
else else
TestSequence_TestArray_mem_addr(TestSequence_cnt) <= std_logic_vector(to_unsigned(TestSequence_TestArray_cnt,TestSequence_TestArray_mem_addr'length)); TestSequence_TestArray_mem_addr(TestSequence_cnt) <= std_logic_vector(to_unsigned(TestSequence_TestArray_cnt,TESTSEQUENCE_TESTARRAY_ADDR_WIDTH));
TestSequence_TestArray_mem_data_in(TestSequence_cnt) <= endian_swap(endian_flag, get_sub_vector(data_in_latch, to_integer(align_offset(1 downto 0)), CDR_OCTET_WIDTH, TRUE)); TestSequence_TestArray_mem_data_in(TestSequence_cnt) <= endian_swap(endian_flag, get_sub_vector(data_in_latch, to_integer(align_offset(1 downto 0)), CDR_OCTET_WIDTH, TRUE));
TestSequence_TestArray_mem_valid_in(TestSequence_cnt) <= '1'; TestSequence_TestArray_mem_valid_in(TestSequence_cnt) <= '1';
-- Memory Operation Guard -- Memory Operation Guard
@ -330,7 +339,7 @@ begin
if (TestSequence_TestArray_cnt = TESTSEQUENCE_TESTARRAY_MAX_DEPTH-1) then if (TestSequence_TestArray_cnt = TESTSEQUENCE_TESTARRAY_MAX_DEPTH-1) then
-- DES: The decoding stages are used for both PUSH_DATA and PUSH_SERIALIZED_KEY. -- DES: The decoding stages are used for both PUSH_DATA and PUSH_SERIALIZED_KEY.
-- We us the latched opcode to differentiate between them. -- We us the latched opcode to differentiate between them.
if (opcode_latch = READ_SERIALIZED_KEY) then if (opcode_latch = PUSH_SERIALIZED_KEY) then
decode_stage_next <= TESTSEQUENCE_MEMBER_END; decode_stage_next <= TESTSEQUENCE_MEMBER_END;
else else
decode_stage_next <= GET_TESTSEQUENCE_TESTCHAR; decode_stage_next <= GET_TESTSEQUENCE_TESTCHAR;
@ -353,7 +362,7 @@ begin
stage_next <= ALIGN_IN_STREAM; stage_next <= ALIGN_IN_STREAM;
else else
align_offset_next <= align_offset + 1; align_offset_next <= align_offset + 1;
decode_stage_next <= GET_TESTSEQUENCE_TESTWCHAR; decode_stage_next <= GET_TESTSEQUENCE_TESTWCHAR;
-- Need to fetch next Word -- Need to fetch next Word
if(align_offset(1 downto 0) = "11") then if(align_offset(1 downto 0) = "11") then
@ -505,7 +514,7 @@ begin
if (opcode_latch = READ_KEY_HASH) then if (opcode_latch = READ_KEY_HASH) then
-- Mark Last Word -- Mark Last Word
if (finalize_payload = '1' and cnt_2 = to_integer(unsigned(align_offset(1 downto 0)))) then if (finalize_payload = '1' and cnt_2 = to_integer(unsigned(align_offset(1 downto 0)))) then
last_word_out <= '1'; last_word_in_md5 <= '1';
end if; end if;
valid_in_md5 <= '1'; valid_in_md5 <= '1';
@ -619,7 +628,7 @@ begin
case (cnt) is case (cnt) is
-- GET -- GET
when 0 => when 0 =>
TestSequence_TestArray_mem_addr(TestSequence_cnt) <= std_logic_vector(to_unsigned(TestSequence_TestArray_cnt,TestSequence_TestArray_mem_addr'length)); TestSequence_TestArray_mem_addr(TestSequence_cnt) <= std_logic_vector(to_unsigned(TestSequence_TestArray_cnt,TESTSEQUENCE_TESTARRAY_ADDR_WIDTH));
TestSequence_TestArray_mem_valid_in(TestSequence_cnt) <= '1'; TestSequence_TestArray_mem_valid_in(TestSequence_cnt) <= '1';
TestSequence_TestArray_mem_read(TestSequence_cnt) <= '1'; TestSequence_TestArray_mem_read(TestSequence_cnt) <= '1';
-- Memory Operation Guard -- Memory Operation Guard
@ -638,8 +647,7 @@ begin
-- All Elements processed -- All Elements processed
if (TestSequence_TestArray_cnt = TESTSEQUENCE_TESTARRAY_MAX_DEPTH-1) then if (TestSequence_TestArray_cnt = TESTSEQUENCE_TESTARRAY_MAX_DEPTH-1) then
-- DONE -- DONE
stage_next <= PUSH; encode_stage_next <= TESTSEQUENCE_MEMBER_END;
finalize_payload_next <= '1';
else else
TestSequence_TestArray_cnt_next <= TestSequence_TestArray_cnt + 1; TestSequence_TestArray_cnt_next <= TestSequence_TestArray_cnt + 1;
end if; end if;
@ -718,7 +726,7 @@ begin
-- OVERREAD GUARD -- OVERREAD GUARD
-- Attempted read on empty input -- Attempted read on empty input
if (last_word_in_latch = '1' and ready_in_sig = '1') then if (last_word_in_latch = '1' and last_word_in = '0' and ready_in_sig = '1') then
stage_next <= SKIP_PAYLOAD; stage_next <= SKIP_PAYLOAD;
decode_error_latch_next <= '1'; decode_error_latch_next <= '1';
end if; end if;
@ -739,12 +747,13 @@ begin
cnt_2 <= 0; cnt_2 <= 0;
endian_flag <= '0'; endian_flag <= '0';
last_word_in_latch <= '0'; last_word_in_latch <= '0';
decode_error <= '0'; decode_error_latch <= '0';
optional <= '0'; optional <= '0';
align_op <= '0'; align_op <= '0';
finalize_payload <= '0'; finalize_payload <= '0';
align_offset <= (others => '0'); align_offset <= (others => '0');
data_in_latch <= (others => '0'); data_in_latch <= (others => '0');
data_out_latch <= (others => '0');
key_hash <= HANDLE_NIL; key_hash <= HANDLE_NIL;
-- ###GENERATED START### -- ###GENERATED START###
id_latch <= (others => '0'); id_latch <= (others => '0');
@ -763,12 +772,13 @@ begin
cnt_2 <= cnt_2_next; cnt_2 <= cnt_2_next;
endian_flag <= endian_flag_next; endian_flag <= endian_flag_next;
last_word_in_latch <= last_word_in_latch_next; last_word_in_latch <= last_word_in_latch_next;
decode_error <= decode_error_latch_next; decode_error_latch <= decode_error_latch_next;
optional <= optional_next; optional <= optional_next;
align_op <= align_op_next; align_op <= align_op_next;
finalize_payload <= finalize_payload_next; finalize_payload <= finalize_payload_next;
align_offset <= align_offset_next; align_offset <= align_offset_next;
data_in_latch <= data_in_latch_next; data_in_latch <= data_in_latch_next;
data_out_latch <= data_out_latch_next;
key_hash <= key_hash_next; key_hash <= key_hash_next;
-- ###GENERATED START### -- ###GENERATED START###
id_latch <= id_latch_next; id_latch <= id_latch_next;

35
src/Tests/Type2_package.vhd
View File

@ -49,39 +49,4 @@ package Type2_package is
constant MAX_TYPE2_KEY_HOLDER_SIZE : natural := 28; constant MAX_TYPE2_KEY_HOLDER_SIZE : natural := 28;
-- TODO:
constant MAX_ALIGN_OFFSET_WIDTH : natural := 3;
type ALIGN_TYPE is (ALIGN_1, ALIGN_2, ALIGN_4, ALIGN_8);
function check_align(offset : unsigned; align : ALIGN_TYPE) return boolean;
end package; end package;
package body Type2_package is
function check_align(offset : unsigned; align : ALIGN_TYPE) return boolean is
variable ret : boolean := FALSE;
begin
assert (offset'length = MAX_ALIGN_OFFSET_WIDTH) severity FAILURE;
case (align) is
when ALIGN_1 =>
ret := TRUE;
when ALIGN_2 =>
if (offset(0 downto 0) = "0") then
ret := TRUE;
end if;
when ALIGN_4 =>
if (offset(1 downto 0) = "00") then
ret := TRUE;
end if;
when ALIGN_8 =>
if (offset(2 downto 0) = "000") then
ret := TRUE;
end if;
end case;
return ret;
end function;
end package body;

2
src/Tests/Type2_reader_wrapper.vhd
View File

@ -1078,7 +1078,7 @@ begin
-- OVERREAD GUARD -- OVERREAD GUARD
-- Attempted read on empty input -- Attempted read on empty input
if (last_word_in_latch = '1' and ready_in_dds_sig = '1') then if (last_word_in_latch = '1' and last_word_in_dds = '0' and ready_in_dds_sig = '1') then
stage_next <= SKIP_PAYLOAD; stage_next <= SKIP_PAYLOAD;
decode_error_latch_next <= '1'; decode_error_latch_next <= '1';
end if; end if;

69
src/Tests/test_md5.vhd Normal file
View File

@ -0,0 +1,69 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture arch of md5_calculator is
type STAGE_TYPE is (IDLE, GEN_CHECKSUM, FINALIZE);
signal stage, stage_next : STAGE_TYPE := IDLE;
signal checksum, checksum_next : std_logic_vector(127 downto 0) := (others => '0');
signal done_sig, done_sig_next : std_logic := '0';
begin
done <= done_sig;
hash_out <= checksum;
checksum_prc : process(all)
begin
-- DEFAULT
stage_next <= stage;
checksum_next <= checksum;
done_sig_next <= '0';
ack <= '0';
case (stage) is
when IDLE =>
if (start = '1') then
ack <= '1';
stage_next <= GEN_CHECKSUM;
-- Reset
checksum_next <= (others => '0');
end if;
when GEN_CHECKSUM =>
ready_in <= '1';
-- Input Guard
if (valid_in = '1') then
checksum_next <= std_logic_vector(unsigned(checksum) + resize(unsigned(data_in),checksum'length));
-- Last Word
if (last_word_in = '1') then
stage_next <= FINALIZE;
end if;
end if;
when FINALIZE =>
checksum_next <= std_logic_vector(-signed(checksum)); -- Two's Complement
done_sig_next <= '1';
stage_next <= IDLE;
when others =>
null;
end case;
end process;
sync_prc : process(clk)
begin
if rising_edge(clk) then
if (reset = '1') then
stage <= IDLE;
done_sig <= '0';
checksum <= (others => '0');
else
stage <= stage_next;
done_sig <= done_sig_next;
checksum <= checksum_next;
end if;
end if;
end process;
end architecture;

6
src/Tests/testbench.pro
View File

@ -81,10 +81,15 @@ analyze Level_0/L0_dds_reader_test4_arznriu.vhd
analyze Level_0/L0_dds_reader_test5_arzkriu.vhd analyze Level_0/L0_dds_reader_test5_arzkriu.vhd
analyze Level_0/L0_dds_reader_test6_arzkriu.vhd analyze Level_0/L0_dds_reader_test6_arzkriu.vhd
analyze Level_0/L0_dds_reader_test7_arzkriu.vhd analyze Level_0/L0_dds_reader_test7_arzkriu.vhd
analyze ../key_holder.vhd
analyze ../md5_calculator.vhd
analyze Type2_package.vhd analyze Type2_package.vhd
analyze Type2_reader_wrapper.vhd analyze Type2_reader_wrapper.vhd
analyze Type2_writer_wrapper.vhd analyze Type2_writer_wrapper.vhd
analyze Type2_key_holder.vhd
analyze test_md5.vhd
analyze Level_1/L1_Type2_wrapper_test1.vhd analyze Level_1/L1_Type2_wrapper_test1.vhd
analyze Level_1/L1_Type2_key_holder_test1.vhd
simulate L0_rtps_handler_test1 simulate L0_rtps_handler_test1
simulate L0_rtps_handler_test2 simulate L0_rtps_handler_test2
@ -148,3 +153,4 @@ simulate L0_dds_reader_test5_arzkriu
simulate L0_dds_reader_test6_arzkriu simulate L0_dds_reader_test6_arzkriu
simulate L0_dds_reader_test7_arzkriu simulate L0_dds_reader_test7_arzkriu
simulate L1_Type2_wrapper_test1 simulate L1_Type2_wrapper_test1
simulate L1_Type2_key_holder_test1

3
src/key_holder.vhd
View File

@ -2,6 +2,9 @@ library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
use work.rtps_package.all;
use work.rtps_config_package.all;
entity key_holder is entity key_holder is
port ( port (
clk : in std_logic; clk : in std_logic;

2
src/md5_calculator.vhd
View File

@ -16,6 +16,6 @@ entity md5_calculator is
last_word_in : in std_logic; last_word_in : in std_logic;
hash_out : out std_logic_vector(127 downto 0); hash_out : out std_logic_vector(127 downto 0);
done : out std_logic; done : out std_logic
); );
end entity; end entity;

31
src/rtps_package.vhd
View File

@ -450,6 +450,12 @@ package rtps_package is
constant PARTICIPANT_MESSAGE_DATA_KIND_AUTOMATIC_LIVELINESS_UPDATE : std_logic_vector(PARTICIPANT_MESSAGE_KIND_WIDTH-1 downto 0) := x"00000001"; constant PARTICIPANT_MESSAGE_DATA_KIND_AUTOMATIC_LIVELINESS_UPDATE : std_logic_vector(PARTICIPANT_MESSAGE_KIND_WIDTH-1 downto 0) := x"00000001";
constant PARTICIPANT_MESSAGE_DATA_KIND_MANUAL_LIVELINESS_UPDATE : std_logic_vector(PARTICIPANT_MESSAGE_KIND_WIDTH-1 downto 0) := x"00000002"; constant PARTICIPANT_MESSAGE_DATA_KIND_MANUAL_LIVELINESS_UPDATE : std_logic_vector(PARTICIPANT_MESSAGE_KIND_WIDTH-1 downto 0) := x"00000002";
--*DDS-XTYPES*
constant MAX_ALIGN_OFFSET_WIDTH : natural := 3;
type ALIGN_TYPE is (ALIGN_1, ALIGN_2, ALIGN_4, ALIGN_8);
function check_align(offset : unsigned; align : ALIGN_TYPE) return boolean;
--*CUSTOM TYPES* --*CUSTOM TYPES*
type CACHE_CHANGE_KIND_TYPE is (ALIVE, ALIVE_FILTERED, NOT_ALIVE_DISPOSED, NOT_ALIVE_UNREGISTERED); type CACHE_CHANGE_KIND_TYPE is (ALIVE, ALIVE_FILTERED, NOT_ALIVE_DISPOSED, NOT_ALIVE_UNREGISTERED);
type USER_BOOLEAN_ARRAY_TYPE is array (natural range <>) of boolean; type USER_BOOLEAN_ARRAY_TYPE is array (natural range <>) of boolean;
@ -738,4 +744,29 @@ package body rtps_package is
end loop; end loop;
return ret; return ret;
end function; end function;
function check_align(offset : unsigned; align : ALIGN_TYPE) return boolean is
variable ret : boolean := FALSE;
begin
assert (offset'length = MAX_ALIGN_OFFSET_WIDTH) severity FAILURE;
case (align) is
when ALIGN_1 =>
ret := TRUE;
when ALIGN_2 =>
if (offset(0 downto 0) = "0") then
ret := TRUE;
end if;
when ALIGN_4 =>
if (offset(1 downto 0) = "00") then
ret := TRUE;
end if;
when ALIGN_8 =>
if (offset(2 downto 0) = "000") then
ret := TRUE;
end if;
end case;
return ret;
end function;
end package body; end package body;

22
src/rtps_test_package.vhd
View File

@ -592,6 +592,8 @@ package rtps_test_package is
function gen_endpoint_array(readers : boolean) return ENDPOINT_DATA_ARRAY_TYPE; function gen_endpoint_array(readers : boolean) return ENDPOINT_DATA_ARRAY_TYPE;
-- Extract Data from RTPS Submessage (Sequence Number, Payload, Serialized_Key) and generate Cache Change -- Extract Data from RTPS Submessage (Sequence Number, Payload, Serialized_Key) and generate Cache Change
function gen_cache_change(ref : RTPS_SUBMESSAGE_TYPE) return CACHE_CHANGE_TYPE; function gen_cache_change(ref : RTPS_SUBMESSAGE_TYPE) return CACHE_CHANGE_TYPE;
procedure gen_CDR(input : std_logic_vector; target_align : ALIGN_TYPE; align_offset : inout unsigned; output : inout TEST_PACKET_TYPE);
end package; end package;
package body rtps_test_package is package body rtps_test_package is
@ -3345,4 +3347,24 @@ package body rtps_test_package is
end case; end case;
end procedure; end procedure;
procedure gen_CDR(input : std_logic_vector; target_align : ALIGN_TYPE; align_offset : inout unsigned; output : inout TEST_PACKET_TYPE) is
begin
-- Align Stream
while (not check_align(align_offset,target_align)) loop
output.data(output.length) := write_sub_vector(output.data(output.length),(BYTE_WIDTH-1 downto 0 => '0'), to_integer(align_offset(1 downto 0)), TRUE);
if (align_offset(1 downto 0) = "11") then
output.length := output.length + 1;
end if;
align_offset := align_offset + 1;
end loop;
for i in (input'length/BYTE_WIDTH)-1 downto 0 loop
output.data(output.length) := write_sub_vector(output.data(output.length),input(((i+1)*BYTE_WIDTH)-1 downto i*BYTE_WIDTH), to_integer(align_offset(1 downto 0)), TRUE);
if (align_offset(1 downto 0) = "11") then
output.length := output.length + 1;
end if;
align_offset := align_offset + 1;
end loop;
end procedure;
end package body; end package body;