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Modify ports of rtps_handler according to port naming convention

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Greek 2021-11-18 12:20:20 +01:00
parent 8f9f445f21
commit 399bd2bbda
5 changed files with 259 additions and 231 deletions
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61
src/Tests/Level_0/L0_rtps_handler_test1.vhd
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@ -88,9 +88,9 @@ architecture testbench of L0_rtps_handler_test1 is
type TEST_STAGE_TYPE is (IDLE, BUSY); type TEST_STAGE_TYPE is (IDLE, BUSY);
-- *SIGNAL DECLARATION* -- *SIGNAL DECLARATION*
signal clk, reset, in_empty, rd_sig, builtin_full, builtin_wr, last_word_out : std_logic := '0'; signal clk, reset, in_empty, rd_sig, full_be, wr_be, last_word_out_be, last_word_out_ue : std_logic := '0';
signal user_full, user_wr : std_logic_vector(0 to NUM_ENDPOINTS-1) := (others => '0'); signal full_ue, wr_ue : std_logic_vector(0 to NUM_ENDPOINTS-1) := (others => '0');
signal data_in, data_out : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); signal data_in, data_out_be, data_out_ue : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal stim_stage, ref_stage : TEST_STAGE_TYPE := IDLE; signal stim_stage, ref_stage : TEST_STAGE_TYPE := IDLE;
shared variable stimulus, reference : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; shared variable stimulus, reference : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
signal packet_sent, packet_checked : std_logic := '0'; signal packet_sent, packet_checked : std_logic := '0';
@ -111,17 +111,23 @@ begin
-- Unit Under Test -- Unit Under Test
uut : entity work.rtps_handler(arch) uut : entity work.rtps_handler(arch)
port map ( port map (
clk => clk, -- SYSTEM
reset => reset, clk => clk,
empty => in_empty or packet_sent, reset => reset,
rd => rd_sig, -- INPUT
data_in => data_in, empty => in_empty or packet_sent,
data_out => data_out, rd => rd_sig,
builtin_full => builtin_full, data_in => data_in,
builtin_wr => builtin_wr, -- TO BUILTIN ENDPOINT
user_full => user_full, full_be => full_be,
user_wr => user_wr, wr_be => wr_be,
last_word_out => last_word_out data_out_be => data_out_be,
last_word_out_be => last_word_out_be,
-- TO USER ENDPOINT
full_ue => full_ue,
wr_ue => wr_ue,
data_out_ue => data_out_ue,
last_word_out_ue => last_word_out_ue
); );
stimulus_prc : process stimulus_prc : process
@ -1303,20 +1309,20 @@ begin
fifo_ctl_prc : process fifo_ctl_prc : process
begin begin
in_empty <= '0'; in_empty <= '0';
builtin_full <= '0'; full_be <= '0';
user_full <= (others => '0'); full_ue <= (others => '0');
wait until rising_edge(clk); wait until rising_edge(clk);
in_empty <= '1'; in_empty <= '1';
builtin_full <= '0'; full_be <= '0';
user_full <= (others => '0'); full_ue <= (others => '0');
wait until rising_edge(clk); wait until rising_edge(clk);
in_empty <= '0'; in_empty <= '0';
builtin_full <= '1'; full_be <= '1';
user_full <= (others => '0'); full_ue <= (others => '0');
wait until rising_edge(clk); wait until rising_edge(clk);
in_empty <= '0'; in_empty <= '0';
builtin_full <= '0'; full_be <= '0';
user_full <= (others => '1'); full_ue <= (others => '1');
wait until rising_edge(clk); wait until rising_edge(clk);
end process; end process;
@ -1324,8 +1330,8 @@ begin
begin begin
if rising_edge(clk) then if rising_edge(clk) then
alertif(in_empty = '1' and rd_sig = '1', "Input FIFO read signal high while empty signal high", ERROR); alertif(in_empty = '1' and rd_sig = '1', "Input FIFO read signal high while empty signal high", ERROR);
alertif(builtin_full = '1' and builtin_wr = '1', "Builtin FIFO write signal high while full signal high", ERROR); alertif(full_be = '1' and wr_be = '1', "Builtin FIFO write signal high while full signal high", ERROR);
alertif(user_full /= (0 to NUM_ENDPOINTS-1 => '0') and (user_wr /= (0 to NUM_ENDPOINTS-1 => '0')), "User FIFO write signal high while full signal high", ERROR); alertif(full_ue /= (0 to NUM_ENDPOINTS-1 => '0') and (wr_ue /= (0 to NUM_ENDPOINTS-1 => '0')), "User FIFO write signal high while full signal high", ERROR);
end if; end if;
end process; end process;
@ -1383,8 +1389,11 @@ begin
when BUSY => when BUSY =>
if (cnt_ref = reference.length) then if (cnt_ref = reference.length) then
ref_stage <= IDLE; ref_stage <= IDLE;
elsif (builtin_wr = '1' or user_wr /= (0 to NUM_ENDPOINTS-1 => '0')) then elsif (wr_be = '1') then
AffirmIfEqual(last_word_out & data_out, reference.last(cnt_ref) & reference.data(cnt_ref)); AffirmIfEqual(last_word_out_be & data_out_be, reference.last(cnt_ref) & reference.data(cnt_ref));
cnt_ref <= cnt_ref + 1;
elsif (wr_ue /= (0 to NUM_ENDPOINTS-1 => '0')) then
AffirmIfEqual(last_word_out_ue & data_out_ue, reference.last(cnt_ref) & reference.data(cnt_ref));
cnt_ref <= cnt_ref + 1; cnt_ref <= cnt_ref + 1;
end if; end if;
end case; end case;

42
src/Tests/Level_0/L0_rtps_handler_test2.vhd
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@ -26,9 +26,9 @@ architecture testbench of L0_rtps_handler_test2 is
type TEST_STAGE_TYPE is (IDLE, BUSY); type TEST_STAGE_TYPE is (IDLE, BUSY);
-- *SIGNAL DECLARATION* -- *SIGNAL DECLARATION*
signal clk, reset, in_empty, rd_sig, builtin_full, builtin_wr, last_word_out : std_logic := '0'; signal clk, reset, in_empty, rd_sig, full_be, wr_be, last_word_out_be, last_word_out_ue : std_logic := '0';
signal user_full, user_wr : std_logic_vector(0 to NUM_ENDPOINTS-1) := (others => '0'); signal full_ue, wr_ue : std_logic_vector(0 to NUM_ENDPOINTS-1) := (others => '0');
signal data_in, data_out : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); signal data_in, data_out_be, data_out_ue : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal stim_stage, ref_stage : TEST_STAGE_TYPE := IDLE; signal stim_stage, ref_stage : TEST_STAGE_TYPE := IDLE;
shared variable stimulus, dummy : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; shared variable stimulus, dummy : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
signal packet_sent, packet_checked : std_logic := '0'; signal packet_sent, packet_checked : std_logic := '0';
@ -50,17 +50,23 @@ begin
-- Unit Under Test -- Unit Under Test
uut : entity work.rtps_handler(arch) uut : entity work.rtps_handler(arch)
port map ( port map (
clk => clk, -- SYSTEM
reset => reset, clk => clk,
empty => in_empty or packet_sent, reset => reset,
rd => rd_sig, -- INPUT
data_in => data_in, empty => in_empty or packet_sent,
data_out => data_out, rd => rd_sig,
builtin_full => builtin_full, data_in => data_in,
builtin_wr => builtin_wr, -- TO BUILTIN ENDPOINT
user_full => user_full, full_be => full_be,
user_wr => user_wr, wr_be => wr_be,
last_word_out => last_word_out data_out_be => data_out_be,
last_word_out_be => last_word_out_be,
-- TO USER ENDPOINT
full_ue => full_ue,
wr_ue => wr_ue,
data_out_ue => data_out_ue,
last_word_out_ue => last_word_out_ue
); );
stimulus_prc : process stimulus_prc : process
@ -113,8 +119,8 @@ begin
Log("Initiating Test", INFO); Log("Initiating Test", INFO);
in_empty <= '0'; in_empty <= '0';
builtin_full <= '0'; full_be <= '0';
user_full <= (others => '0'); full_ue <= (others => '0');
start <= '0'; start <= '0';
reset <= '1'; reset <= '1';
wait until rising_edge(clk); wait until rising_edge(clk);
@ -293,8 +299,8 @@ begin
when BUSY => when BUSY =>
if (cnt_ref = dummy.length) then if (cnt_ref = dummy.length) then
ref_stage <= IDLE; ref_stage <= IDLE;
elsif (builtin_wr = '1' or user_wr /= (0 to NUM_ENDPOINTS-1 => '0')) then elsif (wr_be = '1' or wr_ue /= (0 to NUM_ENDPOINTS-1 => '0')) then
AffirmIfEqual((user_wr & builtin_wr), reference); AffirmIfEqual((wr_ue & wr_be), reference);
cnt_ref <= cnt_ref + 1; cnt_ref <= cnt_ref + 1;
end if; end if;
end case; end case;

32
src/Tests/Level_2/L2_Testbench_Lib2.vhd
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@ -84,8 +84,8 @@ architecture arch of L2_Testbench_Lib2 is
signal last_word_out_rbe : std_logic := '0'; signal last_word_out_rbe : std_logic := '0';
signal data_out_rbe : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); signal data_out_rbe : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal last_word_out_rh_s : std_logic := '0'; signal last_word_out_rh_be_s, last_word_out_rh_ue_s : std_logic := '0';
signal data_out_rh_s : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); signal data_out_rh_be_s, data_out_rh_ue_s : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal data_rtps_out_s : RTPS_OUT_DATA_TYPE := (others => (others => '0')); signal data_rtps_out_s : RTPS_OUT_DATA_TYPE := (others => (others => '0'));
signal last_word_rtps_out_s : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0'); signal last_word_rtps_out_s : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0');
@ -297,24 +297,26 @@ begin
rtps_handler_w_inst : entity Testbench_Lib2.rtps_handler(arch) rtps_handler_w_inst : entity Testbench_Lib2.rtps_handler(arch)
port map ( port map (
clk => clk, -- SYSTEM
reset => reset, clk => clk,
reset => reset,
-- INPUT -- INPUT
empty => empty, empty => empty,
rd => rd, rd => rd,
data_in => data_in, data_in => data_in,
-- TO RTPS BUILTIN ENDPOINT -- TO RTPS BUILTIN ENDPOINT
builtin_full => full_rh(NUM_ENDPOINTS), full_be => full_rh(NUM_ENDPOINTS),
builtin_wr => wr_rh(NUM_ENDPOINTS), wr_be => wr_rh(NUM_ENDPOINTS),
data_out_be => data_out_rh_be_s,
last_word_out_be => last_word_out_rh_be_s,
-- TO RTPS ENDPOINT -- TO RTPS ENDPOINT
user_full => full_rh(0 to NUM_ENDPOINTS-1), full_ue => full_rh(0 to NUM_ENDPOINTS-1),
user_wr => wr_rh(0 to NUM_ENDPOINTS-1), wr_ue => wr_rh(0 to NUM_ENDPOINTS-1),
data_out_ue => data_out_rh_ue_s,
last_word_out => last_word_out_rh_s, last_word_out_ue => last_word_out_rh_ue_s
data_out => data_out_rh_s
); );
data_in_rh <= (others => (last_word_out_rh_s & data_out_rh_s)); data_in_rh <= (NUM_ENDPOINTS => (last_word_out_rh_be_s & data_out_rh_be_s), others => (last_word_out_rh_ue_s & data_out_rh_ue_s));
rtps_out_w_inst : entity Testbench_Lib2.rtps_out(arch) rtps_out_w_inst : entity Testbench_Lib2.rtps_out(arch)
port map ( port map (

32
src/Tests/Level_2/L2_Testbench_Lib3.vhd
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@ -108,8 +108,8 @@ architecture arch of L2_Testbench_Lib3 is
signal last_word_out_rbe : std_logic := '0'; signal last_word_out_rbe : std_logic := '0';
signal data_out_rbe : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); signal data_out_rbe : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal last_word_out_rh_s : std_logic := '0'; signal last_word_out_rh_be_s, last_word_out_rh_ue_s : std_logic := '0';
signal data_out_rh_s : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); signal data_out_rh_be_s, data_out_rh_ue_s : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal data_rtps_out_s : RTPS_OUT_DATA_TYPE := (others => (others => '0')); signal data_rtps_out_s : RTPS_OUT_DATA_TYPE := (others => (others => '0'));
signal last_word_rtps_out_s : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0'); signal last_word_rtps_out_s : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0');
@ -350,24 +350,26 @@ begin
rtps_handler_r_inst : entity Testbench_Lib3.rtps_handler(arch) rtps_handler_r_inst : entity Testbench_Lib3.rtps_handler(arch)
port map ( port map (
clk => clk, -- SYSTEM
reset => reset, clk => clk,
reset => reset,
-- INPUT -- INPUT
empty => empty, empty => empty,
rd => rd, rd => rd,
data_in => data_in, data_in => data_in,
-- TO RTPS BUILTIN ENDPOINT -- TO RTPS BUILTIN ENDPOINT
builtin_full => full_rh(NUM_ENDPOINTS), full_be => full_rh(NUM_ENDPOINTS),
builtin_wr => wr_rh(NUM_ENDPOINTS), wr_be => wr_rh(NUM_ENDPOINTS),
data_out_be => data_out_rh_be_s,
last_word_out_be => last_word_out_rh_be_s,
-- TO RTPS ENDPOINT -- TO RTPS ENDPOINT
user_full => full_rh(0 to NUM_ENDPOINTS-1), full_ue => full_rh(0 to NUM_ENDPOINTS-1),
user_wr => wr_rh(0 to NUM_ENDPOINTS-1), wr_ue => wr_rh(0 to NUM_ENDPOINTS-1),
data_out_ue => data_out_rh_ue_s,
last_word_out => last_word_out_rh_s, last_word_out_ue => last_word_out_rh_ue_s
data_out => data_out_rh_s
); );
data_in_rh <= (others => (last_word_out_rh_s & data_out_rh_s)); data_in_rh <= (NUM_ENDPOINTS => (last_word_out_rh_be_s & data_out_rh_be_s), others => (last_word_out_rh_ue_s & data_out_rh_ue_s));
rtps_out_r_inst : entity Testbench_Lib3.rtps_out(arch) rtps_out_r_inst : entity Testbench_Lib3.rtps_out(arch)
port map ( port map (

323
src/rtps_handler.vhd
View File

@ -9,26 +9,28 @@ use work.rtps_config_package.all;
entity rtps_handler is entity rtps_handler is
port ( port (
clk : in std_logic; -- Input Clock -- SYSTEM
reset : in std_logic; -- Synchronous Reset clk : in std_logic;
empty : in std_logic; -- Input FIFO empty flag reset : in std_logic;
rd : out std_logic; -- Input FIFO read signal -- INPUT
data_in : in std_logic_vector(WORD_WIDTH-1 downto 0); -- Input FIFO data signal empty : in std_logic;
data_out : out std_logic_vector(WORD_WIDTH-1 downto 0); -- Output data signal rd : out std_logic;
builtin_full : in std_logic; -- Output FIFO (Built-In Endpoint) full signal data_in : in std_logic_vector(WORD_WIDTH-1 downto 0);
builtin_wr : out std_logic; -- Output FIFO (Built-In Endpoint) write signal -- TO BUILTIN ENDPOINT
user_full : in std_logic_vector(0 to NUM_ENDPOINTS-1); -- Output FIFO (User Endpoints) full signal full_be : in std_logic;
user_wr : out std_logic_vector(0 to NUM_ENDPOINTS-1); -- Output FIFO (User Endpoints) write signal wr_be : out std_logic;
last_word_out : out std_logic -- Output FIFO Last Word signal data_out_be : out std_logic_vector(WORD_WIDTH-1 downto 0);
last_word_out_be : out std_logic;
-- TO USER ENDPOINTS
data_out_ue : out std_logic_vector(WORD_WIDTH-1 downto 0); -- one-to-many (Multicast) Connection
full_ue : in std_logic_vector(0 to NUM_ENDPOINTS-1);
wr_ue : out std_logic_vector(0 to NUM_ENDPOINTS-1);
last_word_out_ue : out std_logic -- one-to-many (Multicast) Connection
); );
end entity; end entity;
architecture arch of rtps_handler is architecture arch of rtps_handler is
--*****COMPONENT DECLARATION******
--*****CONSTANT DECLARATION*****
--*****TYPE DECLARATION***** --*****TYPE DECLARATION*****
-- FSM states. Explained below in detail -- FSM states. Explained below in detail
type STAGE_TYPE is (SRC_ADDR_HEADER, DEST_ADDR_HEADER, UDP_PORT_HEADER, LEN_HEADER, RTPS_HEADER_1, RTPS_HEADER_2, type STAGE_TYPE is (SRC_ADDR_HEADER, DEST_ADDR_HEADER, UDP_PORT_HEADER, LEN_HEADER, RTPS_HEADER_1, RTPS_HEADER_2,
@ -82,7 +84,7 @@ architecture arch of rtps_handler is
-- Source GUID Prefix latch -- Source GUID Prefix latch
signal src_guidprefix, src_guidprefix_next : GUIDPREFIX_TYPE := (others => (others => '0')); signal src_guidprefix, src_guidprefix_next : GUIDPREFIX_TYPE := (others => (others => '0'));
-- Vector denoting the Destination User Endpoints of the Submessage -- Vector denoting the Destination User Endpoints of the Submessage
signal user_endpoint, user_endpoint_next : std_logic_vector(0 to NUM_ENDPOINTS-1) := (others => '0'); signal user_endpoints, user_endpoints_next : std_logic_vector(0 to NUM_ENDPOINTS-1) := (others => '0');
-- Denotes if the Message is destined for the Built-in Endpoints -- Denotes if the Message is destined for the Built-in Endpoints
signal builtin_endpoint, builtin_endpoint_next : std_logic := '0'; signal builtin_endpoint, builtin_endpoint_next : std_logic := '0';
-- LocatorList NumLocator latch -- LocatorList NumLocator latch
@ -122,6 +124,10 @@ architecture arch of rtps_handler is
signal ip_addr_type, ip_addr_type_next : IPv4_ADDRESS_TYPE := INVALID; signal ip_addr_type, ip_addr_type_next : IPv4_ADDRESS_TYPE := INVALID;
-- Alias "substitution" -- Alias "substitution"
signal rtps_sub_length, rtps_sub_data_length : unsigned(SUBMESSAGE_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal rtps_sub_length, rtps_sub_data_length : unsigned(SUBMESSAGE_LENGTH_WIDTH-1 downto 0) := (others => '0');
-- Internal Signal for data_out
signal data_out_sig : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
-- Internal Signal for last_word_out
signal last_word_out_sig : std_logic := '0';
--*****ALIAS DEFINATION***** --*****ALIAS DEFINATION*****
-- UDP HEADER -- UDP HEADER
@ -139,8 +145,6 @@ architecture arch of rtps_handler is
-- Apparently illegal alias expression -- Apparently illegal alias expression
--alias rtps_sub_data_length : unsigned(15 downto 0) is unsigned(endian_swap(flags(SUBMESSAGE_ENDIAN_FLAG_POS), data_in(15 downto 0))); --alias rtps_sub_data_length : unsigned(15 downto 0) is unsigned(endian_swap(flags(SUBMESSAGE_ENDIAN_FLAG_POS), data_in(15 downto 0)));
--*****FUNCTION DECLARATION*****
begin begin
-- ALIAS SUBSTITUTION -- ALIAS SUBSTITUTION
@ -156,17 +160,22 @@ begin
output_prc : process(all) output_prc : process(all)
begin begin
--Write Enable Signal --Write Enable Signal
builtin_wr <= '0'; wr_be <= '0';
user_wr <= (others => '0'); wr_ue <= (others => '0');
if (wr_sig = '1') then if (wr_sig = '1') then
if (builtin_endpoint = '1') then if (builtin_endpoint = '1') then
builtin_wr <= '1'; wr_be <= '1';
else else
user_wr <= user_endpoint; wr_ue <= user_endpoints;
end if; end if;
end if; end if;
end process; end process;
data_out_be <= data_out_sig;
data_out_ue <= data_out_sig;
last_word_out_be <= last_word_out_sig;
last_word_out_ue <= last_word_out_sig;
-- This process is responsible for reading the input FIFO 4-Byte Word aligned. -- This process is responsible for reading the input FIFO 4-Byte Word aligned.
-- Even though DDSI-RTPS 2.3 defines that Submessages begin at 4-byte boundries, meaning that the -- Even though DDSI-RTPS 2.3 defines that Submessages begin at 4-byte boundries, meaning that the
-- submessage length is always a multiple of 4, the same is not defined for the "octetstoinlineQoS". -- submessage length is always a multiple of 4, the same is not defined for the "octetstoinlineQoS".
@ -223,44 +232,44 @@ begin
variable rd_guard : std_logic := '0'; variable rd_guard : std_logic := '0';
begin begin
--DEFAULT Registered --DEFAULT Registered
stage_next <= stage; stage_next <= stage;
cnt_next <= cnt; cnt_next <= cnt;
align_offset_next <= align_offset; align_offset_next <= align_offset;
align_sig_next <= align_sig; align_sig_next <= align_sig;
packet_length_next <= packet_length; packet_length_next <= packet_length;
sub_end_next <= sub_end; sub_end_next <= sub_end;
offset_latch_next <= offset_latch; offset_latch_next <= offset_latch;
src_addr_next <= src_addr; src_addr_next <= src_addr;
src_port_next <= src_port; src_port_next <= src_port;
flags_next <= flags; flags_next <= flags;
src_entityid_next <= src_entityid; src_entityid_next <= src_entityid;
src_guidprefix_next <= src_guidprefix; src_guidprefix_next <= src_guidprefix;
dest_entityid_next <= dest_entityid; dest_entityid_next <= dest_entityid;
user_endpoint_next <= user_endpoint; user_endpoints_next <= user_endpoints;
builtin_endpoint_next <= builtin_endpoint; builtin_endpoint_next <= builtin_endpoint;
numlocators_next <= numlocators; numlocators_next <= numlocators;
opcode_next <= opcode; opcode_next <= opcode;
data_header_end_next <= data_header_end; data_header_end_next <= data_header_end;
locator_match_next <= locator_match; locator_match_next <= locator_match;
is_metatraffic_next <= is_metatraffic; is_metatraffic_next <= is_metatraffic;
src_is_reader_next <= src_is_reader; src_is_reader_next <= src_is_reader;
sn_latch_1_next <= sn_latch_1; sn_latch_1_next <= sn_latch_1;
sn_latch_2_next <= sn_latch_2; sn_latch_2_next <= sn_latch_2;
sn_latch_3_next <= sn_latch_3; sn_latch_3_next <= sn_latch_3;
long_latch_next <= long_latch; long_latch_next <= long_latch;
ulong_latch_next <= ulong_latch; ulong_latch_next <= ulong_latch;
bitmap_latch_next <= bitmap_latch; bitmap_latch_next <= bitmap_latch;
cnt2_next <= cnt2; cnt2_next <= cnt2;
bitmap_cnt_next <= bitmap_cnt; bitmap_cnt_next <= bitmap_cnt;
src_ts_next <= src_ts; src_ts_next <= src_ts;
ip_addr_type_next <= ip_addr_type; ip_addr_type_next <= ip_addr_type;
-- DEFAULT Unregistered -- DEFAULT Unregistered
data_out <= (others => '0'); data_out_sig <= (others => '0');
rd_sig <= '0'; rd_sig <= '0';
rd_guard := '0'; rd_guard := '0';
reset_read_cnt <= '0'; reset_read_cnt <= '0';
wr_sig <= '0'; wr_sig <= '0';
last_word_out <= '0'; last_word_out_sig <= '0';
case(stage) is case(stage) is
-- Initial/Idle State -- Initial/Idle State
@ -968,7 +977,7 @@ begin
end if; end if;
when MATCH_DST_ENDPOINT => when MATCH_DST_ENDPOINT =>
-- DEFAULT -- DEFAULT
user_endpoint_next <= (others => '0'); user_endpoints_next <= (others => '0');
builtin_endpoint_next <= '0'; builtin_endpoint_next <= '0';
stage_next <= PUSH_PAYLOAD_HEADER; stage_next <= PUSH_PAYLOAD_HEADER;
cnt_next <= 0; cnt_next <= 0;
@ -981,10 +990,10 @@ begin
else else
-- Mark Only Writers -- Mark Only Writers
if (src_is_reader = '1' and NUM_WRITERS /= 0) then if (src_is_reader = '1' and NUM_WRITERS /= 0) then
user_endpoint_next <= not ENDPOINT_READERS; user_endpoints_next <= not ENDPOINT_READERS;
-- Mark Only Readers -- Mark Only Readers
elsif (NUM_READERS /= 0) then elsif (NUM_READERS /= 0) then
user_endpoint_next <= ENDPOINT_READERS; user_endpoints_next <= ENDPOINT_READERS;
end if; end if;
end if; end if;
-- Target Built-In Endpoints -- Target Built-In Endpoints
@ -1009,10 +1018,10 @@ begin
-- SANITY CHECK: Allow only Reader-Writer Communication -- SANITY CHECK: Allow only Reader-Writer Communication
if (src_is_reader = '1') then if (src_is_reader = '1') then
-- Mark only Writers -- Mark only Writers
user_endpoint_next <= tmp and (not ENDPOINT_READERS); user_endpoints_next <= tmp and (not ENDPOINT_READERS);
else else
-- Mark only Readers -- Mark only Readers
user_endpoint_next <= tmp and ENDPOINT_READERS; user_endpoints_next <= tmp and ENDPOINT_READERS;
end if; end if;
end if; end if;
-- Destination Unreachable, skip Submessage -- Destination Unreachable, skip Submessage
@ -1022,72 +1031,72 @@ begin
when PUSH_PAYLOAD_HEADER => when PUSH_PAYLOAD_HEADER =>
-- NOTE: This is a synchronised push on potentially multiple output FIFOs. If one FIFO gets full, the process stalls for all FIFOs. -- NOTE: This is a synchronised push on potentially multiple output FIFOs. If one FIFO gets full, the process stalls for all FIFOs.
-- Output FIFO Guard -- Output FIFO Guard
if (builtin_endpoint = '1' and builtin_full = '0') or (builtin_endpoint = '0' and ((user_endpoint and user_full) = (user_endpoint'range => '0'))) then if (builtin_endpoint = '1' and full_be = '0') or (builtin_endpoint = '0' and ((user_endpoints and full_ue) = (user_endpoints'range => '0'))) then
case (cnt) is case (cnt) is
-- OPCODE (Submessage ID), Submessage Flags, UPDv4 Source Port -- OPCODE (Submessage ID), Submessage Flags, UPDv4 Source Port
when 0 => when 0 =>
data_out <= opcode & flags & src_port; data_out_sig <= opcode & flags & src_port;
wr_sig <= '1'; wr_sig <= '1';
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
-- IPv4 Source Address -- IPv4 Source Address
when 1 => when 1 =>
data_out <= src_addr; data_out_sig <= src_addr;
wr_sig <= '1'; wr_sig <= '1';
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
-- GUID Prefix 1/3 -- GUID Prefix 1/3
when 2 => when 2 =>
data_out <= src_guidprefix(0); data_out_sig <= src_guidprefix(0);
wr_sig <= '1'; wr_sig <= '1';
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
-- GUID Prefix 2/3 -- GUID Prefix 2/3
when 3 => when 3 =>
data_out <= src_guidprefix(1); data_out_sig <= src_guidprefix(1);
wr_sig <= '1'; wr_sig <= '1';
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
-- GUID Prefix 3/3 -- GUID Prefix 3/3
when 4 => when 4 =>
data_out <= src_guidprefix(2); data_out_sig <= src_guidprefix(2);
wr_sig <= '1'; wr_sig <= '1';
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
-- Source Entity ID -- Source Entity ID
when 5 => when 5 =>
data_out <= src_entityid; data_out_sig <= src_entityid;
wr_sig <= '1'; wr_sig <= '1';
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
-- Destination ID [only for Built-in Endpoints] -- Destination ID [only for Built-in Endpoints]
when 6 => when 6 =>
if (builtin_endpoint = '1') then if (builtin_endpoint = '1') then
data_out <= dest_entityid; data_out_sig <= dest_entityid;
wr_sig <= '1'; wr_sig <= '1';
end if; end if;
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
-- Sequence Number 1/2 [only for DATA Submessages] -- Sequence Number 1/2 [only for DATA Submessages]
when 7 => when 7 =>
if (opcode = SID_DATA) then if (opcode = SID_DATA) then
data_out <= std_logic_vector(sn_latch_1(0)); data_out_sig <= std_logic_vector(sn_latch_1(0));
wr_sig <= '1'; wr_sig <= '1';
end if; end if;
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
-- Sequence Number 2/2 [only for DATA Submessages] -- Sequence Number 2/2 [only for DATA Submessages]
when 8 => when 8 =>
if (opcode = SID_DATA) then if (opcode = SID_DATA) then
data_out <= std_logic_vector(sn_latch_1(1)); data_out_sig <= std_logic_vector(sn_latch_1(1));
wr_sig <= '1'; wr_sig <= '1';
end if; end if;
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
-- Source Timestamp 1/2 [only for DATA Submessages and User Endpoints] -- Source Timestamp 1/2 [only for DATA Submessages and User Endpoints]
when 9 => when 9 =>
if (opcode = SID_DATA and builtin_endpoint = '0') then if (opcode = SID_DATA and builtin_endpoint = '0') then
data_out <= std_logic_vector(src_ts(0)); data_out_sig <= std_logic_vector(src_ts(0));
wr_sig <= '1'; wr_sig <= '1';
end if; end if;
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
-- Source Timestamp 1/2 [only for DATA Submessages and User Endpoints] -- Source Timestamp 1/2 [only for DATA Submessages and User Endpoints]
when 10 => when 10 =>
if (opcode = SID_DATA and builtin_endpoint = '0') then if (opcode = SID_DATA and builtin_endpoint = '0') then
data_out <= std_logic_vector(src_ts(1)); data_out_sig <= std_logic_vector(src_ts(1));
wr_sig <= '1'; wr_sig <= '1';
end if; end if;
stage_next <= PUSH_PAYLOAD; stage_next <= PUSH_PAYLOAD;
@ -1099,36 +1108,36 @@ begin
when PUSH_PAYLOAD => when PUSH_PAYLOAD =>
-- NOTE: This is a synchronised push on potentially multiple output FIFOs. If one FIFO gets full, the process stalls for all FIFOs. -- NOTE: This is a synchronised push on potentially multiple output FIFOs. If one FIFO gets full, the process stalls for all FIFOs.
-- Output FIFO Guard -- Output FIFO Guard
if (builtin_endpoint = '1' and builtin_full = '0') or (builtin_endpoint = '0' and ((user_endpoint and user_full) = (user_endpoint'range => '0'))) then if (builtin_endpoint = '1' and full_be = '0') or (builtin_endpoint = '0' and ((user_endpoints and full_ue) = (user_endpoints'range => '0'))) then
case (opcode) is case (opcode) is
when SID_HEARTBEAT => when SID_HEARTBEAT =>
case (cnt) is case (cnt) is
-- FirstSN 1/2 -- FirstSN 1/2
when 0 => when 0 =>
data_out <= std_logic_vector(sn_latch_1(0)); data_out_sig <= std_logic_vector(sn_latch_1(0));
wr_sig <= '1'; wr_sig <= '1';
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
-- FirstSN 2/2 -- FirstSN 2/2
when 1 => when 1 =>
data_out <= std_logic_vector(sn_latch_1(1)); data_out_sig <= std_logic_vector(sn_latch_1(1));
wr_sig <= '1'; wr_sig <= '1';
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
-- LastSN 1/2 -- LastSN 1/2
when 2 => when 2 =>
data_out <= std_logic_vector(sn_latch_2(0)); data_out_sig <= std_logic_vector(sn_latch_2(0));
wr_sig <= '1'; wr_sig <= '1';
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
-- LastSN 2/2 -- LastSN 2/2
when 3 => when 3 =>
data_out <= std_logic_vector(sn_latch_2(1)); data_out_sig <= std_logic_vector(sn_latch_2(1));
wr_sig <= '1'; wr_sig <= '1';
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
-- Count -- Count
when 4 => when 4 =>
data_out <= long_latch; data_out_sig <= long_latch;
wr_sig <= '1'; wr_sig <= '1';
last_word_out <= '1'; last_word_out_sig <= '1';
-- DONE -- DONE
stage_next <= SKIP_SUB; stage_next <= SKIP_SUB;
@ -1139,36 +1148,36 @@ begin
case (cnt) is case (cnt) is
-- ReaderSNState.Base 1/2 -- ReaderSNState.Base 1/2
when 0 => when 0 =>
data_out <= std_logic_vector(sn_latch_1(0)); data_out_sig <= std_logic_vector(sn_latch_1(0));
wr_sig <= '1'; wr_sig <= '1';
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
-- ReaderSNState.Base 2/2 -- ReaderSNState.Base 2/2
when 1 => when 1 =>
data_out <= std_logic_vector(sn_latch_1(1)); data_out_sig <= std_logic_vector(sn_latch_1(1));
wr_sig <= '1'; wr_sig <= '1';
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
-- ReaderSNState.NumBits -- ReaderSNState.NumBits
when 2 => when 2 =>
data_out <= std_logic_vector(ulong_latch); data_out_sig <= std_logic_vector(ulong_latch);
wr_sig <= '1'; wr_sig <= '1';
cnt2_next <= 0; cnt2_next <= 0;
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
-- ReaderSNState.Bitmap -- ReaderSNState.Bitmap
when 3 => when 3 =>
-- Write Bitmap -- Write Bitmap
if (cnt2 < bitmap_cnt) then if (cnt2 < bitmap_cnt) then
cnt2_next <= cnt2 + 1; cnt2_next <= cnt2 + 1;
data_out <= bitmap_latch_next(cnt2); data_out_sig <= bitmap_latch_next(cnt2);
wr_sig <= '1'; wr_sig <= '1';
else else
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
end if; end if;
-- Count -- Count
when 4 => when 4 =>
data_out <= long_latch; data_out_sig <= long_latch;
wr_sig <= '1'; wr_sig <= '1';
last_word_out <= '1'; last_word_out_sig <= '1';
-- DONE -- DONE
stage_next <= SKIP_SUB; stage_next <= SKIP_SUB;
@ -1179,49 +1188,49 @@ begin
case (cnt) is case (cnt) is
-- GapStart 1/2 -- GapStart 1/2
when 0 => when 0 =>
data_out <= std_logic_vector(sn_latch_1(0)); data_out_sig <= std_logic_vector(sn_latch_1(0));
wr_sig <= '1'; wr_sig <= '1';
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
-- GapStart 2/2 -- GapStart 2/2
when 1 => when 1 =>
data_out <= std_logic_vector(sn_latch_1(1)); data_out_sig <= std_logic_vector(sn_latch_1(1));
wr_sig <= '1'; wr_sig <= '1';
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
-- GapList.Base 1/2 -- GapList.Base 1/2
when 2 => when 2 =>
data_out <= std_logic_vector(sn_latch_2(0)); data_out_sig <= std_logic_vector(sn_latch_2(0));
wr_sig <= '1'; wr_sig <= '1';
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
-- GapList.Base 2/2 -- GapList.Base 2/2
when 3 => when 3 =>
data_out <= std_logic_vector(sn_latch_2(1)); data_out_sig <= std_logic_vector(sn_latch_2(1));
wr_sig <= '1'; wr_sig <= '1';
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
-- GapList.NumBits -- GapList.NumBits
when 4 => when 4 =>
data_out <= std_logic_vector(ulong_latch); data_out_sig <= std_logic_vector(ulong_latch);
wr_sig <= '1'; wr_sig <= '1';
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
cnt2_next <= 0; cnt2_next <= 0;
-- GapList.Bitmap -- GapList.Bitmap
when 5 => when 5 =>
-- Write Bitmap -- Write Bitmap
if (cnt2 < bitmap_cnt) then if (cnt2 < bitmap_cnt) then
cnt2_next <= cnt2 + 1; cnt2_next <= cnt2 + 1;
data_out <= bitmap_latch_next(cnt2); data_out_sig <= bitmap_latch_next(cnt2);
wr_sig <= '1'; wr_sig <= '1';
else else
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
end if; end if;
-- NOTE: Because we need to pull "last_word_out" high on the last Byte, and doing so in the last Byte of Bitmap was deemed -- NOTE: Because we need to pull "last_word_out_sig" high on the last Byte, and doing so in the last Byte of Bitmap was deemed
-- to much overhead (We need a counter in addition to cnt2 to track the next-to-last Byte of the Bitmap), we just -- to much overhead (We need a counter in addition to cnt2 to track the next-to-last Byte of the Bitmap), we just
-- define the Frame with an additional dummy word in the end. -- define the Frame with an additional dummy word in the end.
-- UNUSED -- UNUSED
when 6 => when 6 =>
data_out <= (others => '0'); data_out_sig <= (others => '0');
wr_sig <= '1'; wr_sig <= '1';
last_word_out <= '1'; last_word_out_sig <= '1';
-- DONE -- DONE
stage_next <= SKIP_SUB; stage_next <= SKIP_SUB;
@ -1245,11 +1254,11 @@ begin
align_sig_next <= data_in(23 downto 0); align_sig_next <= data_in(23 downto 0);
-- Push Payload -- Push Payload
data_out <= data_in_aligned; data_out_sig <= data_in_aligned;
wr_sig <= '1'; wr_sig <= '1';
if (read_cnt_plus = sub_end) then if (read_cnt_plus = sub_end) then
last_word_out <= '1'; last_word_out_sig <= '1';
-- Begin parsing of next submessage -- Begin parsing of next submessage
stage_next <= RTPS_SUB_HEADER; stage_next <= RTPS_SUB_HEADER;
-- Reset alignement -- Reset alignement
@ -1310,7 +1319,7 @@ begin
-- Force rd_sig low -- Force rd_sig low
rd_sig <= '0'; rd_sig <= '0';
-- Notify Endpoints of EOP -- Notify Endpoints of EOP
last_word_out <= '1'; last_word_out_sig <= '1';
-- Continue parsing next Packet -- Continue parsing next Packet
stage_next <= SRC_ADDR_HEADER; stage_next <= SRC_ADDR_HEADER;
-- Reset Lengths -- Reset Lengths
@ -1322,16 +1331,16 @@ begin
-- The SKIP_SUB clause prevents a read signal from occuring in this situation, and thus prevents from entering this state. -- The SKIP_SUB clause prevents a read signal from occuring in this situation, and thus prevents from entering this state.
elsif (read_cnt = sub_end and rd_guard = '1') then elsif (read_cnt = sub_end and rd_guard = '1') then
-- Force rd_sig low -- Force rd_sig low
rd_sig <= '0'; rd_sig <= '0';
-- Notify Endpoints of EOS -- Notify Endpoints of EOS
last_word_out <= '1'; last_word_out_sig <= '1';
-- Invalid Submessage Length Field, Skip Packet (see DDSI-RTPS 2.3 Section 8.3.4.1) -- Invalid Submessage Length Field, Skip Packet (see DDSI-RTPS 2.3 Section 8.3.4.1)
stage_next <= SKIP_PACKET; stage_next <= SKIP_PACKET;
-- Reset Submessage End -- Reset Submessage End
sub_end_next <= (others => '1'); sub_end_next <= (others => '1');
-- DEFAULT -- DEFAULT
else else
rd_sig <= rd_guard; rd_sig <= rd_guard;
end if; end if;
end process; end process;
@ -1368,7 +1377,7 @@ begin
flags <= (others => '0'); flags <= (others => '0');
src_entityid <= (others => '0'); src_entityid <= (others => '0');
dest_entityid <= (others => '0'); dest_entityid <= (others => '0');
user_endpoint <= (others => '0'); user_endpoints <= (others => '0');
numlocators <= (others => '0'); numlocators <= (others => '0');
opcode <= (others => '0'); opcode <= (others => '0');
data_header_end <= (others => '0'); data_header_end <= (others => '0');
@ -1400,7 +1409,7 @@ begin
flags <= flags_next; flags <= flags_next;
src_entityid <= src_entityid_next; src_entityid <= src_entityid_next;
dest_entityid <= dest_entityid_next; dest_entityid <= dest_entityid_next;
user_endpoint <= user_endpoint_next; user_endpoints <= user_endpoints_next;
numlocators <= numlocators_next; numlocators <= numlocators_next;
opcode <= opcode_next; opcode <= opcode_next;
data_header_end <= data_header_end_next; data_header_end <= data_header_end_next;