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Fix Bug in Key Holder

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The Key Holder was sending only the 1st Byte of 4-Byte Key Fields.
This commit is contained in:
Greek 2021-12-06 16:38:04 +01:00
parent ddc331d9ba
commit 4420a62d63
3 changed files with 21 additions and 6 deletions
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7
src/TEMPLATE_key_holder.vhd
View File

@ -99,6 +99,7 @@ begin
main_prc : process (all)
variable tmp_length : unsigned(WORD_WIDTH-1 downto 0);
variable cnt2_ref : std_logic_vector(1 downto 0);
begin
-- DEFAULT
stage_next <= stage;
@ -344,8 +345,10 @@ begin
when PUSH =>
-- Push to Key Hash Generator
if (opcode_latch = READ_KEY_HASH) then
-- XXX: Assumes data_out_latch is 32 bits (TODO)
cnt2_ref := std_logic_vector(unsigned(align_offset(1 downto 0)) - to_unsigned(1,2));
-- Mark Last Word
if (finalize_payload = '1' and cnt_2 = to_integer(unsigned(align_offset(1 downto 0)))) then
if (finalize_payload = '1' and cnt_2 = to_integer(unsigned(cnt2_ref))) then
last_word_in_kh <= '1';
end if;
@ -354,7 +357,7 @@ begin
-- Output Guard
if (ready_in_kh = '1') then
-- Last Byte
if ((finalize_payload = '1' and cnt_2 = to_integer(unsigned(align_offset(1 downto 0)))) or cnt_2 = (WORD_WIDTH/BYTE_WIDTH)-1) then
if (cnt_2 = to_integer(unsigned(cnt2_ref))) then
-- Reset
cnt_2_next <= 0;
-- Alignment Operation in process

10
src/Tests/Type1_key_holder.vhd
View File

@ -1,3 +1,6 @@
-- altera vhdl_input_version vhdl_2008
-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
@ -92,6 +95,7 @@ begin
main_prc : process (all)
variable tmp_length : unsigned(WORD_WIDTH-1 downto 0);
variable cnt2_ref : std_logic_vector(1 downto 0);
begin
-- DEFAULT
stage_next <= stage;
@ -348,8 +352,10 @@ begin
when PUSH =>
-- Push to Key Hash Generator
if (opcode_latch = READ_KEY_HASH) then
-- XXX: Assumes data_out_latch is 32 bits (TODO)
cnt2_ref := std_logic_vector(unsigned(align_offset(1 downto 0)) - to_unsigned(1,2));
-- Mark Last Word
if (finalize_payload = '1' and cnt_2 = to_integer(unsigned(align_offset(1 downto 0)))) then
if (finalize_payload = '1' and cnt_2 = to_integer(unsigned(cnt2_ref))) then
last_word_in_kh <= '1';
end if;
@ -358,7 +364,7 @@ begin
-- Output Guard
if (ready_in_kh = '1') then
-- Last Byte
if ((finalize_payload = '1' and cnt_2 = to_integer(unsigned(align_offset(1 downto 0)))) or cnt_2 = (WORD_WIDTH/BYTE_WIDTH)-1) then
if (cnt_2 = to_integer(unsigned(cnt2_ref))) then
-- Reset
cnt_2_next <= 0;
-- Alignment Operation in process

10
src/Tests/Type2_key_holder.vhd
View File

@ -1,3 +1,6 @@
-- altera vhdl_input_version vhdl_2008
-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
@ -127,6 +130,7 @@ begin
main_prc : process (all)
variable tmp_length : unsigned(WORD_WIDTH-1 downto 0);
variable cnt2_ref : std_logic_vector(1 downto 0);
begin
-- DEFAULT
stage_next <= stage;
@ -548,8 +552,10 @@ begin
when PUSH =>
-- Push to Key Hash Generator
if (opcode_latch = READ_KEY_HASH) then
-- XXX: Assumes data_out_latch is 32 bits (TODO)
cnt2_ref := std_logic_vector(unsigned(align_offset(1 downto 0)) - to_unsigned(1,2));
-- Mark Last Word
if (finalize_payload = '1' and cnt_2 = to_integer(unsigned(align_offset(1 downto 0)))) then
if (finalize_payload = '1' and cnt_2 = to_integer(unsigned(cnt2_ref))) then
last_word_in_kh <= '1';
end if;
@ -558,7 +564,7 @@ begin
-- Output Guard
if (ready_in_kh = '1') then
-- Last Byte
if ((finalize_payload = '1' and cnt_2 = to_integer(unsigned(align_offset(1 downto 0)))) or cnt_2 = (WORD_WIDTH/BYTE_WIDTH)-1) then
if (cnt_2 = to_integer(unsigned(cnt2_ref))) then
-- Reset
cnt_2_next <= 0;
-- Alignment Operation in process