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code refactoring

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Greek 2021-12-08 12:01:16 +01:00
parent 3e387b9513
commit 4896929e1b
3 changed files with 5 additions and 7 deletions
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1
src/Tests/Level_2/L2_testbench_Lib4.vhd
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@ -8,7 +8,6 @@ use ieee.numeric_std.all;
use work.rtps_package.all; use work.rtps_package.all;
use work.user_config.all; use work.user_config.all;
use work.rtps_config_package.all; use work.rtps_config_package.all;
use work.rtps_test_package.all;
use work.Type1_package.all; use work.Type1_package.all;
entity L2_Testbench_Lib4 is entity L2_Testbench_Lib4 is

9
src/Tests/test_loopback.vhd
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@ -7,7 +7,6 @@ use ieee.numeric_std.all;
use work.rtps_package.all; use work.rtps_package.all;
use work.rtps_config_package.all; use work.rtps_config_package.all;
use work.rtps_test_package.all;
entity test_loopback is entity test_loopback is
port ( port (
@ -106,7 +105,7 @@ begin
case (stage) is case (stage) is
-- Get the Instance Handle for the target Topic Instance -- Get the Instance Handle for the target Topic Instance
when INITIALIZE => when INITIALIZE =>
id_w <= int(1, CDR_LONG_WIDTH); id_w <= std_logic_vector(to_unsigned(1, CDR_LONG_WIDTH));
case (cnt) is case (cnt) is
when 0 => when 0 =>
start_w <= '1'; start_w <= '1';
@ -161,7 +160,7 @@ begin
end if; end if;
when 3 => when 3 =>
if (valid_r = '1') then if (valid_r = '1') then
assert (id_r = int(1,CDR_LONG_WIDTH)) severity FAILURE; assert (id_r = std_logic_vector(to_unsigned(1,CDR_LONG_WIDTH))) severity FAILURE;
long_next <= a_r; long_next <= a_r;
stage_next <= PROCESS_MESSAGE; stage_next <= PROCESS_MESSAGE;
end if; end if;
@ -170,11 +169,11 @@ begin
end case; end case;
when PROCESS_MESSAGE => when PROCESS_MESSAGE =>
-- Add 1k to Message -- Add 1k to Message
long_next <= std_logic_vector(unsigned(long) + unsigned(int(1000, CDR_LONG_WIDTH))); long_next <= std_logic_vector(unsigned(long) + to_unsigned(1000, CDR_LONG_WIDTH));
stage_next <= WRITE; stage_next <= WRITE;
cnt_next <= 0; cnt_next <= 0;
when WRITE => when WRITE =>
id_w <= int(2, CDR_LONG_WIDTH); id_w <= std_logic_vector(to_unsigned(2, CDR_LONG_WIDTH));
a_w <= long; a_w <= long;
case (cnt) is case (cnt) is
when 0 => when 0 =>

2
src/mem_ctrl.vhd
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@ -84,7 +84,7 @@ begin
elsif ((ready_in_sig and valid_in and read) = '0' and delay_line(1) = '1') then elsif ((ready_in_sig and valid_in and read) = '0' and delay_line(1) = '1') then
delay_cnt <= delay_cnt - 1; delay_cnt <= delay_cnt - 1;
end if; end if;
else else -- READ_LATENCY = 1
delay_line(0) <= ready_in_sig and valid_in and read; delay_line(0) <= ready_in_sig and valid_in and read;
if ((ready_in_sig and valid_in and read) = '1' and delay_line(0) = '0') then if ((ready_in_sig and valid_in and read) = '1' and delay_line(0) = '0') then