Add UDP loopback in De10-Nano GHRD Project and generate output files

The UDP loopback just reads from the input FIFO, reverses src and destination
addresses, and writes back to the output FIFO.
This can be used to measure the throughput of the HPS-FPGA communication

syn/DE10-Nano/top.qsf

@@ -53,8 +53,10 @@ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 
+
 set_global_assignment -name SDC_FILE top.sdc
 set_global_assignment -name VHDL_FILE ../test_top.vhd -hdl_version VHDL_2008
+set_global_assignment -name VHDL_FILE ../loopback.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib6.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/ros2/Tests/test_loopback_util.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/ros2/Tests/Type1_ros_pub.vhd -hdl_version VHDL_2008
@@ -141,5 +143,4 @@ set_global_assignment -name VHDL_FILE ../../src/ros2/rcl_interfaces/action_msgs/
 set_global_assignment -name VHDL_FILE ../../src/ros2/ros_package.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/rtps_package.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../src/math_pkg.vhd -hdl_version VHDL_2008
-
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

syn/DE10_NANO_SoC_GHRD/test_fpga_hw.tcl

@@ -1,11 +1,11 @@
 # TCL File Generated by Component Editor 21.1
-# Sun Jul 23 18:44:32 GMT+02:00 2023
+# Thu Jul 27 13:57:40 GMT+02:00 2023
 # DO NOT MODIFY
 
 
 # 
 # test_fpga "test_fpga" v1.0
-#  2023.07.23.18:44:32
+#  2023.07.27.13:57:40
 # Test PL-PS Communication
 # 
 
@@ -40,49 +40,15 @@ set_fileset_property QUARTUS_SYNTH TOP_LEVEL test_top
 set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
 set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
 add_fileset_file test_top.vhd VHDL PATH ../test_top.vhd TOP_LEVEL_FILE
-add_fileset_file math_pkg.vhd VHDL PATH ../../src/math_pkg.vhd
-add_fileset_file rtps_package.vhd VHDL PATH ../../src/rtps_package.vhd
-add_fileset_file ros_package.vhd VHDL PATH ../../src/ros2/ros_package.vhd
-add_fileset_file Type1_package.vhd VHDL PATH ../../src/ros2/Tests/Type1_package.vhd
-add_fileset_file Type1_ros_pub.vhd VHDL PATH ../../src/ros2/Tests/Type1_ros_pub.vhd
-add_fileset_file Type1_ros_sub.vhd VHDL PATH ../../src/ros2/Tests/Type1_ros_sub.vhd
-add_fileset_file test_loopback_util.vhd VHDL PATH ../../src/ros2/Tests/test_loopback_util.vhd
-add_fileset_file L2_Testbench_ROS_Lib6.vhd VHDL PATH ../../src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib6.vhd
 add_fileset_file FWFT_FIFO.vhd VHDL PATH ../../src/FWFT_FIFO.vhd
 add_fileset_file FWFT_FIFO_Altera.vhd VHDL PATH ../../src/FWFT_FIFO_Altera.vhd
 add_fileset_file FWFT_FIFO_cfg.vhd VHDL PATH ../../src/FWFT_FIFO_cfg.vhd
-add_fileset_file dds_reader.vhd VHDL PATH ../../src/dds_reader.vhd
-add_fileset_file dds_writer.vhd VHDL PATH ../../src/dds_writer.vhd
-add_fileset_file dp_mem_ctrl.vhd VHDL PATH ../../src/dp_mem_ctrl.vhd
-add_fileset_file dual_port_ram.vhd VHDL PATH ../../src/dual_port_ram.vhd
-add_fileset_file dual_port_ram_Altera.vhd VHDL PATH ../../src/dual_port_ram_Altera.vhd
-add_fileset_file dual_port_ram_cfg.vhd VHDL PATH ../../src/dual_port_ram_cfg.vhd
-add_fileset_file mem_ctrl.vhd VHDL PATH ../../src/mem_ctrl.vhd
-add_fileset_file moving_average.vhd VHDL PATH ../../src/moving_average.vhd
-add_fileset_file moving_average_wrapper.vhd VHDL PATH ../../src/moving_average_wrapper.vhd
-add_fileset_file mult.vhd VHDL PATH ../../src/mult.vhd
-add_fileset_file mult_Altera.vhd VHDL PATH ../../src/mult_Altera.vhd
-add_fileset_file mult_cfg.vhd VHDL PATH ../../src/mult_cfg.vhd
-add_fileset_file rtps_config_package.vhd VHDL PATH ../../src/rtps_config_package.vhd
-add_fileset_file rtps_discovery_module.vhd VHDL PATH ../../src/rtps_discovery_module.vhd
-add_fileset_file rtps_handler.vhd VHDL PATH ../../src/rtps_handler.vhd
-add_fileset_file rtps_out.vhd VHDL PATH ../../src/rtps_out.vhd
-add_fileset_file rtps_reader.vhd VHDL PATH ../../src/rtps_reader.vhd
-add_fileset_file rtps_writer.vhd VHDL PATH ../../src/rtps_writer.vhd
-add_fileset_file single_port_ram.vhd VHDL PATH ../../src/single_port_ram.vhd
-add_fileset_file single_port_ram_Altera.vhd VHDL PATH ../../src/single_port_ram_Altera.vhd
-add_fileset_file single_port_ram_cfg.vhd VHDL PATH ../../src/single_port_ram_cfg.vhd
-add_fileset_file vector_FIFO.vhd VHDL PATH ../../src/vector_FIFO.vhd
-add_fileset_file syn_ros_rtt_config.vhd VHDL PATH ../syn_ros_rtt_config.vhd
-add_fileset_file dds_user_config.vhd VHDL PATH ../../src/ros2/dds_user_config.vhd
-add_fileset_file ros_config_package.vhd VHDL PATH ../../src/ros2/ros_config_package.vhd
-add_fileset_file ros_static_discovery_writer.vhd VHDL PATH ../../src/ros2/ros_static_discovery_writer.vhd
-add_fileset_file ros_time_converter.vhd VHDL PATH ../../src/ros2/ros_time_converter.vhd
-add_fileset_file CancelGoal_package.vhd VHDL PATH ../../src/ros2/rcl_interfaces/action_msgs/CancelGoal_package.vhd
-add_fileset_file GoalInfo_package.vhd VHDL PATH ../../src/ros2/rcl_interfaces/action_msgs/GoalInfo_package.vhd
-add_fileset_file GoalStatusArray_package.vhd VHDL PATH ../../src/ros2/rcl_interfaces/action_msgs/GoalStatusArray_package.vhd
-add_fileset_file GoalStatus_package.vhd VHDL PATH ../../src/ros2/rcl_interfaces/action_msgs/GoalStatus_package.vhd
 add_fileset_file Avalon_MM_wrapper.vhd VHDL PATH ../../src/Avalon_MM_wrapper.vhd
+add_fileset_file loopback.vhd VHDL PATH ../loopback.vhd
+add_fileset_file math_pkg.vhd VHDL PATH ../../src/math_pkg.vhd
+add_fileset_file rtps_config_package.vhd VHDL PATH ../../src/rtps_config_package.vhd
+add_fileset_file rtps_package.vhd VHDL PATH ../../src/rtps_package.vhd
+add_fileset_file TEMPLATE_user_config.vhd VHDL PATH ../../src/TEMPLATE_user_config.vhd
 
 
 # 

syn/DE10_NANO_SoC_GHRD/test_fpga_hw.tcl.ros_rtt.BAK

@@ -0,0 +1,163 @@
+# TCL File Generated by Component Editor 21.1
+# Sun Jul 23 18:44:32 GMT+02:00 2023
+# DO NOT MODIFY
+
+
+# 
+# test_fpga "test_fpga" v1.0
+#  2023.07.23.18:44:32
+# Test PL-PS Communication
+# 
+
+# 
+# request TCL package from ACDS 16.1
+# 
+package require -exact qsys 16.1
+
+
+# 
+# module test_fpga
+# 
+set_module_property DESCRIPTION "Test PL-PS Communication"
+set_module_property NAME test_fpga
+set_module_property VERSION 1.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property AUTHOR ""
+set_module_property DISPLAY_NAME test_fpga
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+# 
+# file sets
+# 
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL test_top
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
+add_fileset_file test_top.vhd VHDL PATH ../test_top.vhd TOP_LEVEL_FILE
+add_fileset_file math_pkg.vhd VHDL PATH ../../src/math_pkg.vhd
+add_fileset_file rtps_package.vhd VHDL PATH ../../src/rtps_package.vhd
+add_fileset_file ros_package.vhd VHDL PATH ../../src/ros2/ros_package.vhd
+add_fileset_file Type1_package.vhd VHDL PATH ../../src/ros2/Tests/Type1_package.vhd
+add_fileset_file Type1_ros_pub.vhd VHDL PATH ../../src/ros2/Tests/Type1_ros_pub.vhd
+add_fileset_file Type1_ros_sub.vhd VHDL PATH ../../src/ros2/Tests/Type1_ros_sub.vhd
+add_fileset_file test_loopback_util.vhd VHDL PATH ../../src/ros2/Tests/test_loopback_util.vhd
+add_fileset_file L2_Testbench_ROS_Lib6.vhd VHDL PATH ../../src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib6.vhd
+add_fileset_file FWFT_FIFO.vhd VHDL PATH ../../src/FWFT_FIFO.vhd
+add_fileset_file FWFT_FIFO_Altera.vhd VHDL PATH ../../src/FWFT_FIFO_Altera.vhd
+add_fileset_file FWFT_FIFO_cfg.vhd VHDL PATH ../../src/FWFT_FIFO_cfg.vhd
+add_fileset_file dds_reader.vhd VHDL PATH ../../src/dds_reader.vhd
+add_fileset_file dds_writer.vhd VHDL PATH ../../src/dds_writer.vhd
+add_fileset_file dp_mem_ctrl.vhd VHDL PATH ../../src/dp_mem_ctrl.vhd
+add_fileset_file dual_port_ram.vhd VHDL PATH ../../src/dual_port_ram.vhd
+add_fileset_file dual_port_ram_Altera.vhd VHDL PATH ../../src/dual_port_ram_Altera.vhd
+add_fileset_file dual_port_ram_cfg.vhd VHDL PATH ../../src/dual_port_ram_cfg.vhd
+add_fileset_file mem_ctrl.vhd VHDL PATH ../../src/mem_ctrl.vhd
+add_fileset_file moving_average.vhd VHDL PATH ../../src/moving_average.vhd
+add_fileset_file moving_average_wrapper.vhd VHDL PATH ../../src/moving_average_wrapper.vhd
+add_fileset_file mult.vhd VHDL PATH ../../src/mult.vhd
+add_fileset_file mult_Altera.vhd VHDL PATH ../../src/mult_Altera.vhd
+add_fileset_file mult_cfg.vhd VHDL PATH ../../src/mult_cfg.vhd
+add_fileset_file rtps_config_package.vhd VHDL PATH ../../src/rtps_config_package.vhd
+add_fileset_file rtps_discovery_module.vhd VHDL PATH ../../src/rtps_discovery_module.vhd
+add_fileset_file rtps_handler.vhd VHDL PATH ../../src/rtps_handler.vhd
+add_fileset_file rtps_out.vhd VHDL PATH ../../src/rtps_out.vhd
+add_fileset_file rtps_reader.vhd VHDL PATH ../../src/rtps_reader.vhd
+add_fileset_file rtps_writer.vhd VHDL PATH ../../src/rtps_writer.vhd
+add_fileset_file single_port_ram.vhd VHDL PATH ../../src/single_port_ram.vhd
+add_fileset_file single_port_ram_Altera.vhd VHDL PATH ../../src/single_port_ram_Altera.vhd
+add_fileset_file single_port_ram_cfg.vhd VHDL PATH ../../src/single_port_ram_cfg.vhd
+add_fileset_file vector_FIFO.vhd VHDL PATH ../../src/vector_FIFO.vhd
+add_fileset_file syn_ros_rtt_config.vhd VHDL PATH ../syn_ros_rtt_config.vhd
+add_fileset_file dds_user_config.vhd VHDL PATH ../../src/ros2/dds_user_config.vhd
+add_fileset_file ros_config_package.vhd VHDL PATH ../../src/ros2/ros_config_package.vhd
+add_fileset_file ros_static_discovery_writer.vhd VHDL PATH ../../src/ros2/ros_static_discovery_writer.vhd
+add_fileset_file ros_time_converter.vhd VHDL PATH ../../src/ros2/ros_time_converter.vhd
+add_fileset_file CancelGoal_package.vhd VHDL PATH ../../src/ros2/rcl_interfaces/action_msgs/CancelGoal_package.vhd
+add_fileset_file GoalInfo_package.vhd VHDL PATH ../../src/ros2/rcl_interfaces/action_msgs/GoalInfo_package.vhd
+add_fileset_file GoalStatusArray_package.vhd VHDL PATH ../../src/ros2/rcl_interfaces/action_msgs/GoalStatusArray_package.vhd
+add_fileset_file GoalStatus_package.vhd VHDL PATH ../../src/ros2/rcl_interfaces/action_msgs/GoalStatus_package.vhd
+add_fileset_file Avalon_MM_wrapper.vhd VHDL PATH ../../src/Avalon_MM_wrapper.vhd
+
+
+# 
+# parameters
+# 
+
+
+# 
+# display items
+# 
+
+
+# 
+# connection point clock
+# 
+add_interface clock clock end
+set_interface_property clock clockRate 0
+set_interface_property clock ENABLED true
+set_interface_property clock EXPORT_OF ""
+set_interface_property clock PORT_NAME_MAP ""
+set_interface_property clock CMSIS_SVD_VARIABLES ""
+set_interface_property clock SVD_ADDRESS_GROUP ""
+
+add_interface_port clock clk clk Input 1
+
+
+# 
+# connection point reset
+# 
+add_interface reset reset end
+set_interface_property reset associatedClock clock
+set_interface_property reset synchronousEdges DEASSERT
+set_interface_property reset ENABLED true
+set_interface_property reset EXPORT_OF ""
+set_interface_property reset PORT_NAME_MAP ""
+set_interface_property reset CMSIS_SVD_VARIABLES ""
+set_interface_property reset SVD_ADDRESS_GROUP ""
+
+add_interface_port reset reset reset Input 1
+
+
+# 
+# connection point avalon_slave_0
+# 
+add_interface avalon_slave_0 avalon end
+set_interface_property avalon_slave_0 addressUnits WORDS
+set_interface_property avalon_slave_0 associatedClock clock
+set_interface_property avalon_slave_0 associatedReset reset
+set_interface_property avalon_slave_0 bitsPerSymbol 8
+set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
+set_interface_property avalon_slave_0 burstcountUnits WORDS
+set_interface_property avalon_slave_0 explicitAddressSpan 0
+set_interface_property avalon_slave_0 holdTime 0
+set_interface_property avalon_slave_0 linewrapBursts false
+set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
+set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0
+set_interface_property avalon_slave_0 readLatency 0
+set_interface_property avalon_slave_0 readWaitTime 1
+set_interface_property avalon_slave_0 setupTime 0
+set_interface_property avalon_slave_0 timingUnits Cycles
+set_interface_property avalon_slave_0 writeWaitTime 0
+set_interface_property avalon_slave_0 ENABLED true
+set_interface_property avalon_slave_0 EXPORT_OF ""
+set_interface_property avalon_slave_0 PORT_NAME_MAP ""
+set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES ""
+set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP ""
+
+add_interface_port avalon_slave_0 address address Input 2
+add_interface_port avalon_slave_0 read read Input 1
+add_interface_port avalon_slave_0 write write Input 1
+add_interface_port avalon_slave_0 readdata readdata Output 32
+add_interface_port avalon_slave_0 writedata writedata Input 32
+add_interface_port avalon_slave_0 waitrequest waitrequest Output 1
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0
+set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0
+

syn/loopback.vhd

@@ -0,0 +1,172 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.rtps_package.all;
+
+-- LOOPBACK
+-- This entity reads packets form the input FIFO, flips the src/dest address and ports, and writes the packet back to
+-- the output FIFO.
+-- This loopback entity can be used to measure maximum throughput through the FIFO interfaces.
+
+-- Packets have following structure:
+--    31............24..............16..............8...............0
+--   |               |               |               |               |
+--   +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+--   +---------------------------------------------------------------+
+-- 01|                         SRC_IPv4_ADDR                         |
+--   +---------------------------------------------------------------+
+-- 02|                         DEST_IPv4_ADDR                        |
+--   +-------------------------------+-------------------------------+
+-- 03|         SRC_UDP_PORT          |          DEST_UDP_PORT        |
+--   +-------------------------------+-------------------------------+
+-- 04|                         PACKET_LENGTH                         |
+--   +---------------------------------------------------------------+
+-- 05|                                                               |
+--   ~                             PACKET                            ~
+-- **|                                                               |
+--   +---------------------------------------------------------------+
+
+entity loopback is
+    port (
+        -- SYSTEM
+        clk         : in std_logic;
+        reset       : in std_logic;
+        -- INPUT
+        empty       : in std_logic;
+        rd          : out std_logic;
+        data_in     : in std_logic_vector(WORD_WIDTH-1 downto 0);
+        -- OUTPUT
+        full        : in std_logic;
+        wr          : out std_logic;
+        data_out    : out std_logic_vector(WORD_WIDTH-1 downto 0)
+    );
+end entity;
+
+architecture arch of loopback is
+    
+    -- *TYPE DECLARATION*
+    type STAGE_TYPE is (READ_SRC_ADDR, READ_DEST_ADDR, READ_PORTS, READ_LENGTH, WRITE_SRC_ADDR, WRITE_DEST_ADDR, WRITE_PORTS, WRITE_LENGTH, PASSTHROUGH);
+    
+    -- *SIGNAL DECLARATION*
+    signal stage, stage_next : STAGE_TYPE;
+    signal src_addr, src_addr_next : std_logic_vector(WORD_WIDTH-1 downto 0);
+    signal dest_addr, dest_addr_next : std_logic_vector(WORD_WIDTH-1 downto 0);
+    signal ports, ports_next : std_logic_vector(WORD_WIDTH-1 downto 0);
+    signal length, length_next : unsigned(WORD_WIDTH-1 downto 0);
+    signal cnt, cnt_next : unsigned(WORD_WIDTH-1 downto 0);
+    
+begin
+    
+    main_prc : process (all)
+    begin
+        -- DEFAULT
+        stage_next      <= stage;
+        src_addr_next   <= src_addr;
+        dest_addr_next  <= dest_addr;
+        ports_next      <= ports;
+        length_next     <= length;
+        cnt_next        <= cnt;
+        -- DEFAULT Unregistered
+        rd          <= '0';
+        wr          <= '0';
+        data_out    <= (others => '0');
+        
+        case (stage) is
+            when READ_SRC_ADDR =>
+                -- Input FIFO Guard
+                if (empty = '0') then
+                    src_addr_next   <= data_in;
+                    rd              <= '1';
+                    stage_next      <= READ_DEST_ADDR;
+                end if;
+            when READ_DEST_ADDR =>
+                -- Input FIFO Guard
+                if (empty = '0') then
+                    dest_addr_next  <= data_in;
+                    rd              <= '1';
+                    stage_next      <= READ_PORTS;
+                end if;
+            when READ_PORTS =>
+                -- Input FIFO Guard
+                if (empty = '0') then
+                    ports_next  <= data_in;
+                    rd          <= '1';
+                    stage_next  <= READ_LENGTH;
+                end if;
+            when READ_LENGTH =>
+                -- Input FIFO Guard
+                if (empty = '0') then
+                    length_next <= unsigned(data_in);
+                    rd          <= '1';
+                    stage_next  <= WRITE_SRC_ADDR;
+                end if;
+            when WRITE_SRC_ADDR =>
+                -- Output FIFO Guard
+                if (full = '0') then
+                    data_out    <= dest_addr;
+                    wr          <= '1';
+                    stage_next  <= WRITE_DEST_ADDR;
+                end if;
+            when WRITE_DEST_ADDR =>
+                -- Output FIFO Guard
+                if (full = '0') then
+                    data_out    <= src_addr;
+                    wr          <= '1';
+                    stage_next  <= WRITE_PORTS;
+                end if;
+            when WRITE_PORTS =>
+                -- Output FIFO Guard
+                if (full = '0') then
+                    data_out    <= ports(UDP_PORT_WIDTH-1 downto 0) & ports(WORD_WIDTH-1 downto UDP_PORT_WIDTH);
+                    wr          <= '1';
+                    stage_next  <= WRITE_LENGTH;
+                end if;
+            when WRITE_LENGTH =>
+                -- Output FIFO Guard
+                if (full = '0') then
+                    data_out    <= std_logic_vector(length);
+                    wr          <= '1';
+                    stage_next  <= PASSTHROUGH;
+                    cnt_next    <= to_unsigned(1,WORD_WIDTH);
+                end if;
+            when PASSTHROUGH =>
+                -- Input & Output FIFO Guard
+                if (empty = '0' and full = '0') then
+                    data_out    <= data_in;
+                    rd          <= '1';
+                    wr          <= '1';
+                    cnt_next    <= cnt + 1;
+                    -- Reached End of Packet
+                    if (cnt = length) then
+                        stage_next  <= READ_SRC_ADDR;
+                    end if;
+                end if;
+        end case;
+    end process;
+    
+    sync_prc : process(all)
+    begin
+        if rising_edge(clk) then
+            if (reset = '1') then
+                stage       <= READ_SRC_ADDR;
+                src_addr    <= (others => '0');
+                dest_addr   <= (others => '0');
+                ports       <= (others => '0');
+                length      <= (others => '0');
+                cnt         <= (others => '0');
+            else
+                stage       <= stage_next;
+                src_addr    <= src_addr_next;
+                dest_addr   <= dest_addr_next;
+                ports       <= ports_next;
+                length      <= length_next;
+                cnt         <= cnt_next;
+            end if;
+        end if;
+    end process;
+    
+end architecture;

syn/test_top.vhd

@@ -132,22 +132,37 @@ begin
     --        data_out    => data_test_fo
     --    );
     
-    ros_rtt : entity work.L2_Testbench_ROS_Lib6(arch)
+    --ros_rtt_inst : entity work.L2_Testbench_ROS_Lib6(arch)
+    --    port map (
+    --        -- SYSTEM
+    --        clk         => clk,
+    --        reset       => reset,
+    --        time        => time,
+    --        -- UTILIZATION
+    --        input_util  => std_logic_vector(to_unsigned(input_util, WORD_WIDTH)),
+    --        output_util => std_logic_vector(to_unsigned(output_util, WORD_WIDTH)),
+    --        -- INPUT
+    --        empty       => empty_fi_test,
+    --        read        => read_test_fi,
+    --        data_in     => data_fi_test,
+    --        -- OUTPUT
+    --        full        => full_fo_test,
+    --        write       => write_test_fo,
+    --        data_out    => data_test_fo
+    --    );
+        
+    loopback_inst : entity work.loopback(arch)
         port map (
             -- SYSTEM
             clk         => clk,
             reset       => reset,
-            time        => time,
-            -- UTILIZATION
-            input_util  => std_logic_vector(to_unsigned(input_util, WORD_WIDTH)),
-            output_util => std_logic_vector(to_unsigned(output_util, WORD_WIDTH)),
             -- INPUT
             empty       => empty_fi_test,
-            read        => read_test_fi,
+            rd          => read_test_fi,
             data_in     => data_fi_test,
             -- OUTPUT
             full        => full_fo_test,
-            write       => write_test_fo,
+            wr          => write_test_fo,
             data_out    => data_test_fo
         );