Add directive to allow QSYS Compilation

QSYS does not allow to change the VHDL version of processed files.
All respective files have to have a comment directive forcing the VHDL version.

src/Avalon_MM_wrapper.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -84,4 +87,4 @@ begin
         end if;
     end process;
     
-end architecture;
+end architecture;

src/FWFT_FIFO.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -66,4 +69,4 @@ begin
         end if;
     end process;
     
-end architecture;
+end architecture;

src/FWFT_FIFO_Altera.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -40,4 +43,4 @@ begin
 		usedw   => used_sig
 	);
     
-end architecture;
+end architecture;

src/FWFT_FIFO_cfg.vhd

@@ -1,4 +1,7 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 configuration FWFT_FIFO_cfg of FWFT_FIFO is
     for altera
     end for;
-end configuration;
+end configuration;

src/TEMPLATE_key_holder.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -508,4 +511,4 @@ begin
         end if;
     end process;
     
-end architecture;
+end architecture;

src/TEMPLATE_reader_wrapper.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -391,4 +394,4 @@ begin
         end if;
     end process;
     
-end architecture;
+end architecture;

src/TEMPLATE_writer_wrapper.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -253,4 +256,4 @@ begin
         end if;
     end process;
     
-end architecture;
+end architecture;

src/addsub.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -73,4 +76,4 @@ begin
         end if;
     end process;
     
-end architecture;
+end architecture;

src/checksum.vhd

@@ -1,8 +1,10 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
-
 entity addsub is
     generic (
         INPUT_WIDTH     : integer := 32;
@@ -44,4 +46,4 @@ architecture arch of addsub is
 begin
 
     
-end architecture;
+end architecture;

src/dds_reader.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -6825,4 +6828,4 @@ begin
             end if;
         end if;
     end process;
-end architecture;
+end architecture;

src/dds_writer.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -4685,4 +4688,4 @@ begin
         end if;
     end process;
     
-end architecture;
+end architecture;

src/history_cache.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -1677,4 +1680,4 @@ begin
         end case;
     end process;
     
-end architecture;
+end architecture;

src/ip_package.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -15,4 +18,4 @@ package ip_package is
 end package;
 
 package body ip_package is
-end package body;
+end package body;

src/ipv4_in_handler.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -1033,4 +1036,4 @@ begin
         end if;
     end process;
     
-end architecture;
+end architecture;

src/key_hash_generator.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -19,4 +22,4 @@ entity key_hash_generator is
         key_hash        : out std_logic_vector(127 downto 0);
         done            : out std_logic
     );
-end entity;
+end entity;

src/key_holder.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -27,4 +30,4 @@ entity key_holder is
         data_out        : out std_logic_vector(WORD_WIDTH-1 downto 0);
         last_word_out   : out std_logic
     );
-end entity;
+end entity;

src/math_pkg.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 package math_pkg is
     -- calculates the logarithm dualis of the operand and rounds up
     -- the result to the next integer value.

src/mem_ctrl.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -110,4 +113,4 @@ begin
             full        => open,
             free        => fifo_cnt
         );
-end architecture;
+end architecture;

src/rtps_builtin_endpoint.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

src/rtps_config_package.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

src/rtps_handler.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

src/rtps_out.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -312,4 +315,4 @@ begin
         end if;
     end process;
     
-end architecture;
+end architecture;

src/rtps_package.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

src/rtps_reader.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -3068,4 +3071,4 @@ begin
             end if;
         end if;
     end process;
-end architecture;
+end architecture;

src/rtps_test_package.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -3367,4 +3370,4 @@ package body rtps_test_package is
         end loop;
     end procedure;
     
-end package body;
+end package body;

src/rtps_writer.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -3757,4 +3760,4 @@ begin
         end if;
     end process;
     
-end architecture;
+end architecture;

src/single_port_ram.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

src/single_port_ram_Altera.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

src/single_port_ram_cfg.vhd

@@ -1,4 +1,7 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 configuration single_port_ram_cfg of single_port_ram is
     for altera
     end for;
-end configuration;
+end configuration;

src/true_dual_port_ram.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

src/user_config.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -123,4 +126,4 @@ package user_config is
     
     -- Set to TRUE for Simulation Testing (Extra Code generated)
     constant SIMULATION_FLAG : boolean := FALSE;
-end package;
+end package;

syn/dds_reader_syn.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

syn/dds_writer_syn.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

syn/rtps_reader_syn.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

syn/rtps_writer_syn.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

syn/syn_config.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -125,4 +128,4 @@ package user_config is
     
     -- Set to TRUE for Simulation Testing (Extra Code generated)
     constant SIMULATION_FLAG : boolean := FALSE;
-end package;
+end package;

syn/test.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

syn/test2.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

syn/test3.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

syn/test4.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

syn/test5.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

syn/test_fpga.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

syn/test_package.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

syn/test_top.vhd

@@ -1,3 +1,6 @@
+-- altera vhdl_input_version vhdl_2008
+-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;