Convert dds_writer to Vector Endpoint
This commit is contained in:
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74af242bcc
commit
5e7ea79887
@ -59,4 +59,18 @@
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; |dds_writer:\dds_endpoint_gen:7:dds_endpoint_if:dds_writer_inst| ; 1496 (1357) ; 527 (453) ; 292096 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_gen:7:dds_endpoint_if:dds_writer_inst ; dds_writer ; work ;
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; |rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst| ; 5427 (5295) ; 2360 (2279) ; 84672 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst ; rtps_reader ; work ;
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; |rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst| ; 7010 (6750) ; 3150 (2988) ; 169344 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst ; rtps_writer ; work ;
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+------------------------------------------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+--------------+
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+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Analysis & Synthesis Resource Utilization by Entity ;
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+------------------------------------------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+--------------+
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; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
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+------------------------------------------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+--------------+
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; |test_top ; 42256 (64) ; 19765 (63) ; 2408283 ; 4 ; 71 ; 0 ; |test_top ; test_top ; work ;
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; |dds_reader:\dds_endpoint_gen:0:dds_reader_inst| ; 2371 (2263) ; 606 (551) ; 20160 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst ; dds_reader ; work ;
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; |dds_reader:\dds_endpoint_gen:1:dds_reader_inst| ; 2363 (2258) ; 605 (551) ; 18752 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst ; dds_reader ; work ;
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; |dds_reader:\dds_endpoint_gen:2:dds_reader_inst| ; 2372 (2266) ; 605 (551) ; 21568 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst ; dds_reader ; work ;
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; |dds_writer:\dds_endpoint_w_if:dds_writer_inst| ; 6798 (4926) ; 4149 (1812) ; 428928 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst ; dds_writer ; work ;
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; |rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst| ; 5381 (5249) ; 2360 (2279) ; 84672 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst ; rtps_reader ; work ;
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; |rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst| ; 6872 (6612) ; 3150 (2988) ; 169344 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst ; rtps_writer ; work ;
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+------------------------------------------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+--------------+
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686
ros_action_Fibonacci_with_feedback5.rpt
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686
ros_action_Fibonacci_with_feedback5.rpt
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@ -0,0 +1,686 @@
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Resource Utilization by Entity report for top
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Sat Apr 2 19:16:42 2022
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Quartus Prime Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Analysis & Synthesis Resource Utilization by Entity
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 2021 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and any partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details, at
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https://fpgasoftware.intel.com/eula.
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+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Analysis & Synthesis Resource Utilization by Entity ;
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+------------------------------------------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+--------------+
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; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
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+------------------------------------------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+--------------+
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; |test_top ; 42256 (64) ; 19765 (63) ; 2408283 ; 4 ; 71 ; 0 ; |test_top ; test_top ; work ;
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; |Avalon_MM_wrapper:Avalon_MM_wrapper_inst| ; 69 (69) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|Avalon_MM_wrapper:Avalon_MM_wrapper_inst ; Avalon_MM_wrapper ; work ;
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; |FWFT_FIFO:FIFO_IN_inst| ; 121 (0) ; 62 (0) ; 524288 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_IN_inst ; FWFT_FIFO ; work ;
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; |scfifo:scfifo_component| ; 121 (0) ; 62 (0) ; 524288 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_IN_inst|scfifo:scfifo_component ; scfifo ; work ;
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; |scfifo_ink1:auto_generated| ; 121 (0) ; 62 (0) ; 524288 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_IN_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated ; scfifo_ink1 ; work ;
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; |a_dpfifo_ojb1:dpfifo| ; 121 (43) ; 62 (20) ; 524288 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_IN_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo ; a_dpfifo_ojb1 ; work ;
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; |altsyncram_eek1:FIFOram| ; 34 (0) ; 1 (1) ; 524288 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_IN_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo|altsyncram_eek1:FIFOram ; altsyncram_eek1 ; work ;
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; |decode_s07:decode2| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_IN_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo|altsyncram_eek1:FIFOram|decode_s07:decode2 ; decode_s07 ; work ;
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; |decode_s07:wren_decode_a| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_IN_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo|altsyncram_eek1:FIFOram|decode_s07:wren_decode_a ; decode_s07 ; work ;
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; |mux_ps7:mux3| ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_IN_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo|altsyncram_eek1:FIFOram|mux_ps7:mux3 ; mux_ps7 ; work ;
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; |cntr_04b:wr_ptr| ; 15 (15) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_IN_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo|cntr_04b:wr_ptr ; cntr_04b ; work ;
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; |cntr_c47:usedw_counter| ; 15 (15) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_IN_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo|cntr_c47:usedw_counter ; cntr_c47 ; work ;
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; |cntr_v3b:rd_ptr_msb| ; 14 (14) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_IN_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo|cntr_v3b:rd_ptr_msb ; cntr_v3b ; work ;
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; |FWFT_FIFO:FIFO_OUT_inst| ; 91 (0) ; 62 (0) ; 524288 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_OUT_inst ; FWFT_FIFO ; work ;
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; |scfifo:scfifo_component| ; 91 (0) ; 62 (0) ; 524288 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_OUT_inst|scfifo:scfifo_component ; scfifo ; work ;
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; |scfifo_ink1:auto_generated| ; 91 (0) ; 62 (0) ; 524288 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_OUT_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated ; scfifo_ink1 ; work ;
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; |a_dpfifo_ojb1:dpfifo| ; 91 (45) ; 62 (20) ; 524288 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_OUT_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo ; a_dpfifo_ojb1 ; work ;
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; |altsyncram_eek1:FIFOram| ; 2 (0) ; 1 (1) ; 524288 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_OUT_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo|altsyncram_eek1:FIFOram ; altsyncram_eek1 ; work ;
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; |decode_s07:decode2| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_OUT_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo|altsyncram_eek1:FIFOram|decode_s07:decode2 ; decode_s07 ; work ;
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; |cntr_04b:wr_ptr| ; 15 (15) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_OUT_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo|cntr_04b:wr_ptr ; cntr_04b ; work ;
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; |cntr_c47:usedw_counter| ; 15 (15) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_OUT_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo|cntr_c47:usedw_counter ; cntr_c47 ; work ;
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; |cntr_v3b:rd_ptr_msb| ; 14 (14) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; |test_top|FWFT_FIFO:FIFO_OUT_inst|scfifo:scfifo_component|scfifo_ink1:auto_generated|a_dpfifo_ojb1:dpfifo|cntr_v3b:rd_ptr_msb ; cntr_v3b ; work ;
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; |L2_Testbench_ROS_Lib4:ros_action_inst| ; 41911 (0) ; 19578 (0) ; 1359707 ; 4 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst ; L2_Testbench_ROS_Lib4 ; work ;
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; |FWFT_FIFO:\fifo_in_ro_gen:0:fifo_in_ro_if:fifo_in_ro_inst| ; 17 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:0:fifo_in_ro_if:fifo_in_ro_inst ; FWFT_FIFO ; work ;
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; |scfifo:scfifo_component| ; 17 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:0:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component ; scfifo ; work ;
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; |scfifo_bfk1:auto_generated| ; 17 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:0:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated ; scfifo_bfk1 ; work ;
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; |a_dpfifo_hbb1:dpfifo| ; 17 (13) ; 9 (7) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:0:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo ; a_dpfifo_hbb1 ; work ;
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; |altsyncram_0uj1:FIFOram| ; 0 (0) ; 0 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:0:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|altsyncram_0uj1:FIFOram ; altsyncram_0uj1 ; work ;
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; |cntr_c2b:wr_ptr| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:0:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_c2b:wr_ptr ; cntr_c2b ; work ;
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; |cntr_o27:usedw_counter| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:0:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_o27:usedw_counter ; cntr_o27 ; work ;
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; |FWFT_FIFO:\fifo_in_ro_gen:1:fifo_in_ro_if:fifo_in_ro_inst| ; 17 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:1:fifo_in_ro_if:fifo_in_ro_inst ; FWFT_FIFO ; work ;
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; |scfifo:scfifo_component| ; 17 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:1:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component ; scfifo ; work ;
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; |scfifo_bfk1:auto_generated| ; 17 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:1:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated ; scfifo_bfk1 ; work ;
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; |a_dpfifo_hbb1:dpfifo| ; 17 (13) ; 9 (7) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:1:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo ; a_dpfifo_hbb1 ; work ;
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; |altsyncram_0uj1:FIFOram| ; 0 (0) ; 0 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:1:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|altsyncram_0uj1:FIFOram ; altsyncram_0uj1 ; work ;
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; |cntr_c2b:wr_ptr| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:1:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_c2b:wr_ptr ; cntr_c2b ; work ;
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; |cntr_o27:usedw_counter| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:1:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_o27:usedw_counter ; cntr_o27 ; work ;
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; |FWFT_FIFO:\fifo_in_ro_gen:2:fifo_in_ro_if:fifo_in_ro_inst| ; 16 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:2:fifo_in_ro_if:fifo_in_ro_inst ; FWFT_FIFO ; work ;
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; |scfifo:scfifo_component| ; 16 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:2:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component ; scfifo ; work ;
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; |scfifo_bfk1:auto_generated| ; 16 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:2:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated ; scfifo_bfk1 ; work ;
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; |a_dpfifo_hbb1:dpfifo| ; 16 (12) ; 9 (7) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:2:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo ; a_dpfifo_hbb1 ; work ;
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; |altsyncram_0uj1:FIFOram| ; 0 (0) ; 0 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:2:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|altsyncram_0uj1:FIFOram ; altsyncram_0uj1 ; work ;
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; |cntr_c2b:wr_ptr| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:2:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_c2b:wr_ptr ; cntr_c2b ; work ;
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; |cntr_o27:usedw_counter| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:\fifo_in_ro_gen:2:fifo_in_ro_if:fifo_in_ro_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_o27:usedw_counter ; cntr_o27 ; work ;
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; |FWFT_FIFO:fifo_in_rb_inst| ; 16 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:fifo_in_rb_inst ; FWFT_FIFO ; work ;
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; |scfifo:scfifo_component| ; 16 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:fifo_in_rb_inst|scfifo:scfifo_component ; scfifo ; work ;
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; |scfifo_bfk1:auto_generated| ; 16 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:fifo_in_rb_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated ; scfifo_bfk1 ; work ;
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; |a_dpfifo_hbb1:dpfifo| ; 16 (12) ; 9 (7) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:fifo_in_rb_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo ; a_dpfifo_hbb1 ; work ;
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; |altsyncram_0uj1:FIFOram| ; 0 (0) ; 0 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:fifo_in_rb_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|altsyncram_0uj1:FIFOram ; altsyncram_0uj1 ; work ;
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; |cntr_c2b:wr_ptr| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:fifo_in_rb_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_c2b:wr_ptr ; cntr_c2b ; work ;
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; |cntr_o27:usedw_counter| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|FWFT_FIFO:fifo_in_rb_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_o27:usedw_counter ; cntr_o27 ; work ;
|
||||
; |Fibonacci:Fibonacci_inst| ; 295 (295) ; 183 (183) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci:Fibonacci_inst ; Fibonacci ; work ;
|
||||
; |Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst| ; 4277 (128) ; 3171 (13) ; 50439 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst ; Fibonacci_ros_action_server ; work ;
|
||||
; |CancelGoal_ros_srv_server:cancel_srv_server_inst| ; 598 (584) ; 699 (501) ; 19200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst ; CancelGoal_ros_srv_server ; work ;
|
||||
; |mem_ctrl:goals_canceling_goal_id_mem| ; 8 (5) ; 131 (2) ; 12800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_goal_id_mem ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 3 (0) ; 129 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_goal_id_mem|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 3 (0) ; 129 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_goal_id_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |a_regfifo:subfifo| ; 3 (3) ; 129 (129) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_goal_id_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|a_regfifo:subfifo ; a_regfifo ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 12800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_goal_id_mem|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 12800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_goal_id_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_hpv3:auto_generated| ; 0 (0) ; 0 (0) ; 12800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_goal_id_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_hpv3:auto_generated ; altsyncram_hpv3 ; work ;
|
||||
; |mem_ctrl:goals_canceling_stamp_mem| ; 6 (4) ; 67 (2) ; 6400 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_stamp_mem ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 2 (0) ; 65 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_stamp_mem|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 2 (0) ; 65 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_stamp_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |a_regfifo:subfifo| ; 2 (2) ; 65 (65) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_stamp_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|a_regfifo:subfifo ; a_regfifo ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 6400 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_stamp_mem|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 6400 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_stamp_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_vnv3:auto_generated| ; 0 (0) ; 0 (0) ; 6400 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|CancelGoal_ros_srv_server:cancel_srv_server_inst|mem_ctrl:goals_canceling_stamp_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_vnv3:auto_generated ; altsyncram_vnv3 ; work ;
|
||||
; |Fibonacci_ros_action_feedback_pub:\feedback_gen:feedback_pub_inst| ; 194 (155) ; 95 (60) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_feedback_pub:\feedback_gen:feedback_pub_inst ; Fibonacci_ros_action_feedback_pub ; work ;
|
||||
; |mem_ctrl:seq_mem| ; 39 (4) ; 35 (2) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_feedback_pub:\feedback_gen:feedback_pub_inst|mem_ctrl:seq_mem ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 35 (0) ; 33 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_feedback_pub:\feedback_gen:feedback_pub_inst|mem_ctrl:seq_mem|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 35 (0) ; 33 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_feedback_pub:\feedback_gen:feedback_pub_inst|mem_ctrl:seq_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |a_regfifo:subfifo| ; 35 (35) ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_feedback_pub:\feedback_gen:feedback_pub_inst|mem_ctrl:seq_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|a_regfifo:subfifo ; a_regfifo ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_feedback_pub:\feedback_gen:feedback_pub_inst|mem_ctrl:seq_mem|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_feedback_pub:\feedback_gen:feedback_pub_inst|mem_ctrl:seq_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_qnv3:auto_generated| ; 0 (0) ; 0 (0) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_feedback_pub:\feedback_gen:feedback_pub_inst|mem_ctrl:seq_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_qnv3:auto_generated ; altsyncram_qnv3 ; work ;
|
||||
; |Fibonacci_ros_action_goal_srv_server:goal_srv_server_inst| ; 368 (368) ; 460 (460) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_goal_srv_server:goal_srv_server_inst ; Fibonacci_ros_action_goal_srv_server ; work ;
|
||||
; |Fibonacci_ros_action_result_srv_server:result_srv_server_inst| ; 458 (419) ; 470 (435) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_result_srv_server:result_srv_server_inst ; Fibonacci_ros_action_result_srv_server ; work ;
|
||||
; |mem_ctrl:seq_mem| ; 39 (5) ; 35 (2) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_result_srv_server:result_srv_server_inst|mem_ctrl:seq_mem ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 34 (0) ; 33 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_result_srv_server:result_srv_server_inst|mem_ctrl:seq_mem|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 34 (0) ; 33 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_result_srv_server:result_srv_server_inst|mem_ctrl:seq_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |a_regfifo:subfifo| ; 34 (34) ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_result_srv_server:result_srv_server_inst|mem_ctrl:seq_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|a_regfifo:subfifo ; a_regfifo ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_result_srv_server:result_srv_server_inst|mem_ctrl:seq_mem|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_result_srv_server:result_srv_server_inst|mem_ctrl:seq_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_qnv3:auto_generated| ; 0 (0) ; 0 (0) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|Fibonacci_ros_action_result_srv_server:result_srv_server_inst|mem_ctrl:seq_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_qnv3:auto_generated ; altsyncram_qnv3 ; work ;
|
||||
; |GoalStatusArray_ros_pub:status_pub_inst| ; 254 (226) ; 271 (62) ; 20000 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst ; GoalStatusArray_ros_pub ; work ;
|
||||
; |mem_ctrl:status_list_goal_info_goal_id_mem| ; 7 (4) ; 131 (2) ; 12800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_goal_id_mem ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 3 (0) ; 129 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_goal_id_mem|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 3 (0) ; 129 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_goal_id_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |a_regfifo:subfifo| ; 3 (3) ; 129 (129) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_goal_id_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|a_regfifo:subfifo ; a_regfifo ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 12800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_goal_id_mem|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 12800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_goal_id_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_hpv3:auto_generated| ; 0 (0) ; 0 (0) ; 12800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_goal_id_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_hpv3:auto_generated ; altsyncram_hpv3 ; work ;
|
||||
; |mem_ctrl:status_list_goal_info_stamp_mem| ; 6 (4) ; 67 (2) ; 6400 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_stamp_mem ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 2 (0) ; 65 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_stamp_mem|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 2 (0) ; 65 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_stamp_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |a_regfifo:subfifo| ; 2 (2) ; 65 (65) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_stamp_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|a_regfifo:subfifo ; a_regfifo ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 6400 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_stamp_mem|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 6400 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_stamp_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_vnv3:auto_generated| ; 0 (0) ; 0 (0) ; 6400 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_goal_info_stamp_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_vnv3:auto_generated ; altsyncram_vnv3 ; work ;
|
||||
; |mem_ctrl:status_list_status_mem| ; 15 (4) ; 11 (2) ; 800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_status_mem ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 11 (0) ; 9 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_status_mem|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 11 (0) ; 9 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_status_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |a_regfifo:subfifo| ; 11 (11) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_status_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|a_regfifo:subfifo ; a_regfifo ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_status_mem|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_status_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_emv3:auto_generated| ; 0 (0) ; 0 (0) ; 800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|GoalStatusArray_ros_pub:status_pub_inst|mem_ctrl:status_list_status_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_emv3:auto_generated ; altsyncram_emv3 ; work ;
|
||||
; |mem_ctrl:\r_seq_gen:0:r_seq_mem| ; 38 (4) ; 35 (2) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:\r_seq_gen:0:r_seq_mem ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 34 (0) ; 33 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:\r_seq_gen:0:r_seq_mem|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 34 (0) ; 33 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:\r_seq_gen:0:r_seq_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |a_regfifo:subfifo| ; 34 (34) ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:\r_seq_gen:0:r_seq_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|a_regfifo:subfifo ; a_regfifo ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:\r_seq_gen:0:r_seq_mem|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:\r_seq_gen:0:r_seq_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_qnv3:auto_generated| ; 0 (0) ; 0 (0) ; 3200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:\r_seq_gen:0:r_seq_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_qnv3:auto_generated ; altsyncram_qnv3 ; work ;
|
||||
; |mem_ctrl:r_seq_len_mem| ; 14 (5) ; 10 (2) ; 7 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:r_seq_len_mem ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 9 (0) ; 8 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:r_seq_len_mem|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 9 (0) ; 8 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:r_seq_len_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |a_regfifo:subfifo| ; 9 (9) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:r_seq_len_mem|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|a_regfifo:subfifo ; a_regfifo ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 7 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:r_seq_len_mem|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 7 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:r_seq_len_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_6jv3:auto_generated| ; 0 (0) ; 0 (0) ; 7 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|mem_ctrl:r_seq_len_mem|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_6jv3:auto_generated ; altsyncram_6jv3 ; work ;
|
||||
; |ros_action_server:action_server_inst| ; 2225 (2142) ; 1118 (1072) ; 1632 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst ; ros_action_server ; work ;
|
||||
; |mem_ctrl:goal_mem_ctrl_inst| ; 42 (6) ; 23 (2) ; 832 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:goal_mem_ctrl_inst ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 36 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:goal_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 36 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:goal_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_sgk1:auto_generated| ; 36 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:goal_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated ; scfifo_sgk1 ; work ;
|
||||
; |a_dpfifo_2db1:dpfifo| ; 36 (22) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:goal_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo ; a_dpfifo_2db1 ; work ;
|
||||
; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:goal_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ;
|
||||
; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:goal_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ;
|
||||
; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:goal_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ;
|
||||
; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:goal_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 320 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:goal_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 320 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:goal_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_7mv3:auto_generated| ; 0 (0) ; 0 (0) ; 320 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:goal_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_7mv3:auto_generated ; altsyncram_7mv3 ; work ;
|
||||
; |mem_ctrl:rrq_mem_ctrl_inst| ; 41 (6) ; 23 (2) ; 800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:rrq_mem_ctrl_inst ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 35 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:rrq_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 35 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:rrq_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_kfk1:auto_generated| ; 35 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:rrq_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated ; scfifo_kfk1 ; work ;
|
||||
; |a_dpfifo_qbb1:dpfifo| ; 35 (21) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:rrq_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo ; a_dpfifo_qbb1 ; work ;
|
||||
; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:rrq_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ;
|
||||
; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:rrq_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ;
|
||||
; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:rrq_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ;
|
||||
; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:rrq_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:rrq_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:rrq_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_vkv3:auto_generated| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|Fibonacci_ros_action_server:Fibonacci_ros_action_server_inst|ros_action_server:action_server_inst|mem_ctrl:rrq_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_vkv3:auto_generated ; altsyncram_vkv3 ; work ;
|
||||
; |dds_reader:\dds_endpoint_gen:0:dds_reader_inst| ; 2371 (2263) ; 606 (551) ; 20160 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst ; dds_reader ; work ;
|
||||
; |key_holder:key_holder_inst| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|key_holder:key_holder_inst ; key_holder ; work ;
|
||||
; |mem_ctrl:payload_mem_ctrl_inst| ; 61 (14) ; 31 (2) ; 16128 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 47 (2) ; 29 (0) ; 2048 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 45 (0) ; 29 (0) ; 2048 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_1hk1:auto_generated| ; 45 (0) ; 29 (0) ; 2048 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_1hk1:auto_generated ; scfifo_1hk1 ; work ;
|
||||
; |a_dpfifo_7db1:dpfifo| ; 45 (25) ; 29 (12) ; 2048 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_1hk1:auto_generated|a_dpfifo_7db1:dpfifo ; a_dpfifo_7db1 ; work ;
|
||||
; |altsyncram_o1k1:FIFOram| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_1hk1:auto_generated|a_dpfifo_7db1:dpfifo|altsyncram_o1k1:FIFOram ; altsyncram_o1k1 ; work ;
|
||||
; |cntr_g2b:rd_ptr_msb| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_1hk1:auto_generated|a_dpfifo_7db1:dpfifo|cntr_g2b:rd_ptr_msb ; cntr_g2b ; work ;
|
||||
; |cntr_h2b:wr_ptr| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_1hk1:auto_generated|a_dpfifo_7db1:dpfifo|cntr_h2b:wr_ptr ; cntr_h2b ; work ;
|
||||
; |cntr_t27:usedw_counter| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_1hk1:auto_generated|a_dpfifo_7db1:dpfifo|cntr_t27:usedw_counter ; cntr_t27 ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 14080 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 14080 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_3ov3:auto_generated| ; 0 (0) ; 0 (0) ; 14080 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_3ov3:auto_generated ; altsyncram_3ov3 ; work ;
|
||||
; |mem_ctrl:sample_mem_ctrl_inst| ; 47 (7) ; 23 (2) ; 4032 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 40 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 40 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_sgk1:auto_generated| ; 40 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated ; scfifo_sgk1 ; work ;
|
||||
; |a_dpfifo_2db1:dpfifo| ; 40 (26) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo ; a_dpfifo_2db1 ; work ;
|
||||
; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ;
|
||||
; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ;
|
||||
; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ;
|
||||
; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 3520 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 3520 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_rnv3:auto_generated| ; 0 (0) ; 0 (0) ; 3520 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:0:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_rnv3:auto_generated ; altsyncram_rnv3 ; work ;
|
||||
; |dds_reader:\dds_endpoint_gen:1:dds_reader_inst| ; 2363 (2258) ; 605 (551) ; 18752 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst ; dds_reader ; work ;
|
||||
; |mem_ctrl:payload_mem_ctrl_inst| ; 60 (15) ; 31 (2) ; 14720 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 45 (1) ; 29 (0) ; 2048 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 44 (0) ; 29 (0) ; 2048 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_6hk1:auto_generated| ; 44 (0) ; 29 (0) ; 2048 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_6hk1:auto_generated ; scfifo_6hk1 ; work ;
|
||||
; |a_dpfifo_cdb1:dpfifo| ; 44 (24) ; 29 (12) ; 2048 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_6hk1:auto_generated|a_dpfifo_cdb1:dpfifo ; a_dpfifo_cdb1 ; work ;
|
||||
; |altsyncram_o1k1:FIFOram| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_6hk1:auto_generated|a_dpfifo_cdb1:dpfifo|altsyncram_o1k1:FIFOram ; altsyncram_o1k1 ; work ;
|
||||
; |cntr_g2b:rd_ptr_msb| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_6hk1:auto_generated|a_dpfifo_cdb1:dpfifo|cntr_g2b:rd_ptr_msb ; cntr_g2b ; work ;
|
||||
; |cntr_h2b:wr_ptr| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_6hk1:auto_generated|a_dpfifo_cdb1:dpfifo|cntr_h2b:wr_ptr ; cntr_h2b ; work ;
|
||||
; |cntr_t27:usedw_counter| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_6hk1:auto_generated|a_dpfifo_cdb1:dpfifo|cntr_t27:usedw_counter ; cntr_t27 ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 12672 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 12672 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_dov3:auto_generated| ; 0 (0) ; 0 (0) ; 12672 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_dov3:auto_generated ; altsyncram_dov3 ; work ;
|
||||
; |mem_ctrl:sample_mem_ctrl_inst| ; 45 (7) ; 23 (2) ; 4032 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 38 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 38 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_sgk1:auto_generated| ; 38 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated ; scfifo_sgk1 ; work ;
|
||||
; |a_dpfifo_2db1:dpfifo| ; 38 (24) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo ; a_dpfifo_2db1 ; work ;
|
||||
; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ;
|
||||
; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ;
|
||||
; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ;
|
||||
; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 3520 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 3520 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_rnv3:auto_generated| ; 0 (0) ; 0 (0) ; 3520 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:1:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_rnv3:auto_generated ; altsyncram_rnv3 ; work ;
|
||||
; |dds_reader:\dds_endpoint_gen:2:dds_reader_inst| ; 2372 (2266) ; 605 (551) ; 21568 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst ; dds_reader ; work ;
|
||||
; |mem_ctrl:payload_mem_ctrl_inst| ; 61 (15) ; 31 (2) ; 17536 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 46 (2) ; 29 (0) ; 2048 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 44 (0) ; 29 (0) ; 2048 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_7hk1:auto_generated| ; 44 (0) ; 29 (0) ; 2048 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_7hk1:auto_generated ; scfifo_7hk1 ; work ;
|
||||
; |a_dpfifo_ddb1:dpfifo| ; 44 (24) ; 29 (12) ; 2048 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_7hk1:auto_generated|a_dpfifo_ddb1:dpfifo ; a_dpfifo_ddb1 ; work ;
|
||||
; |altsyncram_o1k1:FIFOram| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_7hk1:auto_generated|a_dpfifo_ddb1:dpfifo|altsyncram_o1k1:FIFOram ; altsyncram_o1k1 ; work ;
|
||||
; |cntr_g2b:rd_ptr_msb| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_7hk1:auto_generated|a_dpfifo_ddb1:dpfifo|cntr_g2b:rd_ptr_msb ; cntr_g2b ; work ;
|
||||
; |cntr_h2b:wr_ptr| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_7hk1:auto_generated|a_dpfifo_ddb1:dpfifo|cntr_h2b:wr_ptr ; cntr_h2b ; work ;
|
||||
; |cntr_t27:usedw_counter| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_7hk1:auto_generated|a_dpfifo_ddb1:dpfifo|cntr_t27:usedw_counter ; cntr_t27 ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 15488 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 15488 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_bov3:auto_generated| ; 0 (0) ; 0 (0) ; 15488 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_bov3:auto_generated ; altsyncram_bov3 ; work ;
|
||||
; |mem_ctrl:sample_mem_ctrl_inst| ; 45 (7) ; 23 (2) ; 4032 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 38 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 38 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_sgk1:auto_generated| ; 38 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated ; scfifo_sgk1 ; work ;
|
||||
; |a_dpfifo_2db1:dpfifo| ; 38 (24) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo ; a_dpfifo_2db1 ; work ;
|
||||
; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ;
|
||||
; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ;
|
||||
; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ;
|
||||
; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_sgk1:auto_generated|a_dpfifo_2db1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 3520 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 3520 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_rnv3:auto_generated| ; 0 (0) ; 0 (0) ; 3520 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_reader:\dds_endpoint_gen:2:dds_reader_inst|mem_ctrl:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_rnv3:auto_generated ; altsyncram_rnv3 ; work ;
|
||||
; |dds_writer:\dds_endpoint_w_if:dds_writer_inst| ; 6798 (4926) ; 4149 (1812) ; 428928 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst ; dds_writer ; work ;
|
||||
; |key_holder:\key_holder_gen:0:key_holder_inst| ; 217 (184) ; 384 (249) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|key_holder:\key_holder_gen:0:key_holder_inst ; key_holder ; work ;
|
||||
; |key_hash_generator:key_hash_generator_inst| ; 33 (33) ; 135 (135) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|key_holder:\key_holder_gen:0:key_holder_inst|key_hash_generator:key_hash_generator_inst ; key_hash_generator ; work ;
|
||||
; |key_holder:\key_holder_gen:1:key_holder_inst| ; 215 (183) ; 384 (249) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|key_holder:\key_holder_gen:1:key_holder_inst ; key_holder ; work ;
|
||||
; |key_hash_generator:key_hash_generator_inst| ; 32 (32) ; 135 (135) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|key_holder:\key_holder_gen:1:key_holder_inst|key_hash_generator:key_hash_generator_inst ; key_hash_generator ; work ;
|
||||
; |key_holder:\key_holder_gen:2:key_holder_inst| ; 217 (182) ; 384 (249) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|key_holder:\key_holder_gen:2:key_holder_inst ; key_holder ; work ;
|
||||
; |key_hash_generator:key_hash_generator_inst| ; 35 (35) ; 135 (135) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|key_holder:\key_holder_gen:2:key_holder_inst|key_hash_generator:key_hash_generator_inst ; key_hash_generator ; work ;
|
||||
; |key_holder:\key_holder_gen:3:key_holder_inst| ; 215 (183) ; 384 (249) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|key_holder:\key_holder_gen:3:key_holder_inst ; key_holder ; work ;
|
||||
; |key_hash_generator:key_hash_generator_inst| ; 32 (32) ; 135 (135) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|key_holder:\key_holder_gen:3:key_holder_inst|key_hash_generator:key_hash_generator_inst ; key_hash_generator ; work ;
|
||||
; |key_holder:\key_holder_gen:4:key_holder_inst| ; 214 (181) ; 384 (249) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|key_holder:\key_holder_gen:4:key_holder_inst ; key_holder ; work ;
|
||||
; |key_hash_generator:key_hash_generator_inst| ; 33 (33) ; 135 (135) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|key_holder:\key_holder_gen:4:key_holder_inst|key_hash_generator:key_hash_generator_inst ; key_hash_generator ; work ;
|
||||
; |mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst| ; 40 (7) ; 23 (2) ; 800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_kfk1:auto_generated| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated ; scfifo_kfk1 ; work ;
|
||||
; |a_dpfifo_qbb1:dpfifo| ; 33 (19) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo ; a_dpfifo_qbb1 ; work ;
|
||||
; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ;
|
||||
; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ;
|
||||
; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ;
|
||||
; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_vkv3:auto_generated| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:0:instance_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_vkv3:auto_generated ; altsyncram_vkv3 ; work ;
|
||||
; |mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst| ; 38 (5) ; 23 (2) ; 800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_kfk1:auto_generated| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated ; scfifo_kfk1 ; work ;
|
||||
; |a_dpfifo_qbb1:dpfifo| ; 33 (19) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo ; a_dpfifo_qbb1 ; work ;
|
||||
; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ;
|
||||
; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ;
|
||||
; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ;
|
||||
; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_vkv3:auto_generated| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:1:instance_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_vkv3:auto_generated ; altsyncram_vkv3 ; work ;
|
||||
; |mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst| ; 38 (5) ; 23 (2) ; 800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_kfk1:auto_generated| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated ; scfifo_kfk1 ; work ;
|
||||
; |a_dpfifo_qbb1:dpfifo| ; 33 (19) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo ; a_dpfifo_qbb1 ; work ;
|
||||
; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ;
|
||||
; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ;
|
||||
; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ;
|
||||
; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_vkv3:auto_generated| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:2:instance_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_vkv3:auto_generated ; altsyncram_vkv3 ; work ;
|
||||
; |mem_ctrl:\instance_mem_ctrl_gen:3:instance_mem_ctrl_inst| ; 38 (5) ; 23 (2) ; 800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:3:instance_mem_ctrl_inst ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:3:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:3:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_kfk1:auto_generated| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:3:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated ; scfifo_kfk1 ; work ;
|
||||
; |a_dpfifo_qbb1:dpfifo| ; 33 (19) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:3:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo ; a_dpfifo_qbb1 ; work ;
|
||||
; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:3:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ;
|
||||
; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:3:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ;
|
||||
; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:3:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ;
|
||||
; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:3:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:3:instance_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:3:instance_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_vkv3:auto_generated| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:3:instance_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_vkv3:auto_generated ; altsyncram_vkv3 ; work ;
|
||||
; |mem_ctrl:\instance_mem_ctrl_gen:4:instance_mem_ctrl_inst| ; 38 (5) ; 23 (2) ; 800 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:4:instance_mem_ctrl_inst ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:4:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:4:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_kfk1:auto_generated| ; 33 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:4:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated ; scfifo_kfk1 ; work ;
|
||||
; |a_dpfifo_qbb1:dpfifo| ; 33 (19) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:4:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo ; a_dpfifo_qbb1 ; work ;
|
||||
; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:4:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ;
|
||||
; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:4:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ;
|
||||
; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:4:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ;
|
||||
; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:4:instance_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:4:instance_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:4:instance_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_vkv3:auto_generated| ; 0 (0) ; 0 (0) ; 288 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\instance_mem_ctrl_gen:4:instance_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_vkv3:auto_generated ; altsyncram_vkv3 ; work ;
|
||||
; |mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst| ; 40 (6) ; 23 (2) ; 3680 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 34 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 34 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_kfk1:auto_generated| ; 34 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated ; scfifo_kfk1 ; work ;
|
||||
; |a_dpfifo_qbb1:dpfifo| ; 34 (20) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo ; a_dpfifo_qbb1 ; work ;
|
||||
; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ;
|
||||
; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ;
|
||||
; |cntr_f2b:wr_ptr| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ;
|
||||
; |cntr_r27:usedw_counter| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_kfk1:auto_generated|a_dpfifo_qbb1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 3168 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 3168 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_aov3:auto_generated| ; 0 (0) ; 0 (0) ; 3168 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:0:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_aov3:auto_generated ; altsyncram_aov3 ; work ;
|
||||
; |mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst| ; 69 (14) ; 35 (2) ; 41760 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 55 (5) ; 33 (0) ; 4096 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 50 (0) ; 33 (0) ; 4096 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_oik1:auto_generated| ; 50 (0) ; 33 (0) ; 4096 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_oik1:auto_generated ; scfifo_oik1 ; work ;
|
||||
; |a_dpfifo_ueb1:dpfifo| ; 50 (27) ; 33 (13) ; 4096 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_oik1:auto_generated|a_dpfifo_ueb1:dpfifo ; a_dpfifo_ueb1 ; work ;
|
||||
; |altsyncram_s4k1:FIFOram| ; 0 (0) ; 0 (0) ; 4096 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_oik1:auto_generated|a_dpfifo_ueb1:dpfifo|altsyncram_s4k1:FIFOram ; altsyncram_s4k1 ; work ;
|
||||
; |cntr_h2b:rd_ptr_msb| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_oik1:auto_generated|a_dpfifo_ueb1:dpfifo|cntr_h2b:rd_ptr_msb ; cntr_h2b ; work ;
|
||||
; |cntr_i2b:wr_ptr| ; 8 (8) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_oik1:auto_generated|a_dpfifo_ueb1:dpfifo|cntr_i2b:wr_ptr ; cntr_i2b ; work ;
|
||||
; |cntr_u27:usedw_counter| ; 8 (8) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_oik1:auto_generated|a_dpfifo_ueb1:dpfifo|cntr_u27:usedw_counter ; cntr_u27 ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 37664 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 37664 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_6rv3:auto_generated| ; 0 (0) ; 0 (0) ; 37664 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:1:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_6rv3:auto_generated ; altsyncram_6rv3 ; work ;
|
||||
; |mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst| ; 90 (19) ; 47 (2) ; 246432 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 71 (5) ; 45 (0) ; 32768 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 66 (0) ; 45 (0) ; 32768 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_5kk1:auto_generated| ; 66 (0) ; 45 (0) ; 32768 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_5kk1:auto_generated ; scfifo_5kk1 ; work ;
|
||||
; |a_dpfifo_bgb1:dpfifo| ; 66 (34) ; 45 (16) ; 32768 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_5kk1:auto_generated|a_dpfifo_bgb1:dpfifo ; a_dpfifo_bgb1 ; work ;
|
||||
; |altsyncram_8ak1:FIFOram| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_5kk1:auto_generated|a_dpfifo_bgb1:dpfifo|altsyncram_8ak1:FIFOram ; altsyncram_8ak1 ; work ;
|
||||
; |cntr_847:usedw_counter| ; 11 (11) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_5kk1:auto_generated|a_dpfifo_bgb1:dpfifo|cntr_847:usedw_counter ; cntr_847 ; work ;
|
||||
; |cntr_k2b:rd_ptr_msb| ; 10 (10) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_5kk1:auto_generated|a_dpfifo_bgb1:dpfifo|cntr_k2b:rd_ptr_msb ; cntr_k2b ; work ;
|
||||
; |cntr_s3b:wr_ptr| ; 11 (11) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_5kk1:auto_generated|a_dpfifo_bgb1:dpfifo|cntr_s3b:wr_ptr ; cntr_s3b ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 213664 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 213664 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_grv3:auto_generated| ; 0 (0) ; 0 (0) ; 213664 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:2:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_grv3:auto_generated ; altsyncram_grv3 ; work ;
|
||||
; |mem_ctrl:\payload_mem_ctrl_gen:3:payload_mem_ctrl_inst| ; 72 (15) ; 35 (2) ; 41408 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:3:payload_mem_ctrl_inst ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 57 (7) ; 33 (0) ; 4096 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:3:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 50 (0) ; 33 (0) ; 4096 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:3:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_pik1:auto_generated| ; 50 (0) ; 33 (0) ; 4096 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:3:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_pik1:auto_generated ; scfifo_pik1 ; work ;
|
||||
; |a_dpfifo_veb1:dpfifo| ; 50 (27) ; 33 (13) ; 4096 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:3:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_pik1:auto_generated|a_dpfifo_veb1:dpfifo ; a_dpfifo_veb1 ; work ;
|
||||
; |altsyncram_s4k1:FIFOram| ; 0 (0) ; 0 (0) ; 4096 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:3:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_pik1:auto_generated|a_dpfifo_veb1:dpfifo|altsyncram_s4k1:FIFOram ; altsyncram_s4k1 ; work ;
|
||||
; |cntr_h2b:rd_ptr_msb| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:3:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_pik1:auto_generated|a_dpfifo_veb1:dpfifo|cntr_h2b:rd_ptr_msb ; cntr_h2b ; work ;
|
||||
; |cntr_i2b:wr_ptr| ; 8 (8) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:3:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_pik1:auto_generated|a_dpfifo_veb1:dpfifo|cntr_i2b:wr_ptr ; cntr_i2b ; work ;
|
||||
; |cntr_u27:usedw_counter| ; 8 (8) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:3:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_pik1:auto_generated|a_dpfifo_veb1:dpfifo|cntr_u27:usedw_counter ; cntr_u27 ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 37312 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:3:payload_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 37312 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:3:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_5rv3:auto_generated| ; 0 (0) ; 0 (0) ; 37312 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:3:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_5rv3:auto_generated ; altsyncram_5rv3 ; work ;
|
||||
; |mem_ctrl:\payload_mem_ctrl_gen:4:payload_mem_ctrl_inst| ; 90 (17) ; 47 (2) ; 72896 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:4:payload_mem_ctrl_inst ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 73 (8) ; 45 (0) ; 32768 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:4:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 65 (0) ; 45 (0) ; 32768 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:4:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_7kk1:auto_generated| ; 65 (0) ; 45 (0) ; 32768 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:4:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_7kk1:auto_generated ; scfifo_7kk1 ; work ;
|
||||
; |a_dpfifo_dgb1:dpfifo| ; 65 (33) ; 45 (16) ; 32768 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:4:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_7kk1:auto_generated|a_dpfifo_dgb1:dpfifo ; a_dpfifo_dgb1 ; work ;
|
||||
; |altsyncram_8ak1:FIFOram| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:4:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_7kk1:auto_generated|a_dpfifo_dgb1:dpfifo|altsyncram_8ak1:FIFOram ; altsyncram_8ak1 ; work ;
|
||||
; |cntr_847:usedw_counter| ; 11 (11) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:4:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_7kk1:auto_generated|a_dpfifo_dgb1:dpfifo|cntr_847:usedw_counter ; cntr_847 ; work ;
|
||||
; |cntr_k2b:rd_ptr_msb| ; 10 (10) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:4:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_7kk1:auto_generated|a_dpfifo_dgb1:dpfifo|cntr_k2b:rd_ptr_msb ; cntr_k2b ; work ;
|
||||
; |cntr_s3b:wr_ptr| ; 11 (11) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:4:payload_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_7kk1:auto_generated|a_dpfifo_dgb1:dpfifo|cntr_s3b:wr_ptr ; cntr_s3b ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 40128 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:4:payload_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 40128 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:4:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_7rv3:auto_generated| ; 0 (0) ; 0 (0) ; 40128 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\payload_mem_ctrl_gen:4:payload_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_7rv3:auto_generated ; altsyncram_7rv3 ; work ;
|
||||
; |mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst| ; 50 (9) ; 23 (2) ; 4384 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 41 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 41 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_tgk1:auto_generated| ; 41 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated ; scfifo_tgk1 ; work ;
|
||||
; |a_dpfifo_3db1:dpfifo| ; 41 (25) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo ; a_dpfifo_3db1 ; work ;
|
||||
; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ;
|
||||
; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ;
|
||||
; |cntr_f2b:wr_ptr| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ;
|
||||
; |cntr_r27:usedw_counter| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_tnv3:auto_generated| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:0:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_tnv3:auto_generated ; altsyncram_tnv3 ; work ;
|
||||
; |mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst| ; 48 (7) ; 23 (2) ; 4384 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 41 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 41 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_tgk1:auto_generated| ; 41 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated ; scfifo_tgk1 ; work ;
|
||||
; |a_dpfifo_3db1:dpfifo| ; 41 (25) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo ; a_dpfifo_3db1 ; work ;
|
||||
; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ;
|
||||
; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ;
|
||||
; |cntr_f2b:wr_ptr| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ;
|
||||
; |cntr_r27:usedw_counter| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_tnv3:auto_generated| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:1:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_tnv3:auto_generated ; altsyncram_tnv3 ; work ;
|
||||
; |mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst| ; 48 (7) ; 23 (2) ; 4384 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 41 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 41 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_tgk1:auto_generated| ; 41 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated ; scfifo_tgk1 ; work ;
|
||||
; |a_dpfifo_3db1:dpfifo| ; 41 (25) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo ; a_dpfifo_3db1 ; work ;
|
||||
; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ;
|
||||
; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ;
|
||||
; |cntr_f2b:wr_ptr| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ;
|
||||
; |cntr_r27:usedw_counter| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_tnv3:auto_generated| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:2:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_tnv3:auto_generated ; altsyncram_tnv3 ; work ;
|
||||
; |mem_ctrl:\sample_mem_ctrl_gen:3:sample_mem_ctrl_inst| ; 48 (7) ; 23 (2) ; 4384 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:3:sample_mem_ctrl_inst ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 41 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:3:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 41 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:3:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_tgk1:auto_generated| ; 41 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:3:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated ; scfifo_tgk1 ; work ;
|
||||
; |a_dpfifo_3db1:dpfifo| ; 41 (25) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:3:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo ; a_dpfifo_3db1 ; work ;
|
||||
; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:3:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ;
|
||||
; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:3:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ;
|
||||
; |cntr_f2b:wr_ptr| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:3:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ;
|
||||
; |cntr_r27:usedw_counter| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:3:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:3:sample_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:3:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_tnv3:auto_generated| ; 0 (0) ; 0 (0) ; 3872 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:3:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_tnv3:auto_generated ; altsyncram_tnv3 ; work ;
|
||||
; |mem_ctrl:\sample_mem_ctrl_gen:4:sample_mem_ctrl_inst| ; 47 (7) ; 23 (2) ; 1216 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:4:sample_mem_ctrl_inst ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 40 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:4:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 40 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:4:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_tgk1:auto_generated| ; 40 (0) ; 21 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:4:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated ; scfifo_tgk1 ; work ;
|
||||
; |a_dpfifo_3db1:dpfifo| ; 40 (24) ; 21 (10) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:4:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo ; a_dpfifo_3db1 ; work ;
|
||||
; |altsyncram_e1k1:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:4:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|altsyncram_e1k1:FIFOram ; altsyncram_e1k1 ; work ;
|
||||
; |cntr_e2b:rd_ptr_msb| ; 4 (4) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:4:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_e2b:rd_ptr_msb ; cntr_e2b ; work ;
|
||||
; |cntr_f2b:wr_ptr| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:4:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_f2b:wr_ptr ; cntr_f2b ; work ;
|
||||
; |cntr_r27:usedw_counter| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:4:sample_mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_tgk1:auto_generated|a_dpfifo_3db1:dpfifo|cntr_r27:usedw_counter ; cntr_r27 ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 704 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:4:sample_mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 704 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:4:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_fmv3:auto_generated| ; 0 (0) ; 0 (0) ; 704 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|dds_writer:\dds_endpoint_w_if:dds_writer_inst|mem_ctrl:\sample_mem_ctrl_gen:4:sample_mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_fmv3:auto_generated ; altsyncram_fmv3 ; work ;
|
||||
; |ros_static_discovery_writer:ros_discovery_writer_inst| ; 51 (51) ; 12 (12) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|ros_static_discovery_writer:ros_discovery_writer_inst ; ros_static_discovery_writer ; work ;
|
||||
; |ros_time_converter:ros_time_converter_inst| ; 122 (63) ; 240 (95) ; 0 ; 4 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|ros_time_converter:ros_time_converter_inst ; ros_time_converter ; work ;
|
||||
; |mult:mult_inst| ; 59 (0) ; 145 (0) ; 0 ; 4 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|ros_time_converter:ros_time_converter_inst|mult:mult_inst ; mult ; work ;
|
||||
; |lpm_mult:lpm_mult_component| ; 59 (0) ; 145 (0) ; 0 ; 4 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|ros_time_converter:ros_time_converter_inst|mult:mult_inst|lpm_mult:lpm_mult_component ; lpm_mult ; work ;
|
||||
; |mult_ilr:auto_generated| ; 59 (59) ; 145 (145) ; 0 ; 4 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|ros_time_converter:ros_time_converter_inst|mult:mult_inst|lpm_mult:lpm_mult_component|mult_ilr:auto_generated ; mult_ilr ; work ;
|
||||
; |rtps_discovery_module:rtps_discovery_module_inst| ; 8804 (8757) ; 3240 (3213) ; 41024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_discovery_module:rtps_discovery_module_inst ; rtps_discovery_module ; work ;
|
||||
; |mem_ctrl:mem_ctrl_inst| ; 47 (6) ; 27 (2) ; 41024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_discovery_module:rtps_discovery_module_inst|mem_ctrl:mem_ctrl_inst ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 41 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_discovery_module:rtps_discovery_module_inst|mem_ctrl:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 41 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_discovery_module:rtps_discovery_module_inst|mem_ctrl:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_3hk1:auto_generated| ; 41 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_discovery_module:rtps_discovery_module_inst|mem_ctrl:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_3hk1:auto_generated ; scfifo_3hk1 ; work ;
|
||||
; |a_dpfifo_9db1:dpfifo| ; 41 (24) ; 25 (11) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_discovery_module:rtps_discovery_module_inst|mem_ctrl:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_3hk1:auto_generated|a_dpfifo_9db1:dpfifo ; a_dpfifo_9db1 ; work ;
|
||||
; |altsyncram_c1k1:FIFOram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_discovery_module:rtps_discovery_module_inst|mem_ctrl:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_3hk1:auto_generated|a_dpfifo_9db1:dpfifo|altsyncram_c1k1:FIFOram ; altsyncram_c1k1 ; work ;
|
||||
; |cntr_f2b:rd_ptr_msb| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_discovery_module:rtps_discovery_module_inst|mem_ctrl:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_3hk1:auto_generated|a_dpfifo_9db1:dpfifo|cntr_f2b:rd_ptr_msb ; cntr_f2b ; work ;
|
||||
; |cntr_g2b:wr_ptr| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_discovery_module:rtps_discovery_module_inst|mem_ctrl:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_3hk1:auto_generated|a_dpfifo_9db1:dpfifo|cntr_g2b:wr_ptr ; cntr_g2b ; work ;
|
||||
; |cntr_s27:usedw_counter| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_discovery_module:rtps_discovery_module_inst|mem_ctrl:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_3hk1:auto_generated|a_dpfifo_9db1:dpfifo|cntr_s27:usedw_counter ; cntr_s27 ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 40000 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_discovery_module:rtps_discovery_module_inst|mem_ctrl:mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 40000 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_discovery_module:rtps_discovery_module_inst|mem_ctrl:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_sqv3:auto_generated| ; 0 (0) ; 0 (0) ; 40000 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_discovery_module:rtps_discovery_module_inst|mem_ctrl:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_sqv3:auto_generated ; altsyncram_sqv3 ; work ;
|
||||
; |rtps_handler:rtps_handler_inst| ; 1633 (1633) ; 964 (964) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_handler:rtps_handler_inst ; rtps_handler ; work ;
|
||||
; |rtps_out:rtps_out_inst| ; 370 (316) ; 185 (173) ; 524256 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst ; rtps_out ; work ;
|
||||
; |dp_mem_ctrl:buffer_inst| ; 54 (3) ; 12 (2) ; 524256 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst ; dp_mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 15 (0) ; 9 (0) ; 64 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 15 (0) ; 9 (0) ; 64 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_afk1:auto_generated| ; 15 (0) ; 9 (0) ; 64 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_afk1:auto_generated ; scfifo_afk1 ; work ;
|
||||
; |a_dpfifo_gbb1:dpfifo| ; 15 (11) ; 9 (7) ; 64 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_afk1:auto_generated|a_dpfifo_gbb1:dpfifo ; a_dpfifo_gbb1 ; work ;
|
||||
; |altsyncram_utj1:FIFOram| ; 0 (0) ; 0 (0) ; 64 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_afk1:auto_generated|a_dpfifo_gbb1:dpfifo|altsyncram_utj1:FIFOram ; altsyncram_utj1 ; work ;
|
||||
; |cntr_c2b:wr_ptr| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_afk1:auto_generated|a_dpfifo_gbb1:dpfifo|cntr_c2b:wr_ptr ; cntr_c2b ; work ;
|
||||
; |cntr_o27:usedw_counter| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_afk1:auto_generated|a_dpfifo_gbb1:dpfifo|cntr_o27:usedw_counter ; cntr_o27 ; work ;
|
||||
; |dual_port_ram:ram_inst| ; 36 (0) ; 1 (0) ; 524192 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst|dual_port_ram:ram_inst ; dual_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 36 (0) ; 1 (0) ; 524192 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst|dual_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_1qv3:auto_generated| ; 36 (0) ; 1 (1) ; 524192 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst|dual_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_1qv3:auto_generated ; altsyncram_1qv3 ; work ;
|
||||
; |decode_5la:rden_decode_b| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst|dual_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_1qv3:auto_generated|decode_5la:rden_decode_b ; decode_5la ; work ;
|
||||
; |decode_5la:wren_decode_a| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst|dual_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_1qv3:auto_generated|decode_5la:wren_decode_a ; decode_5la ; work ;
|
||||
; |mux_2hb:mux3| ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_out:rtps_out_inst|dp_mem_ctrl:buffer_inst|dual_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_1qv3:auto_generated|mux_2hb:mux3 ; mux_2hb ; work ;
|
||||
; |rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst| ; 5381 (5249) ; 2360 (2279) ; 84672 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst ; rtps_reader ; work ;
|
||||
; |mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst| ; 44 (6) ; 27 (2) ; 28224 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_4hk1:auto_generated| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated ; scfifo_4hk1 ; work ;
|
||||
; |a_dpfifo_adb1:dpfifo| ; 38 (21) ; 25 (11) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo ; a_dpfifo_adb1 ; work ;
|
||||
; |altsyncram_c1k1:FIFOram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|altsyncram_c1k1:FIFOram ; altsyncram_c1k1 ; work ;
|
||||
; |cntr_f2b:rd_ptr_msb| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_f2b:rd_ptr_msb ; cntr_f2b ; work ;
|
||||
; |cntr_g2b:wr_ptr| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_g2b:wr_ptr ; cntr_g2b ; work ;
|
||||
; |cntr_s27:usedw_counter| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_s27:usedw_counter ; cntr_s27 ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_gpv3:auto_generated| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_gpv3:auto_generated ; altsyncram_gpv3 ; work ;
|
||||
; |mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst| ; 44 (6) ; 27 (2) ; 28224 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_4hk1:auto_generated| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated ; scfifo_4hk1 ; work ;
|
||||
; |a_dpfifo_adb1:dpfifo| ; 38 (21) ; 25 (11) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo ; a_dpfifo_adb1 ; work ;
|
||||
; |altsyncram_c1k1:FIFOram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|altsyncram_c1k1:FIFOram ; altsyncram_c1k1 ; work ;
|
||||
; |cntr_f2b:rd_ptr_msb| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_f2b:rd_ptr_msb ; cntr_f2b ; work ;
|
||||
; |cntr_g2b:wr_ptr| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_g2b:wr_ptr ; cntr_g2b ; work ;
|
||||
; |cntr_s27:usedw_counter| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_s27:usedw_counter ; cntr_s27 ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_gpv3:auto_generated| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_gpv3:auto_generated ; altsyncram_gpv3 ; work ;
|
||||
; |mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst| ; 44 (6) ; 27 (2) ; 28224 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_4hk1:auto_generated| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated ; scfifo_4hk1 ; work ;
|
||||
; |a_dpfifo_adb1:dpfifo| ; 38 (21) ; 25 (11) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo ; a_dpfifo_adb1 ; work ;
|
||||
; |altsyncram_c1k1:FIFOram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|altsyncram_c1k1:FIFOram ; altsyncram_c1k1 ; work ;
|
||||
; |cntr_f2b:rd_ptr_msb| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_f2b:rd_ptr_msb ; cntr_f2b ; work ;
|
||||
; |cntr_g2b:wr_ptr| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_g2b:wr_ptr ; cntr_g2b ; work ;
|
||||
; |cntr_s27:usedw_counter| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_s27:usedw_counter ; cntr_s27 ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_gpv3:auto_generated| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_reader:\rtps_endpoint_r_if:rtps_reader_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_gpv3:auto_generated ; altsyncram_gpv3 ; work ;
|
||||
; |rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst| ; 6872 (6612) ; 3150 (2988) ; 169344 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst ; rtps_writer ; work ;
|
||||
; |mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst| ; 45 (7) ; 27 (2) ; 28224 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_4hk1:auto_generated| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated ; scfifo_4hk1 ; work ;
|
||||
; |a_dpfifo_adb1:dpfifo| ; 38 (21) ; 25 (11) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo ; a_dpfifo_adb1 ; work ;
|
||||
; |altsyncram_c1k1:FIFOram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|altsyncram_c1k1:FIFOram ; altsyncram_c1k1 ; work ;
|
||||
; |cntr_f2b:rd_ptr_msb| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_f2b:rd_ptr_msb ; cntr_f2b ; work ;
|
||||
; |cntr_g2b:wr_ptr| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_g2b:wr_ptr ; cntr_g2b ; work ;
|
||||
; |cntr_s27:usedw_counter| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_s27:usedw_counter ; cntr_s27 ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_gpv3:auto_generated| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:0:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_gpv3:auto_generated ; altsyncram_gpv3 ; work ;
|
||||
; |mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst| ; 43 (5) ; 27 (2) ; 28224 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_4hk1:auto_generated| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated ; scfifo_4hk1 ; work ;
|
||||
; |a_dpfifo_adb1:dpfifo| ; 38 (21) ; 25 (11) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo ; a_dpfifo_adb1 ; work ;
|
||||
; |altsyncram_c1k1:FIFOram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|altsyncram_c1k1:FIFOram ; altsyncram_c1k1 ; work ;
|
||||
; |cntr_f2b:rd_ptr_msb| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_f2b:rd_ptr_msb ; cntr_f2b ; work ;
|
||||
; |cntr_g2b:wr_ptr| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_g2b:wr_ptr ; cntr_g2b ; work ;
|
||||
; |cntr_s27:usedw_counter| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_s27:usedw_counter ; cntr_s27 ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_gpv3:auto_generated| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:1:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_gpv3:auto_generated ; altsyncram_gpv3 ; work ;
|
||||
; |mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst| ; 43 (5) ; 27 (2) ; 28224 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_4hk1:auto_generated| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated ; scfifo_4hk1 ; work ;
|
||||
; |a_dpfifo_adb1:dpfifo| ; 38 (21) ; 25 (11) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo ; a_dpfifo_adb1 ; work ;
|
||||
; |altsyncram_c1k1:FIFOram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|altsyncram_c1k1:FIFOram ; altsyncram_c1k1 ; work ;
|
||||
; |cntr_f2b:rd_ptr_msb| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_f2b:rd_ptr_msb ; cntr_f2b ; work ;
|
||||
; |cntr_g2b:wr_ptr| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_g2b:wr_ptr ; cntr_g2b ; work ;
|
||||
; |cntr_s27:usedw_counter| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_s27:usedw_counter ; cntr_s27 ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_gpv3:auto_generated| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:2:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_gpv3:auto_generated ; altsyncram_gpv3 ; work ;
|
||||
; |mem_ctrl:\mem_ctrl_gen:3:mem_ctrl_inst| ; 43 (5) ; 27 (2) ; 28224 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:3:mem_ctrl_inst ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:3:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:3:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_4hk1:auto_generated| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:3:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated ; scfifo_4hk1 ; work ;
|
||||
; |a_dpfifo_adb1:dpfifo| ; 38 (21) ; 25 (11) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:3:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo ; a_dpfifo_adb1 ; work ;
|
||||
; |altsyncram_c1k1:FIFOram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:3:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|altsyncram_c1k1:FIFOram ; altsyncram_c1k1 ; work ;
|
||||
; |cntr_f2b:rd_ptr_msb| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:3:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_f2b:rd_ptr_msb ; cntr_f2b ; work ;
|
||||
; |cntr_g2b:wr_ptr| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:3:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_g2b:wr_ptr ; cntr_g2b ; work ;
|
||||
; |cntr_s27:usedw_counter| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:3:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_s27:usedw_counter ; cntr_s27 ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:3:mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:3:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_gpv3:auto_generated| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:3:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_gpv3:auto_generated ; altsyncram_gpv3 ; work ;
|
||||
; |mem_ctrl:\mem_ctrl_gen:4:mem_ctrl_inst| ; 43 (5) ; 27 (2) ; 28224 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:4:mem_ctrl_inst ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:4:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:4:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_4hk1:auto_generated| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:4:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated ; scfifo_4hk1 ; work ;
|
||||
; |a_dpfifo_adb1:dpfifo| ; 38 (21) ; 25 (11) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:4:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo ; a_dpfifo_adb1 ; work ;
|
||||
; |altsyncram_c1k1:FIFOram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:4:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|altsyncram_c1k1:FIFOram ; altsyncram_c1k1 ; work ;
|
||||
; |cntr_f2b:rd_ptr_msb| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:4:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_f2b:rd_ptr_msb ; cntr_f2b ; work ;
|
||||
; |cntr_g2b:wr_ptr| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:4:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_g2b:wr_ptr ; cntr_g2b ; work ;
|
||||
; |cntr_s27:usedw_counter| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:4:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_s27:usedw_counter ; cntr_s27 ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:4:mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:4:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_gpv3:auto_generated| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:4:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_gpv3:auto_generated ; altsyncram_gpv3 ; work ;
|
||||
; |mem_ctrl:\mem_ctrl_gen:5:mem_ctrl_inst| ; 43 (5) ; 27 (2) ; 28224 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:5:mem_ctrl_inst ; mem_ctrl ; work ;
|
||||
; |FWFT_FIFO:burst_fifo_inst| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:5:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:5:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_4hk1:auto_generated| ; 38 (0) ; 25 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:5:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated ; scfifo_4hk1 ; work ;
|
||||
; |a_dpfifo_adb1:dpfifo| ; 38 (21) ; 25 (11) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:5:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo ; a_dpfifo_adb1 ; work ;
|
||||
; |altsyncram_c1k1:FIFOram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:5:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|altsyncram_c1k1:FIFOram ; altsyncram_c1k1 ; work ;
|
||||
; |cntr_f2b:rd_ptr_msb| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:5:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_f2b:rd_ptr_msb ; cntr_f2b ; work ;
|
||||
; |cntr_g2b:wr_ptr| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:5:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_g2b:wr_ptr ; cntr_g2b ; work ;
|
||||
; |cntr_s27:usedw_counter| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:5:mem_ctrl_inst|FWFT_FIFO:burst_fifo_inst|scfifo:scfifo_component|scfifo_4hk1:auto_generated|a_dpfifo_adb1:dpfifo|cntr_s27:usedw_counter ; cntr_s27 ; work ;
|
||||
; |single_port_ram:ram_inst| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:5:mem_ctrl_inst|single_port_ram:ram_inst ; single_port_ram ; work ;
|
||||
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:5:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component ; altsyncram ; work ;
|
||||
; |altsyncram_gpv3:auto_generated| ; 0 (0) ; 0 (0) ; 27200 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|rtps_writer:\rtps_endpoint_w_if:rtps_writer_inst|mem_ctrl:\mem_ctrl_gen:5:mem_ctrl_inst|single_port_ram:ram_inst|altsyncram:altsyncram_component|altsyncram_gpv3:auto_generated ; altsyncram_gpv3 ; work ;
|
||||
; |vector_FIFO:\fifo_in_re_r_if:fifo_in_re_inst| ; 32 (2) ; 18 (0) ; 72 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_r_if:fifo_in_re_inst ; vector_FIFO ; work ;
|
||||
; |FWFT_FIFO:fifo_main_inst| ; 15 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_r_if:fifo_in_re_inst|FWFT_FIFO:fifo_main_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 15 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_r_if:fifo_in_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_bfk1:auto_generated| ; 15 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_r_if:fifo_in_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated ; scfifo_bfk1 ; work ;
|
||||
; |a_dpfifo_hbb1:dpfifo| ; 15 (11) ; 9 (7) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_r_if:fifo_in_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo ; a_dpfifo_hbb1 ; work ;
|
||||
; |altsyncram_0uj1:FIFOram| ; 0 (0) ; 0 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_r_if:fifo_in_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|altsyncram_0uj1:FIFOram ; altsyncram_0uj1 ; work ;
|
||||
; |cntr_c2b:wr_ptr| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_r_if:fifo_in_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_c2b:wr_ptr ; cntr_c2b ; work ;
|
||||
; |cntr_o27:usedw_counter| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_r_if:fifo_in_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_o27:usedw_counter ; cntr_o27 ; work ;
|
||||
; |FWFT_FIFO:fifo_sup_inst| ; 15 (0) ; 9 (0) ; 6 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_r_if:fifo_in_re_inst|FWFT_FIFO:fifo_sup_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 15 (0) ; 9 (0) ; 6 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_r_if:fifo_in_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_odk1:auto_generated| ; 15 (0) ; 9 (0) ; 6 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_r_if:fifo_in_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_odk1:auto_generated ; scfifo_odk1 ; work ;
|
||||
; |a_dpfifo_u9b1:dpfifo| ; 15 (11) ; 9 (7) ; 6 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_r_if:fifo_in_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_odk1:auto_generated|a_dpfifo_u9b1:dpfifo ; a_dpfifo_u9b1 ; work ;
|
||||
; |altsyncram_qqj1:FIFOram| ; 0 (0) ; 0 (0) ; 6 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_r_if:fifo_in_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_odk1:auto_generated|a_dpfifo_u9b1:dpfifo|altsyncram_qqj1:FIFOram ; altsyncram_qqj1 ; work ;
|
||||
; |cntr_c2b:wr_ptr| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_r_if:fifo_in_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_odk1:auto_generated|a_dpfifo_u9b1:dpfifo|cntr_c2b:wr_ptr ; cntr_c2b ; work ;
|
||||
; |cntr_o27:usedw_counter| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_r_if:fifo_in_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_odk1:auto_generated|a_dpfifo_u9b1:dpfifo|cntr_o27:usedw_counter ; cntr_o27 ; work ;
|
||||
; |vector_FIFO:\fifo_in_re_w_if:fifo_in_re_inst| ; 37 (7) ; 18 (0) ; 78 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_w_if:fifo_in_re_inst ; vector_FIFO ; work ;
|
||||
; |FWFT_FIFO:fifo_main_inst| ; 15 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_w_if:fifo_in_re_inst|FWFT_FIFO:fifo_main_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 15 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_w_if:fifo_in_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_bfk1:auto_generated| ; 15 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_w_if:fifo_in_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated ; scfifo_bfk1 ; work ;
|
||||
; |a_dpfifo_hbb1:dpfifo| ; 15 (11) ; 9 (7) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_w_if:fifo_in_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo ; a_dpfifo_hbb1 ; work ;
|
||||
; |altsyncram_0uj1:FIFOram| ; 0 (0) ; 0 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_w_if:fifo_in_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|altsyncram_0uj1:FIFOram ; altsyncram_0uj1 ; work ;
|
||||
; |cntr_c2b:wr_ptr| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_w_if:fifo_in_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_c2b:wr_ptr ; cntr_c2b ; work ;
|
||||
; |cntr_o27:usedw_counter| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_w_if:fifo_in_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_o27:usedw_counter ; cntr_o27 ; work ;
|
||||
; |FWFT_FIFO:fifo_sup_inst| ; 15 (0) ; 9 (0) ; 12 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_w_if:fifo_in_re_inst|FWFT_FIFO:fifo_sup_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 15 (0) ; 9 (0) ; 12 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_w_if:fifo_in_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_rdk1:auto_generated| ; 15 (0) ; 9 (0) ; 12 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_w_if:fifo_in_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_rdk1:auto_generated ; scfifo_rdk1 ; work ;
|
||||
; |a_dpfifo_1ab1:dpfifo| ; 15 (11) ; 9 (7) ; 12 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_w_if:fifo_in_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_rdk1:auto_generated|a_dpfifo_1ab1:dpfifo ; a_dpfifo_1ab1 ; work ;
|
||||
; |altsyncram_0rj1:FIFOram| ; 0 (0) ; 0 (0) ; 12 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_w_if:fifo_in_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_rdk1:auto_generated|a_dpfifo_1ab1:dpfifo|altsyncram_0rj1:FIFOram ; altsyncram_0rj1 ; work ;
|
||||
; |cntr_c2b:wr_ptr| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_w_if:fifo_in_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_rdk1:auto_generated|a_dpfifo_1ab1:dpfifo|cntr_c2b:wr_ptr ; cntr_c2b ; work ;
|
||||
; |cntr_o27:usedw_counter| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_in_re_w_if:fifo_in_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_rdk1:auto_generated|a_dpfifo_1ab1:dpfifo|cntr_o27:usedw_counter ; cntr_o27 ; work ;
|
||||
; |vector_FIFO:\fifo_rb_re_r_if:fifo_rb_re_inst| ; 30 (0) ; 18 (0) ; 72 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_r_if:fifo_rb_re_inst ; vector_FIFO ; work ;
|
||||
; |FWFT_FIFO:fifo_main_inst| ; 15 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_r_if:fifo_rb_re_inst|FWFT_FIFO:fifo_main_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 15 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_r_if:fifo_rb_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_bfk1:auto_generated| ; 15 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_r_if:fifo_rb_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated ; scfifo_bfk1 ; work ;
|
||||
; |a_dpfifo_hbb1:dpfifo| ; 15 (11) ; 9 (7) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_r_if:fifo_rb_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo ; a_dpfifo_hbb1 ; work ;
|
||||
; |altsyncram_0uj1:FIFOram| ; 0 (0) ; 0 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_r_if:fifo_rb_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|altsyncram_0uj1:FIFOram ; altsyncram_0uj1 ; work ;
|
||||
; |cntr_c2b:wr_ptr| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_r_if:fifo_rb_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_c2b:wr_ptr ; cntr_c2b ; work ;
|
||||
; |cntr_o27:usedw_counter| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_r_if:fifo_rb_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_o27:usedw_counter ; cntr_o27 ; work ;
|
||||
; |FWFT_FIFO:fifo_sup_inst| ; 15 (0) ; 9 (0) ; 6 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_r_if:fifo_rb_re_inst|FWFT_FIFO:fifo_sup_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 15 (0) ; 9 (0) ; 6 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_r_if:fifo_rb_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_odk1:auto_generated| ; 15 (0) ; 9 (0) ; 6 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_r_if:fifo_rb_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_odk1:auto_generated ; scfifo_odk1 ; work ;
|
||||
; |a_dpfifo_u9b1:dpfifo| ; 15 (11) ; 9 (7) ; 6 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_r_if:fifo_rb_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_odk1:auto_generated|a_dpfifo_u9b1:dpfifo ; a_dpfifo_u9b1 ; work ;
|
||||
; |altsyncram_qqj1:FIFOram| ; 0 (0) ; 0 (0) ; 6 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_r_if:fifo_rb_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_odk1:auto_generated|a_dpfifo_u9b1:dpfifo|altsyncram_qqj1:FIFOram ; altsyncram_qqj1 ; work ;
|
||||
; |cntr_c2b:wr_ptr| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_r_if:fifo_rb_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_odk1:auto_generated|a_dpfifo_u9b1:dpfifo|cntr_c2b:wr_ptr ; cntr_c2b ; work ;
|
||||
; |cntr_o27:usedw_counter| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_r_if:fifo_rb_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_odk1:auto_generated|a_dpfifo_u9b1:dpfifo|cntr_o27:usedw_counter ; cntr_o27 ; work ;
|
||||
; |vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst| ; 37 (7) ; 18 (0) ; 78 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst ; vector_FIFO ; work ;
|
||||
; |FWFT_FIFO:fifo_main_inst| ; 15 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_main_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 15 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_bfk1:auto_generated| ; 15 (0) ; 9 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated ; scfifo_bfk1 ; work ;
|
||||
; |a_dpfifo_hbb1:dpfifo| ; 15 (11) ; 9 (7) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo ; a_dpfifo_hbb1 ; work ;
|
||||
; |altsyncram_0uj1:FIFOram| ; 0 (0) ; 0 (0) ; 66 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|altsyncram_0uj1:FIFOram ; altsyncram_0uj1 ; work ;
|
||||
; |cntr_c2b:wr_ptr| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_c2b:wr_ptr ; cntr_c2b ; work ;
|
||||
; |cntr_o27:usedw_counter| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_main_inst|scfifo:scfifo_component|scfifo_bfk1:auto_generated|a_dpfifo_hbb1:dpfifo|cntr_o27:usedw_counter ; cntr_o27 ; work ;
|
||||
; |FWFT_FIFO:fifo_sup_inst| ; 15 (0) ; 9 (0) ; 12 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_sup_inst ; FWFT_FIFO ; work ;
|
||||
; |scfifo:scfifo_component| ; 15 (0) ; 9 (0) ; 12 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component ; scfifo ; work ;
|
||||
; |scfifo_rdk1:auto_generated| ; 15 (0) ; 9 (0) ; 12 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_rdk1:auto_generated ; scfifo_rdk1 ; work ;
|
||||
; |a_dpfifo_1ab1:dpfifo| ; 15 (11) ; 9 (7) ; 12 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_rdk1:auto_generated|a_dpfifo_1ab1:dpfifo ; a_dpfifo_1ab1 ; work ;
|
||||
; |altsyncram_0rj1:FIFOram| ; 0 (0) ; 0 (0) ; 12 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_rdk1:auto_generated|a_dpfifo_1ab1:dpfifo|altsyncram_0rj1:FIFOram ; altsyncram_0rj1 ; work ;
|
||||
; |cntr_c2b:wr_ptr| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_rdk1:auto_generated|a_dpfifo_1ab1:dpfifo|cntr_c2b:wr_ptr ; cntr_c2b ; work ;
|
||||
; |cntr_o27:usedw_counter| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |test_top|L2_Testbench_ROS_Lib4:ros_action_inst|vector_FIFO:\fifo_rb_re_w_if:fifo_rb_re_inst|FWFT_FIFO:fifo_sup_inst|scfifo:scfifo_component|scfifo_rdk1:auto_generated|a_dpfifo_1ab1:dpfifo|cntr_o27:usedw_counter ; cntr_o27 ; work ;
|
||||
+------------------------------------------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+--------------+
|
||||
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
||||
|
||||
|
||||
+---------------------------------------------------------+
|
||||
; Analysis & Synthesis Resource Usage Summary ;
|
||||
+---------------------------------------------+-----------+
|
||||
; Resource ; Usage ;
|
||||
+---------------------------------------------+-----------+
|
||||
; Estimate of Logic utilization (ALMs needed) ; 27731 ;
|
||||
; ; ;
|
||||
; Combinational ALUT usage for logic ; 42256 ;
|
||||
; -- 7 input functions ; 700 ;
|
||||
; -- 6 input functions ; 8987 ;
|
||||
; -- 5 input functions ; 9513 ;
|
||||
; -- 4 input functions ; 9502 ;
|
||||
; -- <=3 input functions ; 13554 ;
|
||||
; ; ;
|
||||
; Dedicated logic registers ; 19765 ;
|
||||
; ; ;
|
||||
; I/O pins ; 71 ;
|
||||
; Total MLAB memory bits ; 0 ;
|
||||
; Total block memory bits ; 2408283 ;
|
||||
; ; ;
|
||||
; Total DSP Blocks ; 4 ;
|
||||
; ; ;
|
||||
; Maximum fan-out node ; clk~input ;
|
||||
; Maximum fan-out ; 22878 ;
|
||||
; Total fan-out ; 293222 ;
|
||||
; Average fan-out ; 4.49 ;
|
||||
+---------------------------------------------+-----------+
|
||||
154
sim/L0_dds_writer_test1.do
Normal file
154
sim/L0_dds_writer_test1.do
Normal file
@ -0,0 +1,154 @@
|
||||
onerror {resume}
|
||||
radix define DDS_RETCODE {
|
||||
"10#0#" "RETCODE_OK",
|
||||
"10#1#" "RETCODE_ERROR",
|
||||
"10#2#" "RETCODE_UNSUPPORTED",
|
||||
"10#3#" "RETCODE_BAD_PARAMETER",
|
||||
"10#4#" "RETCODE_PRECONDITION_NOT_MET",
|
||||
"10#5#" "RETCODE_OUT_OF_RESOURCES",
|
||||
"10#6#" "RETCODE_NOT_ENABLED",
|
||||
"10#7#" "RETCODE_IMMUTABLE_POLICY",
|
||||
"10#8#" "RETCODE_INCONSISTENT_POLICY",
|
||||
"10#9#" "RETCODE_ALREADY_DELETED",
|
||||
"10#10#" "RETCODE_TIMEOUT",
|
||||
"10#11#" "RETCODE_NO_DATA",
|
||||
"10#12#" "RETCODE_ILLEGAL_OPERATION",
|
||||
-default unsigned
|
||||
}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -divider SYSTEM
|
||||
add wave -noupdate /l0_dds_writer_test1/uut/clk
|
||||
add wave -noupdate /l0_dds_writer_test1/uut/reset
|
||||
add wave -noupdate -radix unsigned /l0_dds_writer_test1/uut/time
|
||||
add wave -noupdate -divider {RTPS IN}
|
||||
add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1/uut/start_rtps
|
||||
add wave -noupdate -group {RTPS IN} -radix unsigned /l0_dds_writer_test1/uut/seq_nr_rtps
|
||||
add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1/uut/opcode_rtps
|
||||
add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1/uut/ack_rtps
|
||||
add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1/uut/done_rtps
|
||||
add wave -noupdate -group {RTPS IN} /l0_dds_writer_test1/uut/ret_rtps
|
||||
add wave -noupdate -divider {RTPS OUT}
|
||||
add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test1/uut/cc_instance_handle
|
||||
add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1/uut/cc_kind
|
||||
add wave -noupdate -group {RTPS OUT} -radix unsigned /l0_dds_writer_test1/uut/cc_source_timestamp
|
||||
add wave -noupdate -group {RTPS OUT} -radix unsigned -childformat {{/l0_dds_writer_test1/uut/cc_seq_nr(0) -radix unsigned -childformat {{/l0_dds_writer_test1/uut/cc_seq_nr(0)(0) -radix unsigned} {/l0_dds_writer_test1/uut/cc_seq_nr(0)(1) -radix unsigned}}} {/l0_dds_writer_test1/uut/cc_seq_nr(1) -radix unsigned} {/l0_dds_writer_test1/uut/cc_seq_nr(2) -radix unsigned} {/l0_dds_writer_test1/uut/cc_seq_nr(3) -radix unsigned}} -subitemconfig {/l0_dds_writer_test1/uut/cc_seq_nr(0) {-height 15 -radix unsigned -childformat {{/l0_dds_writer_test1/uut/cc_seq_nr(0)(0) -radix unsigned} {/l0_dds_writer_test1/uut/cc_seq_nr(0)(1) -radix unsigned}}} /l0_dds_writer_test1/uut/cc_seq_nr(0)(0) {-height 15 -radix unsigned} /l0_dds_writer_test1/uut/cc_seq_nr(0)(1) {-height 15 -radix unsigned} /l0_dds_writer_test1/uut/cc_seq_nr(1) {-height 15 -radix unsigned} /l0_dds_writer_test1/uut/cc_seq_nr(2) {-height 15 -radix unsigned} /l0_dds_writer_test1/uut/cc_seq_nr(3) {-height 15 -radix unsigned}} /l0_dds_writer_test1/uut/cc_seq_nr
|
||||
add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1/uut/get_data_rtps
|
||||
add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1/uut/ready_out_rtps
|
||||
add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1/uut/valid_out_rtps
|
||||
add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test1/uut/data_out_rtps
|
||||
add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test1/uut/last_word_out_rtps
|
||||
add wave -noupdate -divider {DDS IN}
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test1/uut/start_dds
|
||||
add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_writer_test1/uut/source_ts_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test1/uut/opcode_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test1/uut/ack_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test1/uut/done_dds
|
||||
add wave -noupdate -expand -group DDS -radix unsigned -childformat {{/l0_dds_writer_test1/uut/return_code_dds(0) -radix DDS_RETCODE} {/l0_dds_writer_test1/uut/return_code_dds(1) -radix DDS_RETCODE} {/l0_dds_writer_test1/uut/return_code_dds(2) -radix DDS_RETCODE} {/l0_dds_writer_test1/uut/return_code_dds(3) -radix DDS_RETCODE}} -subitemconfig {/l0_dds_writer_test1/uut/return_code_dds(0) {-height 15 -radix DDS_RETCODE} /l0_dds_writer_test1/uut/return_code_dds(1) {-height 15 -radix DDS_RETCODE} /l0_dds_writer_test1/uut/return_code_dds(2) {-height 15 -radix DDS_RETCODE} /l0_dds_writer_test1/uut/return_code_dds(3) {-height 15 -radix DDS_RETCODE}} /l0_dds_writer_test1/uut/return_code_dds
|
||||
add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test1/uut/instance_handle_in_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test1/uut/ready_in_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test1/uut/valid_in_dds
|
||||
add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test1/uut/data_in_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test1/uut/last_word_in_dds
|
||||
add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test1/uut/instance_handle_out_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test1/uut/ready_out_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test1/uut/valid_out_dds
|
||||
add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test1/uut/data_out_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test1/uut/last_word_out_dds
|
||||
add wave -noupdate -divider {MAIN FSM}
|
||||
add wave -noupdate /l0_dds_writer_test1/uut/stage
|
||||
add wave -noupdate /l0_dds_writer_test1/uut/cnt
|
||||
add wave -noupdate /l0_dds_writer_test1/uut/ind
|
||||
add wave -noupdate -radix unsigned /l0_dds_writer_test1/uut/global_seq_nr
|
||||
add wave -noupdate -radix unsigned /l0_dds_writer_test1/uut/global_sample_cnt
|
||||
add wave -noupdate -radix unsigned /l0_dds_writer_test1/uut/global_ack_cnt
|
||||
add wave -noupdate -radix unsigned /l0_dds_writer_test1/uut/stale_inst_cnt
|
||||
add wave -noupdate /l0_dds_writer_test1/uut/remove_oldest_inst_sample
|
||||
add wave -noupdate /l0_dds_writer_test1/uut/remove_oldest_sample
|
||||
add wave -noupdate /l0_dds_writer_test1/uut/remove_ack_sample
|
||||
add wave -noupdate -divider MEMORY
|
||||
add wave -noupdate -group {SAMPLE MEM} -radix unsigned /l0_dds_writer_test1/uut/sample_addr
|
||||
add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1/uut/sample_read
|
||||
add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1/uut/sample_ready_in
|
||||
add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1/uut/sample_valid_in
|
||||
add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test1/uut/sample_write_data
|
||||
add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1/uut/sample_ready_out
|
||||
add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1/uut/sample_valid_out
|
||||
add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test1/uut/sample_read_data
|
||||
add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test1/uut/sample_abort_read
|
||||
add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_writer_test1/uut/payload_addr
|
||||
add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1/uut/payload_read
|
||||
add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1/uut/payload_ready_in
|
||||
add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1/uut/payload_valid_in
|
||||
add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test1/uut/payload_write_data
|
||||
add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1/uut/payload_ready_out
|
||||
add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1/uut/payload_valid_out
|
||||
add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test1/uut/payload_read_data
|
||||
add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test1/uut/payload_abort_read
|
||||
add wave -noupdate /l0_dds_writer_test1/uut/inst_op_start
|
||||
add wave -noupdate /l0_dds_writer_test1/uut/inst_opcode
|
||||
add wave -noupdate /l0_dds_writer_test1/uut/inst_op_done
|
||||
add wave -noupdate /l0_dds_writer_test1/uut/inst_stage
|
||||
add wave -noupdate /l0_dds_writer_test1/uut/inst_cnt
|
||||
add wave -noupdate -radix unsigned /l0_dds_writer_test1/uut/inst_addr_base
|
||||
add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_writer_test1/uut/inst_addr
|
||||
add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1/uut/inst_read
|
||||
add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1/uut/inst_ready_in
|
||||
add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1/uut/inst_valid_in
|
||||
add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test1/uut/inst_write_data
|
||||
add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1/uut/inst_ready_out
|
||||
add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1/uut/inst_valid_out
|
||||
add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test1/uut/inst_read_data
|
||||
add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test1/uut/inst_abort_read
|
||||
add wave -noupdate -radix hexadecimal -childformat {{/l0_dds_writer_test1/uut/inst_data.i -radix hexadecimal} {/l0_dds_writer_test1/uut/inst_data.addr -radix unsigned} {/l0_dds_writer_test1/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_writer_test1/uut/inst_data.status_info -radix binary} {/l0_dds_writer_test1/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_writer_test1/uut/inst_data.ack_cnt -radix unsigned}} -subitemconfig {/l0_dds_writer_test1/uut/inst_data.i {-height 15 -radix hexadecimal} /l0_dds_writer_test1/uut/inst_data.addr {-height 15 -radix unsigned} /l0_dds_writer_test1/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_writer_test1/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_writer_test1/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_writer_test1/uut/inst_data.ack_cnt {-height 15 -radix unsigned} /l0_dds_writer_test1/uut/inst_data.field_flags {-height 15}} /l0_dds_writer_test1/uut/inst_data
|
||||
add wave -noupdate -divider {KEY HOLDER}
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1/uut/start_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1/uut/opcode_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1/uut/ack_kh
|
||||
add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test1/uut/data_in_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1/uut/valid_in_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1/uut/ready_in_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1/uut/last_word_in_kh
|
||||
add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test1/uut/data_out_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1/uut/valid_out_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1/uut/ready_out_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1/uut/last_word_out_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test1/uut/abort_kh
|
||||
add wave -noupdate -divider POINTERS
|
||||
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1/uut/empty_sample_list_head
|
||||
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1/uut/empty_sample_list_tail
|
||||
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1/uut/empty_payload_list_head
|
||||
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1/uut/oldest_sample
|
||||
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1/uut/newest_sample
|
||||
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1/uut/inst_empty_head
|
||||
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test1/uut/inst_occupied_head
|
||||
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1/uut/cur_sample
|
||||
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1/uut/prev_sample
|
||||
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1/uut/next_sample
|
||||
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1/uut/cur_payload
|
||||
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1/uut/next_payload
|
||||
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1/uut/cur_inst
|
||||
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test1/uut/next_inst
|
||||
add wave -noupdate -divider TESTBENCH
|
||||
add wave -noupdate -divider MISC
|
||||
add wave -noupdate /l0_dds_writer_test1/uut/cnt2
|
||||
add wave -noupdate /l0_dds_writer_test1/uut/cnt3
|
||||
add wave -noupdate -radix unsigned /l0_dds_writer_test1/uut/long_latch
|
||||
add wave -noupdate /l0_dds_writer_test1/uut/sample_status_info
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {158543351 ps} 0}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 187
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {157882360 ps} {158883001 ps}
|
||||
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
154
sim/L0_dds_writer_test2.do
Normal file
154
sim/L0_dds_writer_test2.do
Normal file
@ -0,0 +1,154 @@
|
||||
onerror {resume}
|
||||
radix define DDS_RETCODE {
|
||||
"10#0#" "RETCODE_OK",
|
||||
"10#1#" "RETCODE_ERROR",
|
||||
"10#2#" "RETCODE_UNSUPPORTED",
|
||||
"10#3#" "RETCODE_BAD_PARAMETER",
|
||||
"10#4#" "RETCODE_PRECONDITION_NOT_MET",
|
||||
"10#5#" "RETCODE_OUT_OF_RESOURCES",
|
||||
"10#6#" "RETCODE_NOT_ENABLED",
|
||||
"10#7#" "RETCODE_IMMUTABLE_POLICY",
|
||||
"10#8#" "RETCODE_INCONSISTENT_POLICY",
|
||||
"10#9#" "RETCODE_ALREADY_DELETED",
|
||||
"10#10#" "RETCODE_TIMEOUT",
|
||||
"10#11#" "RETCODE_NO_DATA",
|
||||
"10#12#" "RETCODE_ILLEGAL_OPERATION",
|
||||
-default unsigned
|
||||
}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -divider SYSTEM
|
||||
add wave -noupdate /l0_dds_writer_test2/uut/clk
|
||||
add wave -noupdate /l0_dds_writer_test2/uut/reset
|
||||
add wave -noupdate -radix unsigned /l0_dds_writer_test2/uut/time
|
||||
add wave -noupdate -radix unsigned /l0_dds_writer_test2/uut/timeout_check_time
|
||||
add wave -noupdate -divider {RTPS IN}
|
||||
add wave -noupdate -group {RTPS IN} /l0_dds_writer_test2/uut/start_rtps
|
||||
add wave -noupdate -group {RTPS IN} -radix unsigned /l0_dds_writer_test2/uut/seq_nr_rtps
|
||||
add wave -noupdate -group {RTPS IN} /l0_dds_writer_test2/uut/opcode_rtps
|
||||
add wave -noupdate -group {RTPS IN} /l0_dds_writer_test2/uut/ack_rtps
|
||||
add wave -noupdate -group {RTPS IN} /l0_dds_writer_test2/uut/done_rtps
|
||||
add wave -noupdate -group {RTPS IN} /l0_dds_writer_test2/uut/ret_rtps
|
||||
add wave -noupdate -divider {RTPS OUT}
|
||||
add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test2/uut/cc_instance_handle
|
||||
add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test2/uut/cc_kind
|
||||
add wave -noupdate -group {RTPS OUT} -radix unsigned /l0_dds_writer_test2/uut/cc_source_timestamp
|
||||
add wave -noupdate -group {RTPS OUT} -radix unsigned -childformat {{/l0_dds_writer_test2/uut/cc_seq_nr(0) -radix unsigned -childformat {{/l0_dds_writer_test2/uut/cc_seq_nr(0)(0) -radix unsigned} {/l0_dds_writer_test2/uut/cc_seq_nr(0)(1) -radix unsigned}}} {/l0_dds_writer_test2/uut/cc_seq_nr(1) -radix unsigned}} -subitemconfig {/l0_dds_writer_test2/uut/cc_seq_nr(0) {-height 15 -radix unsigned -childformat {{/l0_dds_writer_test2/uut/cc_seq_nr(0)(0) -radix unsigned} {/l0_dds_writer_test2/uut/cc_seq_nr(0)(1) -radix unsigned}}} /l0_dds_writer_test2/uut/cc_seq_nr(0)(0) {-height 15 -radix unsigned} /l0_dds_writer_test2/uut/cc_seq_nr(0)(1) {-height 15 -radix unsigned} /l0_dds_writer_test2/uut/cc_seq_nr(1) {-height 15 -radix unsigned}} /l0_dds_writer_test2/uut/cc_seq_nr
|
||||
add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test2/uut/get_data_rtps
|
||||
add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test2/uut/ready_out_rtps
|
||||
add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test2/uut/valid_out_rtps
|
||||
add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test2/uut/data_out_rtps
|
||||
add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test2/uut/last_word_out_rtps
|
||||
add wave -noupdate -divider {DDS IN}
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test2/uut/start_dds
|
||||
add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_writer_test2/uut/source_ts_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test2/uut/opcode_dds
|
||||
add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_writer_test2/uut/max_wait_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test2/uut/ack_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test2/uut/done_dds
|
||||
add wave -noupdate -expand -group DDS -radix unsigned -childformat {{/l0_dds_writer_test2/uut/return_code_dds(0) -radix DDS_RETCODE} {/l0_dds_writer_test2/uut/return_code_dds(1) -radix DDS_RETCODE}} -subitemconfig {/l0_dds_writer_test2/uut/return_code_dds(0) {-height 15 -radix DDS_RETCODE} /l0_dds_writer_test2/uut/return_code_dds(1) {-height 15 -radix DDS_RETCODE}} /l0_dds_writer_test2/uut/return_code_dds
|
||||
add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test2/uut/instance_handle_in_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test2/uut/ready_in_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test2/uut/valid_in_dds
|
||||
add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test2/uut/data_in_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test2/uut/last_word_in_dds
|
||||
add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test2/uut/instance_handle_out_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test2/uut/ready_out_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test2/uut/valid_out_dds
|
||||
add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test2/uut/data_out_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test2/uut/last_word_out_dds
|
||||
add wave -noupdate -divider {MAIN FSM}
|
||||
add wave -noupdate /l0_dds_writer_test2/uut/stage
|
||||
add wave -noupdate /l0_dds_writer_test2/uut/cnt
|
||||
add wave -noupdate /l0_dds_writer_test2/uut/ind
|
||||
add wave -noupdate -radix unsigned /l0_dds_writer_test2/uut/global_seq_nr
|
||||
add wave -noupdate -radix unsigned /l0_dds_writer_test2/uut/global_sample_cnt
|
||||
add wave -noupdate -radix unsigned /l0_dds_writer_test2/uut/global_ack_cnt
|
||||
add wave -noupdate -radix unsigned /l0_dds_writer_test2/uut/stale_inst_cnt
|
||||
add wave -noupdate /l0_dds_writer_test2/uut/remove_oldest_inst_sample
|
||||
add wave -noupdate /l0_dds_writer_test2/uut/remove_oldest_sample
|
||||
add wave -noupdate /l0_dds_writer_test2/uut/remove_ack_sample
|
||||
add wave -noupdate -divider MEMORY
|
||||
add wave -noupdate -group {SAMPLE MEM} -radix unsigned /l0_dds_writer_test2/uut/sample_addr
|
||||
add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test2/uut/sample_read
|
||||
add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test2/uut/sample_ready_in
|
||||
add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test2/uut/sample_valid_in
|
||||
add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test2/uut/sample_write_data
|
||||
add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test2/uut/sample_ready_out
|
||||
add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test2/uut/sample_valid_out
|
||||
add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test2/uut/sample_read_data
|
||||
add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test2/uut/sample_abort_read
|
||||
add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_writer_test2/uut/payload_addr
|
||||
add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test2/uut/payload_read
|
||||
add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test2/uut/payload_ready_in
|
||||
add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test2/uut/payload_valid_in
|
||||
add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test2/uut/payload_write_data
|
||||
add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test2/uut/payload_ready_out
|
||||
add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test2/uut/payload_valid_out
|
||||
add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test2/uut/payload_read_data
|
||||
add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test2/uut/payload_abort_read
|
||||
add wave -noupdate /l0_dds_writer_test2/uut/inst_op_start
|
||||
add wave -noupdate /l0_dds_writer_test2/uut/inst_opcode
|
||||
add wave -noupdate /l0_dds_writer_test2/uut/inst_op_done
|
||||
add wave -noupdate /l0_dds_writer_test2/uut/inst_stage
|
||||
add wave -noupdate /l0_dds_writer_test2/uut/inst_cnt
|
||||
add wave -noupdate -radix unsigned /l0_dds_writer_test2/uut/inst_addr_base
|
||||
add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_writer_test2/uut/inst_addr
|
||||
add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test2/uut/inst_read
|
||||
add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test2/uut/inst_ready_in
|
||||
add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test2/uut/inst_valid_in
|
||||
add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test2/uut/inst_write_data
|
||||
add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test2/uut/inst_ready_out
|
||||
add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test2/uut/inst_valid_out
|
||||
add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test2/uut/inst_read_data
|
||||
add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test2/uut/inst_abort_read
|
||||
add wave -noupdate -radix hexadecimal -childformat {{/l0_dds_writer_test2/uut/inst_data.i -radix hexadecimal} {/l0_dds_writer_test2/uut/inst_data.addr -radix unsigned} {/l0_dds_writer_test2/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_writer_test2/uut/inst_data.status_info -radix binary} {/l0_dds_writer_test2/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_writer_test2/uut/inst_data.ack_cnt -radix unsigned}} -subitemconfig {/l0_dds_writer_test2/uut/inst_data.i {-height 15 -radix hexadecimal} /l0_dds_writer_test2/uut/inst_data.addr {-height 15 -radix unsigned} /l0_dds_writer_test2/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_writer_test2/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_writer_test2/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_writer_test2/uut/inst_data.ack_cnt {-height 15 -radix unsigned} /l0_dds_writer_test2/uut/inst_data.field_flags {-height 15}} /l0_dds_writer_test2/uut/inst_data
|
||||
add wave -noupdate -divider {KEY HOLDER}
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test2/uut/start_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test2/uut/opcode_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test2/uut/ack_kh
|
||||
add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test2/uut/data_in_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test2/uut/valid_in_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test2/uut/ready_in_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test2/uut/last_word_in_kh
|
||||
add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test2/uut/data_out_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test2/uut/valid_out_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test2/uut/ready_out_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test2/uut/last_word_out_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test2/uut/abort_kh
|
||||
add wave -noupdate -divider POINTERS
|
||||
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test2/uut/empty_sample_list_head
|
||||
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test2/uut/empty_sample_list_tail
|
||||
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test2/uut/empty_payload_list_head
|
||||
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test2/uut/oldest_sample
|
||||
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test2/uut/newest_sample
|
||||
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test2/uut/inst_empty_head
|
||||
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test2/uut/inst_occupied_head
|
||||
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test2/uut/cur_sample
|
||||
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test2/uut/prev_sample
|
||||
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test2/uut/next_sample
|
||||
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test2/uut/cur_payload
|
||||
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test2/uut/next_payload
|
||||
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test2/uut/cur_inst
|
||||
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test2/uut/next_inst
|
||||
add wave -noupdate -divider MISC
|
||||
add wave -noupdate /l0_dds_writer_test2/uut/ack_wait
|
||||
add wave -noupdate /l0_dds_writer_test2/uut/ack_wait_check
|
||||
add wave -noupdate -radix unsigned /l0_dds_writer_test2/uut/timeout_time
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {158543351 ps} 0}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 187
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {157882360 ps} {158883001 ps}
|
||||
File diff suppressed because one or more lines are too long
154
sim/L0_dds_writer_test3.do
Normal file
154
sim/L0_dds_writer_test3.do
Normal file
@ -0,0 +1,154 @@
|
||||
onerror {resume}
|
||||
radix define DDS_RETCODE {
|
||||
"10#0#" "RETCODE_OK",
|
||||
"10#1#" "RETCODE_ERROR",
|
||||
"10#2#" "RETCODE_UNSUPPORTED",
|
||||
"10#3#" "RETCODE_BAD_PARAMETER",
|
||||
"10#4#" "RETCODE_PRECONDITION_NOT_MET",
|
||||
"10#5#" "RETCODE_OUT_OF_RESOURCES",
|
||||
"10#6#" "RETCODE_NOT_ENABLED",
|
||||
"10#7#" "RETCODE_IMMUTABLE_POLICY",
|
||||
"10#8#" "RETCODE_INCONSISTENT_POLICY",
|
||||
"10#9#" "RETCODE_ALREADY_DELETED",
|
||||
"10#10#" "RETCODE_TIMEOUT",
|
||||
"10#11#" "RETCODE_NO_DATA",
|
||||
"10#12#" "RETCODE_ILLEGAL_OPERATION",
|
||||
-default unsigned
|
||||
}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -divider SYSTEM
|
||||
add wave -noupdate /l0_dds_writer_test3/uut/clk
|
||||
add wave -noupdate /l0_dds_writer_test3/uut/reset
|
||||
add wave -noupdate -radix unsigned /l0_dds_writer_test3/uut/time
|
||||
add wave -noupdate -divider {RTPS IN}
|
||||
add wave -noupdate -group {RTPS IN} /l0_dds_writer_test3/uut/start_rtps
|
||||
add wave -noupdate -group {RTPS IN} -radix unsigned /l0_dds_writer_test3/uut/seq_nr_rtps
|
||||
add wave -noupdate -group {RTPS IN} /l0_dds_writer_test3/uut/opcode_rtps
|
||||
add wave -noupdate -group {RTPS IN} /l0_dds_writer_test3/uut/ack_rtps
|
||||
add wave -noupdate -group {RTPS IN} /l0_dds_writer_test3/uut/done_rtps
|
||||
add wave -noupdate -group {RTPS IN} /l0_dds_writer_test3/uut/ret_rtps
|
||||
add wave -noupdate -divider {RTPS OUT}
|
||||
add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test3/uut/cc_instance_handle
|
||||
add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test3/uut/cc_kind
|
||||
add wave -noupdate -group {RTPS OUT} -radix unsigned /l0_dds_writer_test3/uut/cc_source_timestamp
|
||||
add wave -noupdate -group {RTPS OUT} -radix unsigned -childformat {{/l0_dds_writer_test3/uut/cc_seq_nr(0) -radix unsigned -childformat {{/l0_dds_writer_test3/uut/cc_seq_nr(0)(0) -radix unsigned} {/l0_dds_writer_test3/uut/cc_seq_nr(0)(1) -radix unsigned}}} {/l0_dds_writer_test3/uut/cc_seq_nr(1) -radix unsigned} {/l0_dds_writer_test3/uut/cc_seq_nr(2) -radix unsigned} {/l0_dds_writer_test3/uut/cc_seq_nr(3) -radix unsigned}} -subitemconfig {/l0_dds_writer_test3/uut/cc_seq_nr(0) {-height 15 -radix unsigned -childformat {{/l0_dds_writer_test3/uut/cc_seq_nr(0)(0) -radix unsigned} {/l0_dds_writer_test3/uut/cc_seq_nr(0)(1) -radix unsigned}}} /l0_dds_writer_test3/uut/cc_seq_nr(0)(0) {-height 15 -radix unsigned} /l0_dds_writer_test3/uut/cc_seq_nr(0)(1) {-height 15 -radix unsigned} /l0_dds_writer_test3/uut/cc_seq_nr(1) {-height 15 -radix unsigned} /l0_dds_writer_test3/uut/cc_seq_nr(2) {-height 15 -radix unsigned} /l0_dds_writer_test3/uut/cc_seq_nr(3) {-height 15 -radix unsigned}} /l0_dds_writer_test3/uut/cc_seq_nr
|
||||
add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test3/uut/get_data_rtps
|
||||
add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test3/uut/ready_out_rtps
|
||||
add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test3/uut/valid_out_rtps
|
||||
add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test3/uut/data_out_rtps
|
||||
add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test3/uut/last_word_out_rtps
|
||||
add wave -noupdate -divider {DDS IN}
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test3/uut/start_dds
|
||||
add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_writer_test3/uut/source_ts_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test3/uut/opcode_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test3/uut/ack_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test3/uut/done_dds
|
||||
add wave -noupdate -expand -group DDS -radix unsigned -childformat {{/l0_dds_writer_test3/uut/return_code_dds(0) -radix DDS_RETCODE} {/l0_dds_writer_test3/uut/return_code_dds(1) -radix DDS_RETCODE} {/l0_dds_writer_test3/uut/return_code_dds(2) -radix DDS_RETCODE} {/l0_dds_writer_test3/uut/return_code_dds(3) -radix DDS_RETCODE}} -subitemconfig {/l0_dds_writer_test3/uut/return_code_dds(0) {-height 15 -radix DDS_RETCODE} /l0_dds_writer_test3/uut/return_code_dds(1) {-height 15 -radix DDS_RETCODE} /l0_dds_writer_test3/uut/return_code_dds(2) {-height 15 -radix DDS_RETCODE} /l0_dds_writer_test3/uut/return_code_dds(3) {-height 15 -radix DDS_RETCODE}} /l0_dds_writer_test3/uut/return_code_dds
|
||||
add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test3/uut/instance_handle_in_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test3/uut/ready_in_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test3/uut/valid_in_dds
|
||||
add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test3/uut/data_in_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test3/uut/last_word_in_dds
|
||||
add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test3/uut/instance_handle_out_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test3/uut/ready_out_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test3/uut/valid_out_dds
|
||||
add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test3/uut/data_out_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test3/uut/last_word_out_dds
|
||||
add wave -noupdate -divider {MAIN FSM}
|
||||
add wave -noupdate /l0_dds_writer_test3/uut/stage
|
||||
add wave -noupdate /l0_dds_writer_test3/uut/cnt
|
||||
add wave -noupdate /l0_dds_writer_test3/uut/ind
|
||||
add wave -noupdate -radix unsigned /l0_dds_writer_test3/uut/global_seq_nr
|
||||
add wave -noupdate -radix unsigned /l0_dds_writer_test3/uut/global_sample_cnt
|
||||
add wave -noupdate -radix unsigned /l0_dds_writer_test3/uut/global_ack_cnt
|
||||
add wave -noupdate -radix unsigned /l0_dds_writer_test3/uut/stale_inst_cnt
|
||||
add wave -noupdate /l0_dds_writer_test3/uut/remove_oldest_inst_sample
|
||||
add wave -noupdate /l0_dds_writer_test3/uut/remove_oldest_sample
|
||||
add wave -noupdate /l0_dds_writer_test3/uut/remove_ack_sample
|
||||
add wave -noupdate -divider MEMORY
|
||||
add wave -noupdate -group {SAMPLE MEM} -radix unsigned /l0_dds_writer_test3/uut/sample_addr
|
||||
add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test3/uut/sample_read
|
||||
add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test3/uut/sample_ready_in
|
||||
add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test3/uut/sample_valid_in
|
||||
add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test3/uut/sample_write_data
|
||||
add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test3/uut/sample_ready_out
|
||||
add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test3/uut/sample_valid_out
|
||||
add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test3/uut/sample_read_data
|
||||
add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test3/uut/sample_abort_read
|
||||
add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_writer_test3/uut/payload_addr
|
||||
add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test3/uut/payload_read
|
||||
add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test3/uut/payload_ready_in
|
||||
add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test3/uut/payload_valid_in
|
||||
add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test3/uut/payload_write_data
|
||||
add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test3/uut/payload_ready_out
|
||||
add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test3/uut/payload_valid_out
|
||||
add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test3/uut/payload_read_data
|
||||
add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test3/uut/payload_abort_read
|
||||
add wave -noupdate /l0_dds_writer_test3/uut/inst_op_start
|
||||
add wave -noupdate /l0_dds_writer_test3/uut/inst_opcode
|
||||
add wave -noupdate /l0_dds_writer_test3/uut/inst_op_done
|
||||
add wave -noupdate /l0_dds_writer_test3/uut/inst_stage
|
||||
add wave -noupdate /l0_dds_writer_test3/uut/inst_cnt
|
||||
add wave -noupdate -radix unsigned /l0_dds_writer_test3/uut/inst_addr_base
|
||||
add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_writer_test3/uut/inst_addr
|
||||
add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test3/uut/inst_read
|
||||
add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test3/uut/inst_ready_in
|
||||
add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test3/uut/inst_valid_in
|
||||
add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test3/uut/inst_write_data
|
||||
add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test3/uut/inst_ready_out
|
||||
add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test3/uut/inst_valid_out
|
||||
add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test3/uut/inst_read_data
|
||||
add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test3/uut/inst_abort_read
|
||||
add wave -noupdate -radix hexadecimal -childformat {{/l0_dds_writer_test3/uut/inst_data.i -radix hexadecimal} {/l0_dds_writer_test3/uut/inst_data.addr -radix unsigned} {/l0_dds_writer_test3/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_writer_test3/uut/inst_data.status_info -radix binary} {/l0_dds_writer_test3/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_writer_test3/uut/inst_data.ack_cnt -radix unsigned}} -subitemconfig {/l0_dds_writer_test3/uut/inst_data.i {-height 15 -radix hexadecimal} /l0_dds_writer_test3/uut/inst_data.addr {-height 15 -radix unsigned} /l0_dds_writer_test3/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_writer_test3/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_writer_test3/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_writer_test3/uut/inst_data.ack_cnt {-height 15 -radix unsigned} /l0_dds_writer_test3/uut/inst_data.field_flags {-height 15}} /l0_dds_writer_test3/uut/inst_data
|
||||
add wave -noupdate -divider {KEY HOLDER}
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3/uut/start_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3/uut/opcode_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3/uut/ack_kh
|
||||
add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test3/uut/data_in_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3/uut/valid_in_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3/uut/ready_in_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3/uut/last_word_in_kh
|
||||
add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test3/uut/data_out_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3/uut/valid_out_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3/uut/ready_out_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3/uut/last_word_out_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test3/uut/abort_kh
|
||||
add wave -noupdate -divider POINTERS
|
||||
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test3/uut/empty_sample_list_head
|
||||
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test3/uut/empty_sample_list_tail
|
||||
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test3/uut/empty_payload_list_head
|
||||
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test3/uut/oldest_sample
|
||||
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test3/uut/newest_sample
|
||||
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test3/uut/inst_empty_head
|
||||
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test3/uut/inst_occupied_head
|
||||
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test3/uut/cur_sample
|
||||
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test3/uut/prev_sample
|
||||
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test3/uut/next_sample
|
||||
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test3/uut/cur_payload
|
||||
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test3/uut/next_payload
|
||||
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test3/uut/cur_inst
|
||||
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test3/uut/next_inst
|
||||
add wave -noupdate -divider TESTBENCH
|
||||
add wave -noupdate -divider MISC
|
||||
add wave -noupdate /l0_dds_writer_test3/uut/cnt2
|
||||
add wave -noupdate /l0_dds_writer_test3/uut/cnt3
|
||||
add wave -noupdate -radix unsigned /l0_dds_writer_test3/uut/long_latch
|
||||
add wave -noupdate /l0_dds_writer_test3/uut/sample_status_info
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {158543351 ps} 0}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 187
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {157882360 ps} {158883001 ps}
|
||||
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
154
sim/L0_dds_writer_test4.do
Normal file
154
sim/L0_dds_writer_test4.do
Normal file
@ -0,0 +1,154 @@
|
||||
onerror {resume}
|
||||
radix define DDS_RETCODE {
|
||||
"10#0#" "RETCODE_OK",
|
||||
"10#1#" "RETCODE_ERROR",
|
||||
"10#2#" "RETCODE_UNSUPPORTED",
|
||||
"10#3#" "RETCODE_BAD_PARAMETER",
|
||||
"10#4#" "RETCODE_PRECONDITION_NOT_MET",
|
||||
"10#5#" "RETCODE_OUT_OF_RESOURCES",
|
||||
"10#6#" "RETCODE_NOT_ENABLED",
|
||||
"10#7#" "RETCODE_IMMUTABLE_POLICY",
|
||||
"10#8#" "RETCODE_INCONSISTENT_POLICY",
|
||||
"10#9#" "RETCODE_ALREADY_DELETED",
|
||||
"10#10#" "RETCODE_TIMEOUT",
|
||||
"10#11#" "RETCODE_NO_DATA",
|
||||
"10#12#" "RETCODE_ILLEGAL_OPERATION",
|
||||
-default unsigned
|
||||
}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -divider SYSTEM
|
||||
add wave -noupdate /l0_dds_writer_test4/uut/clk
|
||||
add wave -noupdate /l0_dds_writer_test4/uut/reset
|
||||
add wave -noupdate -radix unsigned /l0_dds_writer_test4/uut/time
|
||||
add wave -noupdate -divider {RTPS IN}
|
||||
add wave -noupdate -group {RTPS IN} /l0_dds_writer_test4/uut/start_rtps
|
||||
add wave -noupdate -group {RTPS IN} -radix unsigned /l0_dds_writer_test4/uut/seq_nr_rtps
|
||||
add wave -noupdate -group {RTPS IN} /l0_dds_writer_test4/uut/opcode_rtps
|
||||
add wave -noupdate -group {RTPS IN} /l0_dds_writer_test4/uut/ack_rtps
|
||||
add wave -noupdate -group {RTPS IN} /l0_dds_writer_test4/uut/done_rtps
|
||||
add wave -noupdate -group {RTPS IN} /l0_dds_writer_test4/uut/ret_rtps
|
||||
add wave -noupdate -divider {RTPS OUT}
|
||||
add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test4/uut/cc_instance_handle
|
||||
add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test4/uut/cc_kind
|
||||
add wave -noupdate -group {RTPS OUT} -radix unsigned /l0_dds_writer_test4/uut/cc_source_timestamp
|
||||
add wave -noupdate -group {RTPS OUT} -radix unsigned -childformat {{/l0_dds_writer_test4/uut/cc_seq_nr(0) -radix unsigned -childformat {{/l0_dds_writer_test4/uut/cc_seq_nr(0)(0) -radix unsigned} {/l0_dds_writer_test4/uut/cc_seq_nr(0)(1) -radix unsigned}}} {/l0_dds_writer_test4/uut/cc_seq_nr(1) -radix unsigned} {/l0_dds_writer_test4/uut/cc_seq_nr(2) -radix unsigned} {/l0_dds_writer_test4/uut/cc_seq_nr(3) -radix unsigned}} -subitemconfig {/l0_dds_writer_test4/uut/cc_seq_nr(0) {-height 15 -radix unsigned -childformat {{/l0_dds_writer_test4/uut/cc_seq_nr(0)(0) -radix unsigned} {/l0_dds_writer_test4/uut/cc_seq_nr(0)(1) -radix unsigned}}} /l0_dds_writer_test4/uut/cc_seq_nr(0)(0) {-height 15 -radix unsigned} /l0_dds_writer_test4/uut/cc_seq_nr(0)(1) {-height 15 -radix unsigned} /l0_dds_writer_test4/uut/cc_seq_nr(1) {-height 15 -radix unsigned} /l0_dds_writer_test4/uut/cc_seq_nr(2) {-height 15 -radix unsigned} /l0_dds_writer_test4/uut/cc_seq_nr(3) {-height 15 -radix unsigned}} /l0_dds_writer_test4/uut/cc_seq_nr
|
||||
add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test4/uut/get_data_rtps
|
||||
add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test4/uut/ready_out_rtps
|
||||
add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test4/uut/valid_out_rtps
|
||||
add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test4/uut/data_out_rtps
|
||||
add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test4/uut/last_word_out_rtps
|
||||
add wave -noupdate -divider {DDS IN}
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test4/uut/start_dds
|
||||
add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_writer_test4/uut/source_ts_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test4/uut/opcode_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test4/uut/ack_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test4/uut/done_dds
|
||||
add wave -noupdate -expand -group DDS -radix unsigned -childformat {{/l0_dds_writer_test4/uut/return_code_dds(0) -radix DDS_RETCODE} {/l0_dds_writer_test4/uut/return_code_dds(1) -radix DDS_RETCODE} {/l0_dds_writer_test4/uut/return_code_dds(2) -radix DDS_RETCODE} {/l0_dds_writer_test4/uut/return_code_dds(3) -radix DDS_RETCODE}} -subitemconfig {/l0_dds_writer_test4/uut/return_code_dds(0) {-height 15 -radix DDS_RETCODE} /l0_dds_writer_test4/uut/return_code_dds(1) {-height 15 -radix DDS_RETCODE} /l0_dds_writer_test4/uut/return_code_dds(2) {-height 15 -radix DDS_RETCODE} /l0_dds_writer_test4/uut/return_code_dds(3) {-height 15 -radix DDS_RETCODE}} /l0_dds_writer_test4/uut/return_code_dds
|
||||
add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test4/uut/instance_handle_in_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test4/uut/ready_in_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test4/uut/valid_in_dds
|
||||
add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test4/uut/data_in_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test4/uut/last_word_in_dds
|
||||
add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test4/uut/instance_handle_out_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test4/uut/ready_out_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test4/uut/valid_out_dds
|
||||
add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test4/uut/data_out_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test4/uut/last_word_out_dds
|
||||
add wave -noupdate -divider {MAIN FSM}
|
||||
add wave -noupdate /l0_dds_writer_test4/uut/stage
|
||||
add wave -noupdate /l0_dds_writer_test4/uut/cnt
|
||||
add wave -noupdate /l0_dds_writer_test4/uut/ind
|
||||
add wave -noupdate -radix unsigned /l0_dds_writer_test4/uut/global_seq_nr
|
||||
add wave -noupdate -radix unsigned /l0_dds_writer_test4/uut/global_sample_cnt
|
||||
add wave -noupdate -radix unsigned /l0_dds_writer_test4/uut/global_ack_cnt
|
||||
add wave -noupdate -radix unsigned /l0_dds_writer_test4/uut/stale_inst_cnt
|
||||
add wave -noupdate /l0_dds_writer_test4/uut/remove_oldest_inst_sample
|
||||
add wave -noupdate /l0_dds_writer_test4/uut/remove_oldest_sample
|
||||
add wave -noupdate /l0_dds_writer_test4/uut/remove_ack_sample
|
||||
add wave -noupdate -divider MEMORY
|
||||
add wave -noupdate -group {SAMPLE MEM} -radix unsigned /l0_dds_writer_test4/uut/sample_addr
|
||||
add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test4/uut/sample_read
|
||||
add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test4/uut/sample_ready_in
|
||||
add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test4/uut/sample_valid_in
|
||||
add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test4/uut/sample_write_data
|
||||
add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test4/uut/sample_ready_out
|
||||
add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test4/uut/sample_valid_out
|
||||
add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test4/uut/sample_read_data
|
||||
add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test4/uut/sample_abort_read
|
||||
add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_writer_test4/uut/payload_addr
|
||||
add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test4/uut/payload_read
|
||||
add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test4/uut/payload_ready_in
|
||||
add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test4/uut/payload_valid_in
|
||||
add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test4/uut/payload_write_data
|
||||
add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test4/uut/payload_ready_out
|
||||
add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test4/uut/payload_valid_out
|
||||
add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test4/uut/payload_read_data
|
||||
add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test4/uut/payload_abort_read
|
||||
add wave -noupdate /l0_dds_writer_test4/uut/inst_op_start
|
||||
add wave -noupdate /l0_dds_writer_test4/uut/inst_opcode
|
||||
add wave -noupdate /l0_dds_writer_test4/uut/inst_op_done
|
||||
add wave -noupdate /l0_dds_writer_test4/uut/inst_stage
|
||||
add wave -noupdate /l0_dds_writer_test4/uut/inst_cnt
|
||||
add wave -noupdate -radix unsigned /l0_dds_writer_test4/uut/inst_addr_base
|
||||
add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_writer_test4/uut/inst_addr
|
||||
add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test4/uut/inst_read
|
||||
add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test4/uut/inst_ready_in
|
||||
add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test4/uut/inst_valid_in
|
||||
add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test4/uut/inst_write_data
|
||||
add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test4/uut/inst_ready_out
|
||||
add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test4/uut/inst_valid_out
|
||||
add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test4/uut/inst_read_data
|
||||
add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test4/uut/inst_abort_read
|
||||
add wave -noupdate -radix hexadecimal -childformat {{/l0_dds_writer_test4/uut/inst_data.i -radix hexadecimal} {/l0_dds_writer_test4/uut/inst_data.addr -radix unsigned} {/l0_dds_writer_test4/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_writer_test4/uut/inst_data.status_info -radix binary} {/l0_dds_writer_test4/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_writer_test4/uut/inst_data.ack_cnt -radix unsigned}} -subitemconfig {/l0_dds_writer_test4/uut/inst_data.i {-height 15 -radix hexadecimal} /l0_dds_writer_test4/uut/inst_data.addr {-height 15 -radix unsigned} /l0_dds_writer_test4/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_writer_test4/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_writer_test4/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_writer_test4/uut/inst_data.ack_cnt {-height 15 -radix unsigned} /l0_dds_writer_test4/uut/inst_data.field_flags {-height 15}} /l0_dds_writer_test4/uut/inst_data
|
||||
add wave -noupdate -divider {KEY HOLDER}
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test4/uut/start_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test4/uut/opcode_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test4/uut/ack_kh
|
||||
add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test4/uut/data_in_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test4/uut/valid_in_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test4/uut/ready_in_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test4/uut/last_word_in_kh
|
||||
add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test4/uut/data_out_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test4/uut/valid_out_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test4/uut/ready_out_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test4/uut/last_word_out_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test4/uut/abort_kh
|
||||
add wave -noupdate -divider POINTERS
|
||||
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test4/uut/empty_sample_list_head
|
||||
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test4/uut/empty_sample_list_tail
|
||||
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test4/uut/empty_payload_list_head
|
||||
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test4/uut/oldest_sample
|
||||
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test4/uut/newest_sample
|
||||
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test4/uut/inst_empty_head
|
||||
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test4/uut/inst_occupied_head
|
||||
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test4/uut/cur_sample
|
||||
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test4/uut/prev_sample
|
||||
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test4/uut/next_sample
|
||||
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test4/uut/cur_payload
|
||||
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test4/uut/next_payload
|
||||
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test4/uut/cur_inst
|
||||
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test4/uut/next_inst
|
||||
add wave -noupdate -divider TESTBENCH
|
||||
add wave -noupdate -divider MISC
|
||||
add wave -noupdate /l0_dds_writer_test4/uut/cnt2
|
||||
add wave -noupdate /l0_dds_writer_test4/uut/cnt3
|
||||
add wave -noupdate -radix unsigned /l0_dds_writer_test4/uut/long_latch
|
||||
add wave -noupdate /l0_dds_writer_test4/uut/sample_status_info
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {158543351 ps} 0}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 187
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {157882360 ps} {158883001 ps}
|
||||
File diff suppressed because one or more lines are too long
155
sim/L0_dds_writer_test5.do
Normal file
155
sim/L0_dds_writer_test5.do
Normal file
@ -0,0 +1,155 @@
|
||||
onerror {resume}
|
||||
radix define DDS_RETCODE {
|
||||
"10#0#" "RETCODE_OK",
|
||||
"10#1#" "RETCODE_ERROR",
|
||||
"10#2#" "RETCODE_UNSUPPORTED",
|
||||
"10#3#" "RETCODE_BAD_PARAMETER",
|
||||
"10#4#" "RETCODE_PRECONDITION_NOT_MET",
|
||||
"10#5#" "RETCODE_OUT_OF_RESOURCES",
|
||||
"10#6#" "RETCODE_NOT_ENABLED",
|
||||
"10#7#" "RETCODE_IMMUTABLE_POLICY",
|
||||
"10#8#" "RETCODE_INCONSISTENT_POLICY",
|
||||
"10#9#" "RETCODE_ALREADY_DELETED",
|
||||
"10#10#" "RETCODE_TIMEOUT",
|
||||
"10#11#" "RETCODE_NO_DATA",
|
||||
"10#12#" "RETCODE_ILLEGAL_OPERATION",
|
||||
-default unsigned
|
||||
}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -divider SYSTEM
|
||||
add wave -noupdate /l0_dds_writer_test5/uut/clk
|
||||
add wave -noupdate /l0_dds_writer_test5/uut/reset
|
||||
add wave -noupdate -radix unsigned /l0_dds_writer_test5/uut/time
|
||||
add wave -noupdate -radix unsigned /l0_dds_writer_test5/uut/lifespan_time
|
||||
add wave -noupdate -divider {RTPS IN}
|
||||
add wave -noupdate -group {RTPS IN} /l0_dds_writer_test5/uut/start_rtps
|
||||
add wave -noupdate -group {RTPS IN} -radix unsigned /l0_dds_writer_test5/uut/seq_nr_rtps
|
||||
add wave -noupdate -group {RTPS IN} /l0_dds_writer_test5/uut/opcode_rtps
|
||||
add wave -noupdate -group {RTPS IN} /l0_dds_writer_test5/uut/ack_rtps
|
||||
add wave -noupdate -group {RTPS IN} /l0_dds_writer_test5/uut/done_rtps
|
||||
add wave -noupdate -group {RTPS IN} /l0_dds_writer_test5/uut/ret_rtps
|
||||
add wave -noupdate -divider {RTPS OUT}
|
||||
add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test5/uut/cc_instance_handle
|
||||
add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test5/uut/cc_kind
|
||||
add wave -noupdate -group {RTPS OUT} -radix unsigned /l0_dds_writer_test5/uut/cc_source_timestamp
|
||||
add wave -noupdate -group {RTPS OUT} -radix unsigned -childformat {{/l0_dds_writer_test5/uut/cc_seq_nr(0) -radix unsigned -childformat {{/l0_dds_writer_test5/uut/cc_seq_nr(0)(0) -radix unsigned} {/l0_dds_writer_test5/uut/cc_seq_nr(0)(1) -radix unsigned}}} {/l0_dds_writer_test5/uut/cc_seq_nr(1) -radix unsigned}} -subitemconfig {/l0_dds_writer_test5/uut/cc_seq_nr(0) {-height 15 -radix unsigned -childformat {{/l0_dds_writer_test5/uut/cc_seq_nr(0)(0) -radix unsigned} {/l0_dds_writer_test5/uut/cc_seq_nr(0)(1) -radix unsigned}}} /l0_dds_writer_test5/uut/cc_seq_nr(0)(0) {-height 15 -radix unsigned} /l0_dds_writer_test5/uut/cc_seq_nr(0)(1) {-height 15 -radix unsigned} /l0_dds_writer_test5/uut/cc_seq_nr(1) {-height 15 -radix unsigned}} /l0_dds_writer_test5/uut/cc_seq_nr
|
||||
add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test5/uut/get_data_rtps
|
||||
add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test5/uut/ready_out_rtps
|
||||
add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test5/uut/valid_out_rtps
|
||||
add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l0_dds_writer_test5/uut/data_out_rtps
|
||||
add wave -noupdate -group {RTPS OUT} /l0_dds_writer_test5/uut/last_word_out_rtps
|
||||
add wave -noupdate -divider {DDS IN}
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test5/uut/start_dds
|
||||
add wave -noupdate -expand -group DDS -radix unsigned /l0_dds_writer_test5/uut/source_ts_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test5/uut/opcode_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test5/uut/ack_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test5/uut/done_dds
|
||||
add wave -noupdate -expand -group DDS -radix unsigned -childformat {{/l0_dds_writer_test5/uut/return_code_dds(0) -radix DDS_RETCODE} {/l0_dds_writer_test5/uut/return_code_dds(1) -radix DDS_RETCODE}} -subitemconfig {/l0_dds_writer_test5/uut/return_code_dds(0) {-height 15 -radix DDS_RETCODE} /l0_dds_writer_test5/uut/return_code_dds(1) {-height 15 -radix DDS_RETCODE}} /l0_dds_writer_test5/uut/return_code_dds
|
||||
add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test5/uut/instance_handle_in_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test5/uut/ready_in_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test5/uut/valid_in_dds
|
||||
add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test5/uut/data_in_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test5/uut/last_word_in_dds
|
||||
add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test5/uut/instance_handle_out_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test5/uut/ready_out_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test5/uut/valid_out_dds
|
||||
add wave -noupdate -expand -group DDS -radix hexadecimal /l0_dds_writer_test5/uut/data_out_dds
|
||||
add wave -noupdate -expand -group DDS /l0_dds_writer_test5/uut/last_word_out_dds
|
||||
add wave -noupdate -divider {MAIN FSM}
|
||||
add wave -noupdate /l0_dds_writer_test5/uut/stage
|
||||
add wave -noupdate /l0_dds_writer_test5/uut/cnt
|
||||
add wave -noupdate /l0_dds_writer_test5/uut/ind
|
||||
add wave -noupdate -radix unsigned /l0_dds_writer_test5/uut/global_seq_nr
|
||||
add wave -noupdate -radix unsigned /l0_dds_writer_test5/uut/global_sample_cnt
|
||||
add wave -noupdate -radix unsigned /l0_dds_writer_test5/uut/global_ack_cnt
|
||||
add wave -noupdate -radix unsigned /l0_dds_writer_test5/uut/stale_inst_cnt
|
||||
add wave -noupdate /l0_dds_writer_test5/uut/remove_oldest_inst_sample
|
||||
add wave -noupdate /l0_dds_writer_test5/uut/remove_oldest_sample
|
||||
add wave -noupdate /l0_dds_writer_test5/uut/remove_ack_sample
|
||||
add wave -noupdate -divider MEMORY
|
||||
add wave -noupdate -group {SAMPLE MEM} -radix unsigned /l0_dds_writer_test5/uut/sample_addr
|
||||
add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test5/uut/sample_read
|
||||
add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test5/uut/sample_ready_in
|
||||
add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test5/uut/sample_valid_in
|
||||
add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test5/uut/sample_write_data
|
||||
add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test5/uut/sample_ready_out
|
||||
add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test5/uut/sample_valid_out
|
||||
add wave -noupdate -group {SAMPLE MEM} -radix hexadecimal /l0_dds_writer_test5/uut/sample_read_data
|
||||
add wave -noupdate -group {SAMPLE MEM} /l0_dds_writer_test5/uut/sample_abort_read
|
||||
add wave -noupdate -group {PAYLOAD MEM} -radix unsigned /l0_dds_writer_test5/uut/payload_addr
|
||||
add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test5/uut/payload_read
|
||||
add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test5/uut/payload_ready_in
|
||||
add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test5/uut/payload_valid_in
|
||||
add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test5/uut/payload_write_data
|
||||
add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test5/uut/payload_ready_out
|
||||
add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test5/uut/payload_valid_out
|
||||
add wave -noupdate -group {PAYLOAD MEM} -radix hexadecimal /l0_dds_writer_test5/uut/payload_read_data
|
||||
add wave -noupdate -group {PAYLOAD MEM} /l0_dds_writer_test5/uut/payload_abort_read
|
||||
add wave -noupdate /l0_dds_writer_test5/uut/inst_op_start
|
||||
add wave -noupdate /l0_dds_writer_test5/uut/inst_opcode
|
||||
add wave -noupdate /l0_dds_writer_test5/uut/inst_op_done
|
||||
add wave -noupdate /l0_dds_writer_test5/uut/inst_stage
|
||||
add wave -noupdate /l0_dds_writer_test5/uut/inst_cnt
|
||||
add wave -noupdate -radix unsigned /l0_dds_writer_test5/uut/inst_addr_base
|
||||
add wave -noupdate -group {INSTANCE MEM} -radix unsigned /l0_dds_writer_test5/uut/inst_addr
|
||||
add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test5/uut/inst_read
|
||||
add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test5/uut/inst_ready_in
|
||||
add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test5/uut/inst_valid_in
|
||||
add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test5/uut/inst_write_data
|
||||
add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test5/uut/inst_ready_out
|
||||
add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test5/uut/inst_valid_out
|
||||
add wave -noupdate -group {INSTANCE MEM} -radix hexadecimal /l0_dds_writer_test5/uut/inst_read_data
|
||||
add wave -noupdate -group {INSTANCE MEM} /l0_dds_writer_test5/uut/inst_abort_read
|
||||
add wave -noupdate -radix hexadecimal -childformat {{/l0_dds_writer_test5/uut/inst_data.i -radix hexadecimal} {/l0_dds_writer_test5/uut/inst_data.addr -radix unsigned} {/l0_dds_writer_test5/uut/inst_data.key_hash -radix hexadecimal} {/l0_dds_writer_test5/uut/inst_data.status_info -radix binary} {/l0_dds_writer_test5/uut/inst_data.sample_cnt -radix unsigned} {/l0_dds_writer_test5/uut/inst_data.ack_cnt -radix unsigned}} -subitemconfig {/l0_dds_writer_test5/uut/inst_data.i {-height 15 -radix hexadecimal} /l0_dds_writer_test5/uut/inst_data.addr {-height 15 -radix unsigned} /l0_dds_writer_test5/uut/inst_data.key_hash {-height 15 -radix hexadecimal} /l0_dds_writer_test5/uut/inst_data.status_info {-height 15 -radix binary} /l0_dds_writer_test5/uut/inst_data.sample_cnt {-height 15 -radix unsigned} /l0_dds_writer_test5/uut/inst_data.ack_cnt {-height 15 -radix unsigned} /l0_dds_writer_test5/uut/inst_data.field_flags {-height 15}} /l0_dds_writer_test5/uut/inst_data
|
||||
add wave -noupdate -divider {KEY HOLDER}
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test5/uut/start_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test5/uut/opcode_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test5/uut/ack_kh
|
||||
add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test5/uut/data_in_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test5/uut/valid_in_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test5/uut/ready_in_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test5/uut/last_word_in_kh
|
||||
add wave -noupdate -group {KEY HOLDER} -radix hexadecimal /l0_dds_writer_test5/uut/data_out_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test5/uut/valid_out_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test5/uut/ready_out_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test5/uut/last_word_out_kh
|
||||
add wave -noupdate -group {KEY HOLDER} /l0_dds_writer_test5/uut/abort_kh
|
||||
add wave -noupdate -divider POINTERS
|
||||
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test5/uut/empty_sample_list_head
|
||||
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test5/uut/empty_sample_list_tail
|
||||
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test5/uut/empty_payload_list_head
|
||||
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test5/uut/oldest_sample
|
||||
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test5/uut/newest_sample
|
||||
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test5/uut/inst_empty_head
|
||||
add wave -noupdate -group {LIST POINTERS} -radix unsigned /l0_dds_writer_test5/uut/inst_occupied_head
|
||||
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test5/uut/cur_sample
|
||||
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test5/uut/prev_sample
|
||||
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test5/uut/next_sample
|
||||
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test5/uut/cur_payload
|
||||
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test5/uut/next_payload
|
||||
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test5/uut/cur_inst
|
||||
add wave -noupdate -group {GENERAL POINTERS} -radix unsigned /l0_dds_writer_test5/uut/next_inst
|
||||
add wave -noupdate -divider TESTBENCH
|
||||
add wave -noupdate -divider MISC
|
||||
add wave -noupdate /l0_dds_writer_test5/uut/cnt2
|
||||
add wave -noupdate /l0_dds_writer_test5/uut/cnt3
|
||||
add wave -noupdate -radix unsigned /l0_dds_writer_test5/uut/long_latch
|
||||
add wave -noupdate /l0_dds_writer_test5/uut/sample_status_info
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {27047657 ps} 0}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 187
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {26890438 ps} {27891079 ps}
|
||||
File diff suppressed because one or more lines are too long
6528
src/Tests/Level_0/L0_dds_writer_test1.vhd
Normal file
6528
src/Tests/Level_0/L0_dds_writer_test1.vhd
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,270 +0,0 @@
|
||||
SAMPLE MEMORY: -/0,9,18,27,36
|
||||
PAYLOAD MEMORY: -/0,11,22,33,44
|
||||
INSTANCE MEMORY: -/0,8,16
|
||||
RTPS Operation GET_MIN_SN (Expected SEQUENCENUMBER_UNKNOWN)
|
||||
RTPS Operation GET_MAX_SN (Expected SEQUENCENUMBER_UNKNOWN)
|
||||
DDS Operation WRITE [TS 1s, Instance 1] (REJECTED: Instance not Registered)
|
||||
DDS Operation WRITE [TS 1s, Instance 1, HANDLE_NIL] (ACCEPTED)
|
||||
SAMPLE MEMORY: 0(I1S1)/9,18,27,36
|
||||
PAYLOAD MEMORY: 0(I1S1)/11,22,33,44
|
||||
INSTANCE MEMORY: 0(I1)/8,16
|
||||
RTPS Operation GET_MIN_SN (Expected SN 1)
|
||||
RTPS Operation GET_MAX_SN (Expected SN 1)
|
||||
DDS Operation WRITE [TS 2s, Instance 2, Unaligned Payload (2 Slots)] (REJECTED: Instance not Registered)
|
||||
DDS Operation REGISTER_INSTANCE 2 (ACCEPTED)
|
||||
SAMPLE MEMORY: 0(I1S1)/9,18,27,36
|
||||
PAYLOAD MEMORY: 0(I1S1)/11,22,33,44
|
||||
INSTANCE MEMORY: 8(I2),0(I1)/16
|
||||
DDS Operation WRITE [TS 2s, Instance 2, Unaligned Payload (2 Slots)] (ACCEPTED)
|
||||
SAMPLE MEMORY: 0(I1S1),9(I2S2)/18,27,36
|
||||
PAYLOAD MEMORY: 0(I1S1),11(I2S2),22(I2S2)/33,44
|
||||
INSTANCE MEMORY: 8(I2),0(I1)/16
|
||||
DDS Operation WRITE [TS 3s, Instance 1, Unaligned Payload (2 Slots)] (ACCEPTED)
|
||||
SAMPLE MEMORY: 0(I1S1),9(I2S2),18(I1S3)/27,36
|
||||
PAYLOAD MEMORY: 0(I1S1),11(I2S2),22(I2S2),33(I1S3),44(I1S3)/-
|
||||
INSTANCE MEMORY: 8(I2),0(I1)/16
|
||||
RTPS Operation GET_CACHE_CHANGE SN 4 (Invalid)
|
||||
RTPS Operation GET_CACHE_CHANGE SN 1
|
||||
RTPS Operation GET_CACHE_CHANGE SN 2
|
||||
RTPS Operation GET_CACHE_CHANGE SN 3
|
||||
DDS Operation WRITE [TS 4s, Instance 3, HANDLE_NIL, Unaligned Payload (1 Slot)] (REJECTED: Payload Memory Full)
|
||||
RTPS Operation REMOVE_CACHE_CHANGE SN 5 (Invalid)
|
||||
RTPS Operation REMOVE_CACHE_CHANGE SN 2
|
||||
SAMPLE MEMORY: 0(I1S1),18(I1S3)/27,36,9
|
||||
PAYLOAD MEMORY: 0(I1S1),33(I1S3),44(I1S3)/11,22
|
||||
INSTANCE MEMORY: 8(I2),0(I1)/16
|
||||
DDS Operation WRITE [TS 4s, Instance 3, HANDLE_NIL, Unaligned Payload (1 Slot)] (ACCEPTED)
|
||||
SAMPLE MEMORY: 0(I1S1),18(I1S3),27(I3S4)/36,9
|
||||
PAYLOAD MEMORY: 0(I1S1),33(I1S3),44(I1S3),11(I3S4)/22
|
||||
INSTANCE MEMORY: 16(I3),8(I2),0(I1)/-
|
||||
RTPS Operation GET_CACHE_CHANGE SN 4
|
||||
DDS Operation REGISTER_INSTANCE 3 (No Change)
|
||||
DDS Operation DISPOSE [TS 5s, Instance 1] (REJECTED: MAX_SAMPLES_PER_INSTANCE Exceeded)
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 4
|
||||
DDS Operation DISPOSE [TS 5s, Instance 1] (REJECTED: MAX_SAMPLES_PER_INSTANCE Exceeded)
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 1
|
||||
DDS Operation DISPOSE [TS 5s, Instance 1] (ACCEPTED)
|
||||
SAMPLE MEMORY: 18(I1S3),27(I3S4),36(I1S5)/9,0
|
||||
PAYLOAD MEMORY: 33(I1S3),44(I1S3),11(I3S4),22(I1S5)/0
|
||||
INSTANCE MEMORY: 16(I3),8(I2),0(I1)/-
|
||||
RTPS Operation GET_MIN_SN (Expected SN 3)
|
||||
RTPS Operation GET_MAX_SN (Expected SN 5)
|
||||
RTPS Operation GET_CACHE_CHANGE SN 5
|
||||
DDS Operation WRITE [TS 6s, Instance 4, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 3
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 4
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 5
|
||||
DDS Operation WRITE [TS 6s, Instance 4, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)
|
||||
DDS Operation UNREGISTER_INSTANCE [TS 6s, Instance 1] (ACCEPTED)
|
||||
SAMPLE MEMORY: 27(I3S4),36(I1S5),9(I1S6)/0,18
|
||||
PAYLOAD MEMORY: 11(I3S4),22(I1S5),0(I1S6)/33,44
|
||||
INSTANCE MEMORY: 16(I3),8(I2),0(I1)/-
|
||||
RTPS Operation GET_MIN_SN (Expected SN 4)
|
||||
RTPS Operation GET_MAX_SN (Expected SN 6)
|
||||
RTPS Operation GET_CACHE_CHANGE SN 6
|
||||
DDS Operation WRITE [TS 7s, Instance 4, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 6
|
||||
DDS Operation WRITE [TS 7s, Instance 4, HANDLE_NIL, Aligned Payload] (ACCEPTED)
|
||||
SAMPLE MEMORY: 27(I3S4),0(I4S7)/18,36,9
|
||||
PAYLOAD MEMORY: 11(I3S4),33(I4S7)/0,22,44
|
||||
INSTANCE MEMORY: 0(I4),16(I3),8(I2)/-
|
||||
RTPS Operation GET_CACHE_CHANGE SN 5 (Invalid)
|
||||
RTPS Operation GET_CACHE_CHANGE SN 6 (Invalid)
|
||||
RTPS Operation GET_CACHE_CHANGE SN 7
|
||||
DDS Operation WRITE [TS 8s, Instance 2, Unaligned Payload (2 Slots)] (ACCEPTED)
|
||||
SAMPLE MEMORY: 27(I3S4),0(I4S7),18(I2S8)/36,9
|
||||
PAYLOAD MEMORY: 11(I3S4),33(I4S7),0(I2S8),22(I2S8)/44
|
||||
INSTANCE MEMORY: 0(I4),16(I3),8(I2)/-
|
||||
DDS Operation WRITE [TS 9s, Instance 1, Aligned Payload] (REJECTED: Instance not Registered)
|
||||
DDS Operation REGISTER_INSTANCE 1 (REJECTED: MAX_INSTANCES exceeded)
|
||||
DDS Operation UNREGISTER_INSTANCE [TS 9s, Instance 3] (ACCEPTED)
|
||||
SAMPLE MEMORY: 27(I3S4),0(I4S7),18(I2S8),36(I3S9)/9
|
||||
PAYLOAD MEMORY: 11(I3S4),33(I4S7),0(I2S8),22(I2S8),44(I3S9)/-
|
||||
INSTANCE MEMORY: 0(I4),16(I3),8(I2)/-
|
||||
RTPS Operation GET_MIN_SN (Expected SN 4)
|
||||
RTPS Operation GET_MAX_SN (Expected SN 9)
|
||||
RTPS Operation GET_CACHE_CHANGE SN 8
|
||||
RTPS Operation GET_CACHE_CHANGE SN 9
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 9
|
||||
DDS Operation REGISTER_INSTANCE 1 (ACCPETED)
|
||||
SAMPLE MEMORY: 0(I4S7),18(I2S8)/9,27,36
|
||||
PAYLOAD MEMORY: 33(I4S7),0(I2S8),22(I2S8)/44,11
|
||||
INSTANCE MEMORY: 16(I1),0(I4),8(I2)/-
|
||||
DDS Operation WRITE [TS 10s, Instance 1, Aligned Payload] (ACCEPTED)
|
||||
SAMPLE MEMORY: 0(I4S7),18(I2S8),9(I1S10)/27,36
|
||||
PAYLOAD MEMORY: 33(I4S7),0(I2S8),22(I2S8),44(I1S10)/11
|
||||
INSTANCE MEMORY: 16(I1),0(I4),8(I2)/-
|
||||
DDS Operation WRITE [TS 11s, Instance 1, Aligned Payload] (ACCEPTED)
|
||||
SAMPLE MEMORY: 0(I4S7),18(I2S8),9(I1S10),27(I4S11)/36
|
||||
PAYLOAD MEMORY: 33(I4S7),0(I2S8),22(I2S8),44(I1S10),11(I4S11)/-
|
||||
INSTANCE MEMORY: 16(I1),0(I4),8(I2)/-
|
||||
DDS Operation WRITE [TS 12s, Instance 2, Aligned Payload] (REJECTED: Payload Memory Full)
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 8
|
||||
DDS Operation WRITE [TS 12s, Instance 2, Aligned Payload] (ACCEPTED)
|
||||
SAMPLE MEMORY: 0(I4S7),9(I1S10),27(I4S11),36(I2S12)/18
|
||||
PAYLOAD MEMORY: 33(I4S7),44(I1S10),11(I4S11),0(I2S12)/22
|
||||
INSTANCE MEMORY: 16(I1),0(I4),8(I2)/-
|
||||
DDS Operation WRITE [TS 13s, Instance 4, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded)
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 7
|
||||
DDS Operation WRITE [TS 13s, Instance 4, Aligned Payload] (ACCEPTED)
|
||||
SAMPLE MEMORY: 9(I1S10),27(I4S11),36(I2S12),18(I4S13)/0
|
||||
PAYLOAD MEMORY: 44(I1S10),11(I4S11),0(I2S12),22(I4S13)/33
|
||||
INSTANCE MEMORY: 16(I1),0(I4),8(I2)/-
|
||||
RTPS Operation GET_MIN_SN (Expected SN 4)
|
||||
RTPS Operation GET_MAX_SN (Expected SN 9)
|
||||
RTPS Operation GET_CACHE_CHANGE SN 10
|
||||
RTPS Operation GET_CACHE_CHANGE SN 11
|
||||
RTPS Operation GET_CACHE_CHANGE SN 12
|
||||
RTPS Operation GET_CACHE_CHANGE SN 13
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 12
|
||||
DDS Operation UNREGISTER_INSTANCE [TS 14s, Instance 2] (ACCEPTED)
|
||||
SAMPLE MEMORY: 9(I1S10),27(I4S11),18(I4S13),0(I2S14)/36
|
||||
PAYLOAD MEMORY: 44(I1S10),11(I4S11),22(I4S13),33(I2S14)/0
|
||||
INSTANCE MEMORY: 16(I1),0(I4),8(I2)/-
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 11
|
||||
DDS Operation WRITE [TS 15s, Instance 4, Aligned Payload (2 Slots)] (REJECTED: Payload Memory Full)
|
||||
RTPS Operation REMOVE_CACHE_CHANGE SN 11
|
||||
SAMPLE MEMORY: 9(I1S10),18(I4S13),0(I2S14)/36,27
|
||||
PAYLOAD MEMORY: 44(I1S10),22(I4S13),33(I2S14)/11,0
|
||||
INSTANCE MEMORY: 16(I1),0(I4),8(I2)/-
|
||||
DDS Operation WRITE [TS 15s, Instance 4, Aligned Payload (2 Slots)] (ACCEPTED)
|
||||
SAMPLE MEMORY: 9(I1S10),18(I4S13),0(I2S14),36(I4S15)/27
|
||||
PAYLOAD MEMORY: 44(I1S10),22(I4S13),33(I2S14),11(I4S15),0(I4S15)/-
|
||||
INSTANCE MEMORY: 16(I1),0(I4),8(I2)/-
|
||||
DDS Operation UNREGISTER_INSTANCE [TS 16s, Instance 1] (REJECTED: Payload memory Full, MAX_SAMPLES exceeded)
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 10
|
||||
DDS Operation UNREGISTER_INSTANCE [TS 16s, Instance 1] (ACCEPTED)
|
||||
SAMPLE MEMORY: 18(I4S13),0(I2S14),36(I4S15),27(I1S16)/9
|
||||
PAYLOAD MEMORY: 22(I4S13),33(I2S14),11(I4S15),0(I4S15),44(I1S16)/-
|
||||
INSTANCE MEMORY: 16(I1),0(I4),8(I2)/-
|
||||
DDS Operation DISPOSE [TS 17s, Instance 3] (REJECTED: Payload memory Full, MAX_SAMPLES exceeded)
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 13
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 14
|
||||
DDS Operation DISPOSE [TS 17s, Instance 3] (ACCEPTED)
|
||||
SAMPLE MEMORY: 36(I4S15),27(I1S16),9(I3S17)/18,0
|
||||
PAYLOAD MEMORY: 11(I4S15),0(I4S15),44(I1S16),22(I3S17)/33
|
||||
INSTANCE MEMORY: 8(I3),16(I1),0(I4)/-
|
||||
RTPS Operation GET_MIN_SN (Expected SN 15)
|
||||
RTPS Operation GET_MAX_SN (Expected SN 17)
|
||||
RTPS Operation GET_CACHE_CHANGE SN 15
|
||||
RTPS Operation GET_CACHE_CHANGE SN 16
|
||||
RTPS Operation GET_CACHE_CHANGE SN 17
|
||||
RTPS Operation REMOVE_CACHE_CHANGE SN 15
|
||||
SAMPLE MEMORY: 27(I1S16),9(I3S17)/18,0,36
|
||||
PAYLOAD MEMORY: 44(I1S16),22(I3S17)/11,0,33
|
||||
INSTANCE MEMORY: 8(I3),16(I1),0(I4)/-
|
||||
DDS Operation WRITE [TS 18s, Instance 3, Aligned Payload] (ACCEPTED)
|
||||
SAMPLE MEMORY: 27(I1S16),9(I3S17),18(I3S18)/0,36
|
||||
PAYLOAD MEMORY: 44(I1S16),22(I3S17),11(I3S18)/0,33
|
||||
INSTANCE MEMORY: 8(I3),16(I1),0(I4)/-
|
||||
DDS Operation WRITE [TS 19s, Instance 4, Aligned Payload] (ACCEPTED)
|
||||
SAMPLE MEMORY: 27(I1S16),9(I3S17),18(I3S18),0(I4S19)/36
|
||||
PAYLOAD MEMORY: 44(I1S16),22(I3S17),11(I3S18),0(I4S19)/33
|
||||
INSTANCE MEMORY: 8(I3),16(I1),0(I4)/-
|
||||
DDS Operation WRITE [TS 20s, Instance 2, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded, MAX_INSTANCES exceeded)
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 16
|
||||
DDS Operation WRITE [TS 20s, Instance 2, Aligned Payload] (ACCEPTED)
|
||||
SAMPLE MEMORY: 9(I3S17),18(I3S18),0(I4S19),36(I2S20)/27
|
||||
PAYLOAD MEMORY: 22(I3S17),11(I3S18),0(I4S19),33(I2S20)/44
|
||||
INSTANCE MEMORY: 16(I2),8(I3),0(I4)/-
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 17
|
||||
DDS Operation UNREGISTER_INSTANCE [TS 21s, Instance 4] (ACCEPTED)
|
||||
SAMPLE MEMORY: 18(I3S18),0(I4S19),36(I2S20),27(I4S21)/9
|
||||
PAYLOAD MEMORY: 11(I3S18),0(I4S19),33(I2S20),44(I4S21)/22
|
||||
INSTANCE MEMORY: 16(I2),8(I3),0(I4)/-
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 19
|
||||
DDS Operation WRITE [TS 22s, Instance 1, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded, MAX_INSTANCES exceeded)
|
||||
RTPS Operation REMOVE_CACHE_CHANGE SN 19
|
||||
SAMPLE MEMORY: 18(I3S18),36(I2S20),27(I4S21)/9,0
|
||||
PAYLOAD MEMORY: 11(I3S18),33(I2S20),44(I4S21)/0,22
|
||||
INSTANCE MEMORY: 16(I2),8(I3),0(I4)/-
|
||||
RTPS Operation REMOVE_CACHE_CHANGE SN 21
|
||||
SAMPLE MEMORY: 18(I3S18),36(I2S20)/9,0,27
|
||||
PAYLOAD MEMORY: 11(I3S18),33(I2S20)/44,0,22
|
||||
INSTANCE MEMORY: 16(I2),8(I3),0(I4)/-
|
||||
DDS Operation UNREGISTER_INSTANCE [TS 22s, Instance 2] (ACCEPTED)
|
||||
SAMPLE MEMORY: 18(I3S18),36(I2S20),9(I2S22)/0,27
|
||||
PAYLOAD MEMORY: 11(I3S18),33(I2S20),44(I2S22)/0,22
|
||||
INSTANCE MEMORY: 16(I2),8(I3),0(I4)/-
|
||||
DDS Operation UNREGISTER_INSTANCE [TS 23s, Instance 3] (ACCEPTED)
|
||||
SAMPLE MEMORY: 18(I3S18),36(I2S20),9(I2S22),0(I3S23)/27
|
||||
PAYLOAD MEMORY: 11(I3S18),33(I2S20),44(I2S22),0(I3S23)/22
|
||||
INSTANCE MEMORY: 16(I2),8(I3),0(I4)/-
|
||||
DDS Operation WRITE [TS 24s, Instance 1, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded, MAX_INSTANCES exceeded)
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 20
|
||||
DDS Operation WRITE [TS 24s, Instance 1, Aligned Payload] (ACCEPTED)
|
||||
SAMPLE MEMORY: 18(I3S18),9(I2S22),0(I3S23),27(I1S24)/36
|
||||
PAYLOAD MEMORY: 11(I3S18),44(I2S22),0(I3S23),22(I1S24)/33
|
||||
INSTANCE MEMORY: 0(I1),16(I2),8(I3)/-
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 22
|
||||
RTPS Operation NACK_CACHE_CHANGE SN 22
|
||||
DDS Operation REGISTER_INSTANCE 4 (REJECTED: MAX_INSTANCES exceeded)
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 22
|
||||
DDS Operation REGISTER_INSTANCE 2 (ACCEPTED)
|
||||
DDS Operation REGISTER_INSTANCE 4 (REJECTED: MAX_INSTANCES exceeded)
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 18
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 23
|
||||
DDS Operation WRITE [TS 25s, Instance 3, Aligned Payload] (ACCEPTED)
|
||||
SAMPLE MEMORY: 9(I2S22),0(I3S23),27(I1S24),36(I3S25)/18
|
||||
PAYLOAD MEMORY: 44(I2S22),0(I3S23),22(I1S24),33(I3S25)/11
|
||||
INSTANCE MEMORY: 0(I1),16(I2),8(I3)/-
|
||||
DDS Operation REGISTER_INSTANCE 4 (REJECTED: MAX_INSTANCES exceeded)
|
||||
DDS Operation UNREGISTER_INSTANCE [TS 26s, Instance 4] (REJECTED: Instance not Registered)
|
||||
RTPS Operation NACK_CACHE_CHANGE SN 22
|
||||
RTPS Operation NACK_CACHE_CHANGE SN 23
|
||||
DDS Operation UNREGISTER_INSTANCE [TS 26s, Instance 3] (REJECTED: MAX_SAMPLES_PER_INSTANCE exceeded, MAX_SAMPLES exceeded)
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 22
|
||||
DDS Operation UNREGISTER_INSTANCE [TS 26s, Instance 3] (REJECTED: MAX_SAMPLES_PER_INSTANCE exceeded, MAX_SAMPLES exceeded)
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 23
|
||||
DDS Operation UNREGISTER_INSTANCE [TS 26s, Instance 3] (ACCEPTED)
|
||||
SAMPLE MEMORY: 9(I2S22),27(I1S24),36(I3S25),18(I3S26)/0
|
||||
PAYLOAD MEMORY: 44(I2S22),22(I1S24),33(I3S25),11(I3S26)/0
|
||||
INSTANCE MEMORY: 0(I1),16(I2),8(I3)/-
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 25
|
||||
DDS Operation DISPOSE [TS 27s, Instance 3] (ACCEPTED)
|
||||
SAMPLE MEMORY: 9(I2S22),27(I1S24),18(I3S26),0(I3S27)/36
|
||||
PAYLOAD MEMORY: 44(I2S22),22(I1S24),11(I3S26),0(I3S27)/33
|
||||
INSTANCE MEMORY: 0(I1),16(I2),8(I3)/-
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 26
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 27
|
||||
DDS Operation REGISTER_INSTANCE 4 (ACCEPTED)
|
||||
SAMPLE MEMORY: 9(I2S22),27(I1S24)/36,18,0
|
||||
PAYLOAD MEMORY: 44(I2S22),22(I1S24)/0,11,33
|
||||
INSTANCE MEMORY: 8(I4),0(I1),16(I2)/-
|
||||
RTPS Operation GET_MIN_SN (Expected SN 22)
|
||||
RTPS Operation GET_MAX_SN (Expected SN 24)
|
||||
RTPS Operation GET_CACHE_CHANGE SN 22
|
||||
RTPS Operation GET_CACHE_CHANGE SN 24
|
||||
RTPS Operation NACK_CACHE_CHANGE SN 22
|
||||
RTPS Operation NACK_CACHE_CHANGE SN 24
|
||||
DDS Operation WRITE [TS 28s, Instance 4, Aligned Payload] (ACCEPTED)
|
||||
SAMPLE MEMORY: 9(I2S22),27(I1S24),36(I4S28)/18,0
|
||||
PAYLOAD MEMORY: 44(I2S22),22(I1S24),0(I4S28)/11,33
|
||||
INSTANCE MEMORY: 8(I4),0(I1),16(I2)/-
|
||||
DDS Operation WRITE [TS 29s, Instance 2, Aligned Payload] (ACCEPTED)
|
||||
SAMPLE MEMORY: 9(I2S22),27(I1S24),36(I4S28),18(I2S29)/0
|
||||
PAYLOAD MEMORY: 44(I2S22),22(I1S24),0(I4S28),11(I2S29)/33
|
||||
INSTANCE MEMORY: 8(I4),0(I1),16(I2)/-
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 24
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 28
|
||||
DDS Operation WRITE [TS 30s, Instance 1, Aligned Payload] (ACCEPTED)
|
||||
SAMPLE MEMORY: 9(I2S22),36(I4S28),18(I2S29),0(I1S30)/27
|
||||
PAYLOAD MEMORY: 44(I2S22),0(I4S28),11(I2S29),33(I1S30)/22
|
||||
INSTANCE MEMORY: 8(I4),0(I1),16(I2)/-
|
||||
RTPS Operation REMOVE_CACHE_CHANGE SN 28
|
||||
SAMPLE MEMORY: 9(I2S22),18(I2S29),0(I1S30)/27,36
|
||||
PAYLOAD MEMORY: 44(I2S22),11(I2S29),33(I1S30)/0,22
|
||||
INSTANCE MEMORY: 8(I4),0(I1),16(I2)/-
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 22
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 29
|
||||
DDS Operation WRITE [TS 31s, Instance 2, Aligned Payload] (ACCEPTED)
|
||||
SAMPLE MEMORY: 18(I2S29),0(I1S30),27(I2S31)/36,9
|
||||
PAYLOAD MEMORY: 11(I2S29),33(I1S30),0(I2S31)/44,22
|
||||
INSTANCE MEMORY: 8(I4),0(I1),16(I2)/-
|
||||
RTPS Operation GET_MIN_SN (Expected SN 29)
|
||||
RTPS Operation GET_MAX_SN (Expected SN 31)
|
||||
RTPS Operation GET_CACHE_CHANGE SN 29
|
||||
RTPS Operation GET_CACHE_CHANGE SN 30
|
||||
RTPS Operation GET_CACHE_CHANGE SN 31
|
||||
DDS Operation LOOKUP_INSTANCE [Instance 1]
|
||||
DDS Operation LOOKUP_INSTANCE [Unknown Instance]
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,69 +0,0 @@
|
||||
SAMPLE MEMORY: -/0,8,16,24,32
|
||||
PAYLOAD MEMORY: -/0,11,22,33,44
|
||||
RTPS Operation GET_MIN_SN (Expected SEQUENCENUMBER_UNKNOWN)
|
||||
RTPS Operation GET_MAX_SN (Expected SEQUENCENUMBER_UNKNOWN)
|
||||
DDS Operation WRITE [TS 1s, Aligned Payload] (ACCEPTED)
|
||||
SAMPLE MEMORY: 0(S1)/8,16,24,32
|
||||
PAYLOAD MEMORY: 0(S1)/11,22,33,44
|
||||
DDS Operation WRITE [TS 2s, Unaligned Payload (2 Slots)] (ACCEPTED)
|
||||
SAMPLE MEMORY: 0(S1),8(S2)/16,24,32
|
||||
PAYLOAD MEMORY: 0(S1),11(S2),22(S2)/33,44
|
||||
DDS Operation REGISTER_INSTANCE 2 (Illegal Operation)
|
||||
DDS Operation DISPOSE [TS 3s] (ACCEPTED)
|
||||
SAMPLE MEMORY: 0(S1),8(S2),16(S3)/24,32
|
||||
PAYLOAD MEMORY: 0(S1),11(S2),22(S2),33(S3)/44
|
||||
RTPS Operation GET_MIN_SN (Expected SN 1)
|
||||
RTPS Operation GET_MAX_SN (Expected SN 3)
|
||||
RTPS Operation GET_CACHE_CHANGE SN 4 (Invalid)
|
||||
RTPS Operation GET_CACHE_CHANGE SN 1
|
||||
RTPS Operation GET_CACHE_CHANGE SN 2
|
||||
RTPS Operation GET_CACHE_CHANGE SN 3
|
||||
DDS Operation WRITE [TS 2s, Aligned Payload] (ACCEPTED)
|
||||
SAMPLE MEMORY: 0(S1),8(S2),16(S3),24(S4)/32
|
||||
PAYLOAD MEMORY: 0(S1),11(S2),22(S2),33(S3),44(S4)/-
|
||||
DDS Operation UNREGISTER_INSTANCE [TS 5s] (REJECTED: Payload Memory Full)
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 1
|
||||
DDS Operation UNREGISTER_INSTANCE [TS 5s] (ACCEPTED)
|
||||
SAMPLE MEMORY: 8(S2),16(S3),24(S4),32(S5)/0
|
||||
PAYLOAD MEMORY: 11(S2),22(S2),33(S3),44(S4),0(S5)/-
|
||||
DDS Operation WRITE [TS 6s, Aligned Payload] (REJECTED: Payload Memory Full)
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 2
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 3
|
||||
RTPS Operation NACK_CACHE_CHANGE SN 2
|
||||
DDS Operation WRITE [TS 6s, Aligned Payload] (ACCEPTED)
|
||||
SAMPLE MEMORY: 8(S2),24(S4),32(S5),0(S6)/16
|
||||
PAYLOAD MEMORY: 11(S2),22(S2),44(S4),0(S5),33(S6)/-
|
||||
DDS Operation DISPOSE [TS 7s] (REJECTED: Payload Memory Full)
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 2
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 2
|
||||
DDS Operation DISPOSE [TS 7s] (ACCEPTED)
|
||||
SAMPLE MEMORY: 24(S4),32(S5),0(S6),16(S7)/8
|
||||
PAYLOAD MEMORY: 44(S4),0(S5),33(S6),11(S7)/22
|
||||
DDS Operation UNREGISTER_INSTANCE [TS 8s] (REJECTED: MAX_SAMPLES exceeded)
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 5
|
||||
DDS Operation UNREGISTER_INSTANCE [TS 8s] (ACCEPTED)
|
||||
SAMPLE MEMORY: 24(S4),0(S6),16(S7),8(S8)/32
|
||||
PAYLOAD MEMORY: 44(S4),33(S6),11(S7),22(S8)/0
|
||||
RTPS Operation GET_MIN_SN (Expected SN 4)
|
||||
RTPS Operation GET_MAX_SN (Expected SN 8)
|
||||
RTPS Operation GET_CACHE_CHANGE SN 4
|
||||
RTPS Operation GET_CACHE_CHANGE SN 6
|
||||
RTPS Operation GET_CACHE_CHANGE SN 7
|
||||
RTPS Operation GET_CACHE_CHANGE SN 8
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 6
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 8
|
||||
DDS Operation DISPOSE [TS 9s] (ACCEPTED)
|
||||
SAMPLE MEMORY: 24(S4),16(S7),8(S8),32(S9)/0
|
||||
PAYLOAD MEMORY: 44(S4),11(S7),22(S8),0(S9)/33
|
||||
DDS Operation UNREGISTER_INSTANCE [TS 10s] (ACCEPTED)
|
||||
SAMPLE MEMORY: 24(S4),16(S7),32(S9),0(S10)/8
|
||||
PAYLOAD MEMORY: 44(S4),11(S7),0(S9),33(S10)/22
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 7
|
||||
DDS Operation WRITE [TS 11s, Aligned Payload (2 Slots)] (REJECTED: Payload Memory Full)
|
||||
RTPS Operation REMOVE_CACHE_CHANGE SN 12 (Invalid)
|
||||
RTPS Operation REMOVE_CACHE_CHANGE SN 4
|
||||
SAMPLE MEMORY: 16(S7),32(S9),0(S10)/8,24
|
||||
PAYLOAD MEMORY: 11(S7),0(S9),33(S10)/44,22
|
||||
DDS Operation WRITE [TS 11s, Aligned Payload (2 Slots)] (ACCEPTED)
|
||||
SAMPLE MEMORY: 16(S7),32(S9),0(S10),8(S11)/24
|
||||
PAYLOAD MEMORY: 11(S7),0(S9),33(S10),44(S11),22(S11)/-
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,225 +0,0 @@
|
||||
SAMPLE MEMORY: -/0,9,18,27,36
|
||||
PAYLOAD MEMORY: -/0,11,22,33,44
|
||||
INSTANCE MEMORY: -/0,8,16
|
||||
RTPS Operation GET_MIN_SN (Expected SEQUENCENUMBER_UNKNOWN)
|
||||
RTPS Operation GET_MAX_SN (Expected SEQUENCENUMBER_UNKNOWN)
|
||||
DDS Operation WRITE [TS 1s, Instance 1, Aligned Payload] (REJECTED: Instance not Registered)
|
||||
DDS Operation WRITE [TS 1s, Instance 1, HANDLE_NIL, Aligned Payload] (ACCEPTED)
|
||||
SAMPLE MEMORY: 0(I1S1)/9,18,27,36
|
||||
PAYLOAD MEMORY: 0(I1S1)/11,22,33,44
|
||||
INSTANCE MEMORY: 0(I1)/8,16
|
||||
RTPS Operation GET_MIN_SN (Expected SN 1)
|
||||
RTPS Operation GET_MAX_SN (Expected SN 1)
|
||||
DDS Operation WRITE [TS 1s, Instance 1, Unaligned Payload (2 Slots)] (ACCEPTED)
|
||||
SAMPLE MEMORY: 0(I1S1),9(I1S2)/18,27,36
|
||||
PAYLOAD MEMORY: 0(I1S1),11(I1S2),22(I1S2)/33,44
|
||||
INSTANCE MEMORY: 0(I1)/8,16
|
||||
DDS Operation DISPOSE [TS 3s, Instance 2] (REJECTED: Instance not Registered)
|
||||
DDS Operation REGISTER_INSTANCE 2 (ACCEPTED)
|
||||
SAMPLE MEMORY: 0(I1S1),9(I1S2)/18,27,36
|
||||
PAYLOAD MEMORY: 0(I1S1),11(I1S2),22(I1S2)/33,44
|
||||
INSTANCE MEMORY: 8(I2),0(I1)/16
|
||||
DDS Operation DISPOSE [TS 3s, Instance 1] (ACCEPTED)
|
||||
SAMPLE MEMORY: 0(I1S1),9(I1S2),18(I2S3)/27,36
|
||||
PAYLOAD MEMORY: 0(I1S1),11(I1S2),22(I1S2),33(I2S3)/44
|
||||
INSTANCE MEMORY: 8(I2),0(I1)/16
|
||||
RTPS Operation GET_MIN_SN (Expected SN 1)
|
||||
RTPS Operation GET_MAX_SN (Expected SN 3)
|
||||
RTPS Operation GET_CACHE_CHANGE SN 4 (Invalid)
|
||||
RTPS Operation GET_CACHE_CHANGE SN 1
|
||||
RTPS Operation GET_CACHE_CHANGE SN 2
|
||||
RTPS Operation GET_CACHE_CHANGE SN 3
|
||||
DDS Operation WRITE [TS 4s, Instance 1, Aligned Payload] (ACCEPTED)
|
||||
SAMPLE MEMORY: 0(I1S1),9(I1S2),18(I2S3),27(I2S4)/36
|
||||
PAYLOAD MEMORY: 0(I1S1),11(I1S2),22(I1S2),33(I2S3),44(I2S4)/-
|
||||
INSTANCE MEMORY: 8(I2),0(I1)/16
|
||||
DDS Operation WRITE [TS 5s, Instance 3, HANDLE_NIL, Aligned Payload] (ACCEPTED)
|
||||
SAMPLE MEMORY: 9(I1S2),18(I2S3),27(I2S4),36(I3S5)/0
|
||||
PAYLOAD MEMORY: 11(I1S2),22(I1S2),33(I2S3),44(I2S4),0(I3S5)/-
|
||||
INSTANCE MEMORY: 16(I3),8(I2),0(I1)/-
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 3
|
||||
DDS Operation WRITE [TS 6s, Instance 3, Aligned Payload] (ACCEPTED)
|
||||
SAMPLE MEMORY: 9(I1S2),27(I2S4),36(I3S5),0(I3S6)/18
|
||||
PAYLOAD MEMORY: 11(I1S2),22(I1S2),44(I2S4),0(I3S5),33(I3S6)/-
|
||||
INSTANCE MEMORY: 16(I3),8(I2),0(I1)/-
|
||||
RTPS Operation GET_MIN_SN (Expected SN 2)
|
||||
RTPS Operation GET_MAX_SN (Expected SN 6)
|
||||
RTPS Operation GET_CACHE_CHANGE SN 2
|
||||
RTPS Operation GET_CACHE_CHANGE SN 4
|
||||
RTPS Operation GET_CACHE_CHANGE SN 5
|
||||
RTPS Operation GET_CACHE_CHANGE SN 6
|
||||
DDS Operation DISPOSE [TS 7s, Instance 1] (ACCEPTED)
|
||||
SAMPLE MEMORY: 27(I2S4),36(I3S5),0(I3S6),18(I1S7)/9
|
||||
PAYLOAD MEMORY: 44(I2S4),0(I3S5),33(I3S6),11(I1S7)/22
|
||||
INSTANCE MEMORY: 16(I3),8(I2),0(I1)/-
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 5
|
||||
DDS Operation WRITE [TS 8s, Instance 2, Aligned Payload (2 Slots)] (REJECTED: Payload Memory Full)
|
||||
RTPS Operation REMOVE_CACHE_CHANGE SN 3 (Invalid)
|
||||
RTPS Operation REMOVE_CACHE_CHANGE SN 5
|
||||
SAMPLE MEMORY: 27(I2S4),0(I3S6),18(I1S7)/9,36
|
||||
PAYLOAD MEMORY: 44(I2S4),33(I3S6),11(I1S7)/0,22
|
||||
INSTANCE MEMORY: 16(I3),8(I2),0(I1)/-
|
||||
DDS Operation WRITE [TS 8s, Instance 2, Aligned Payload (2 Slots)] (ACCEPTED)
|
||||
SAMPLE MEMORY: 27(I2S4),0(I3S6),18(I1S7),9(I2S8)/36
|
||||
PAYLOAD MEMORY: 44(I2S4),33(I3S6),11(I1S7),0(I2S8),22(I2S8)/-
|
||||
INSTANCE MEMORY: 16(I3),8(I2),0(I1)/-
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 7
|
||||
DDS Operation DISPOSE [TS 9s, Instance 3] (ACCEPTED)
|
||||
SAMPLE MEMORY: 27(I2S4),0(I3S6),9(I2S8),36(I3S9)/18
|
||||
PAYLOAD MEMORY: 44(I2S4),33(I3S6),0(I2S8),22(I2S8),11(I3S9)/-
|
||||
INSTANCE MEMORY: 16(I3),8(I2),0(I1)/-
|
||||
RTPS Operation GET_MIN_SN (Expected SN 4)
|
||||
RTPS Operation GET_MAX_SN (Expected SN 9)
|
||||
RTPS Operation GET_CACHE_CHANGE SN 4
|
||||
RTPS Operation GET_CACHE_CHANGE SN 6
|
||||
RTPS Operation GET_CACHE_CHANGE SN 8
|
||||
RTPS Operation GET_CACHE_CHANGE SN 9
|
||||
DDS Operation UNREGISTER_INSTANCE [TS 10s, Instance 1] (ACCEPTED)
|
||||
SAMPLE MEMORY: 0(I3S6),9(I2S8),36(I3S9),18(I1S10)/27
|
||||
PAYLOAD MEMORY: 33(I3S6),0(I2S8),22(I2S8),11(I3S9),44(I1S10)/-
|
||||
INSTANCE MEMORY: 16(I3),8(I2),0(I1)/-
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 9
|
||||
DDS Operation UNREGISTER_INSTANCE [TS 11s, Instance 2] (ACCEPTED)
|
||||
SAMPLE MEMORY: 0(I3S6),9(I2S8),18(I1S10),27(I2S11)/36
|
||||
PAYLOAD MEMORY: 33(I3S6),0(I2S8),22(I2S8),44(I1S10),11(I2S11)/-
|
||||
INSTANCE MEMORY: 16(I3),8(I2),0(I1)/-
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 6
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 8
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 11
|
||||
DDS Operation WRITE [TS 12s, Instance 4, HANDLE_NIL, Aligned Payload] (ACCEPTED)
|
||||
SAMPLE MEMORY: 18(I1S10),36(I4S12)/0,9,27
|
||||
PAYLOAD MEMORY: 44(I1S10),33(I4S12)/11,0,22
|
||||
INSTANCE MEMORY: 8(I4),16(I3),0(I1)/-
|
||||
RTPS Operation GET_MIN_SN (Expected SN 10)
|
||||
RTPS Operation GET_MAX_SN (Expected SN 12)
|
||||
RTPS Operation GET_CACHE_CHANGE SN 10
|
||||
RTPS Operation GET_CACHE_CHANGE SN 12
|
||||
DDS Operation REGISTER_INSTANCE 2 (REJECTED: MAX_INSTANCES exceeded)
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 10
|
||||
DDS Operation REGISTER_INSTANCE 2 (ACCEPTED)
|
||||
SAMPLE MEMORY: 36(I4S12)/0,9,27,18
|
||||
PAYLOAD MEMORY: 33(I4S12)/44,11,0,22
|
||||
INSTANCE MEMORY: 0(I2),8(I4),16(I3)/-
|
||||
DDS Operation WRITE [TS 13s, Instance 2, Aligned Payload] (ACCEPTED)
|
||||
SAMPLE MEMORY: 36(I4S12),0(I2S13)/9,27,18
|
||||
PAYLOAD MEMORY: 33(I4S12),44(I2S13)/11,0,22
|
||||
INSTANCE MEMORY: 0(I2),8(I4),16(I3)/-
|
||||
DDS Operation REGISTER_INSTANCE 2 (ACCEPTED)
|
||||
DDS Operation WRITE [TS 14s, Instance 2, Aligned Payload] (ACCEPTED)
|
||||
SAMPLE MEMORY: 36(I4S12),0(I2S13),9(I2S14)/27,18
|
||||
PAYLOAD MEMORY: 33(I4S12),44(I2S13),11(I2S14)/0,22
|
||||
INSTANCE MEMORY: 0(I2),8(I4),16(I3)/-
|
||||
DDS Operation WRITE [TS 15s, Instance 2, Aligned Payload] (ACCEPTED)
|
||||
SAMPLE MEMORY: 36(I4S12),9(I2S14),27(I2S15)/18,0
|
||||
PAYLOAD MEMORY: 33(I4S12),11(I2S14),0(I2S15)/44,22
|
||||
INSTANCE MEMORY: 0(I2),8(I4),16(I3)/-
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 15
|
||||
DDS Operation WRITE [TS 16s, Instance 2, Aligned Payload] (ACCEPTED)
|
||||
SAMPLE MEMORY: 36(I4S12),9(I2S14),18(I2S16)/0,27
|
||||
PAYLOAD MEMORY: 33(I4S12),11(I2S14),44(I2S16)/0,22
|
||||
INSTANCE MEMORY: 0(I2),8(I4),16(I3)/-
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 12
|
||||
DDS Operation UNREGISTER_INSTANCE [TS 17s, Instance 2] (ACCEPTED)
|
||||
SAMPLE MEMORY: 36(I4S12),18(I2S16),0(I2S17)/27,9
|
||||
PAYLOAD MEMORY: 33(I4S12),44(I2S16),0(I2S17)/11,22
|
||||
INSTANCE MEMORY: 0(I2),8(I4),16(I3)/-
|
||||
RTPS Operation GET_MIN_SN (Expected SN 12)
|
||||
RTPS Operation GET_MAX_SN (Expected SN 17)
|
||||
RTPS Operation GET_CACHE_CHANGE SN 12
|
||||
RTPS Operation GET_CACHE_CHANGE SN 16
|
||||
RTPS Operation GET_CACHE_CHANGE SN 17
|
||||
DDS Operation UNREGISTER_INSTANCE [TS 18s, Instance 4] (ACCEPTED)
|
||||
SAMPLE MEMORY: 36(I4S12),18(I2S16),0(I2S17),27(I4S18)/9
|
||||
PAYLOAD MEMORY: 33(I4S12),44(I2S16),0(I2S17),11(I4S178)/22
|
||||
INSTANCE MEMORY: 0(I2),8(I4),16(I3)/-
|
||||
RTPS Operation NACK_CACHE_CHANGE SN 12
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 18
|
||||
DDS Operation UNREGISTER_INSTANCE [TS 19s, Instance 3] (ACCEPTED)
|
||||
SAMPLE MEMORY: 36(I4S12),18(I2S16),0(I2S17),9(I3S19)/27
|
||||
PAYLOAD MEMORY: 33(I4S12),44(I2S16),0(I2S17),22(I3S19)/11
|
||||
INSTANCE MEMORY: 0(I2),8(I4),16(I3)/-
|
||||
DDS Operation WRITE [TS 20s, Instance 3, Aligned Payload] (ACCEPTED)
|
||||
SAMPLE MEMORY: 18(I2S16),0(I2S17),9(I3S19),27(I3S20)/36
|
||||
PAYLOAD MEMORY: 44(I2S16),0(I2S17),22(I3S19),11(I3S20)/33
|
||||
INSTANCE MEMORY: 0(I2),8(I4),16(I3)/-
|
||||
DDS Operation WRITE [TS 21s, Instance 3, Aligned Payload] (ACCEPTED)
|
||||
SAMPLE MEMORY: 18(I2S16),0(I2S17),27(I3S20),36(I3S21)/9
|
||||
PAYLOAD MEMORY: 44(I2S16),0(I2S17),11(I3S20),33(I3S21)/22
|
||||
INSTANCE MEMORY: 0(I2),8(I4),16(I3)/-
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 16
|
||||
DDS Operation WRITE [TS 22s, Instance 3, Aligned Payload] (ACCEPTED)
|
||||
SAMPLE MEMORY: 18(I2S16),0(I2S17),36(I3S21),9(I3S22)/27
|
||||
PAYLOAD MEMORY: 44(I2S16),0(I2S17),33(I3S21),22(I3S22)/11
|
||||
INSTANCE MEMORY: 0(I2),8(I4),16(I3)/-
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 22
|
||||
DDS Operation WRITE [TS 23s, Instance 3, Aligned Payload] (ACCEPTED)
|
||||
SAMPLE MEMORY: 18(I2S16),0(I2S17),36(I3S21),27(I3S23)/9
|
||||
PAYLOAD MEMORY: 44(I2S16),0(I2S17),33(I3S21),11(I3S23)/22
|
||||
INSTANCE MEMORY: 0(I2),8(I4),16(I3)/-
|
||||
RTPS Operation GET_MIN_SN (Expected SN 16)
|
||||
RTPS Operation GET_MAX_SN (Expected SN 23)
|
||||
RTPS Operation GET_CACHE_CHANGE SN 21
|
||||
RTPS Operation GET_CACHE_CHANGE SN 22
|
||||
RTPS Operation GET_CACHE_CHANGE SN 23
|
||||
DDS Operation UNREGISTER_INSTANCE [TS 24s, HANDLE_NIL, Instance 1] (REJECTED: Instance not Registered)
|
||||
DDS Operation WRITE [TS 24s, Instance 1, HANDLE_NIL, Aligned Payload] (ACCEPTED)
|
||||
SAMPLE MEMORY: 0(I2S17),36(I3S21),27(I3S23),9(I1S24)/18
|
||||
PAYLOAD MEMORY: 0(I2S17),33(I3S21),11(I3S23),22(I1S24)/44
|
||||
INSTANCE MEMORY: 8(I1),0(I2),16(I3)/-
|
||||
DDS Operation WRITE [TS 25s, Instance 4, HANDLE_NIL Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 21
|
||||
DDS Operation WRITE [TS 25s, Instance 4, HANDLE_NIL Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 17
|
||||
DDS Operation WRITE [TS 25s, Instance 4, HANDLE_NIL, Aligned Payload] (ACCEPTED)
|
||||
SAMPLE MEMORY: 36(I3S21),27(I3S23),9(I1S24),18(I4S25)/0
|
||||
PAYLOAD MEMORY: 33(I3S21),11(I3S23),22(I1S24),22(I4S25)/0
|
||||
INSTANCE MEMORY: 0(I4),8(I1),16(I3)/-
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 21
|
||||
DDS Operation WRITE [TS 26s, Instance 2, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 24
|
||||
DDS Operation WRITE [TS 26s, Instance 2, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)
|
||||
DDS Operation UNREGISTER_INSTANCE [TS 26s, Instance 1] (ACCEPTED)
|
||||
SAMPLE MEMORY: 27(I3S23),9(I1S24),18(I4S25),0(I1S26)/36
|
||||
PAYLOAD MEMORY: 11(I3S23),22(I1S24),22(I4S25),0(I1S26)/33
|
||||
INSTANCE MEMORY: 0(I4),8(I1),16(I3)/-
|
||||
DDS Operation REGISTER_INSTANCE 1 (ACCEPTED)
|
||||
DDS Operation WRITE [TS 27s, Instance 2, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)
|
||||
DDS Operation UNREGISTER_INSTANCE [TS 27s, Instance 3] (ACCEPTED)
|
||||
SAMPLE MEMORY: 27(I3S23),18(I4S25),0(I1S26),36(I3S27)/9
|
||||
PAYLOAD MEMORY: 11(I3S23),22(I4S25),0(I1S26),33(I3S27)/22
|
||||
INSTANCE MEMORY: 0(I4),8(I1),16(I3)/-
|
||||
DDS Operation DISPOSE [TS 28s, Instance 3] (ACCEPTED)
|
||||
SAMPLE MEMORY: 18(I4S25),0(I1S26),36(I3S27),9(I3S28)/27
|
||||
PAYLOAD MEMORY: 22(I4S25),0(I1S26),33(I3S27),22(I3S28)/11
|
||||
INSTANCE MEMORY: 0(I4),8(I1),16(I3)/-
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 27
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 28
|
||||
DDS Operation WRITE [TS 29s, Instance 2, HANDLE_NIL, Aligned Payload] (ACCEPTED)
|
||||
SAMPLE MEMORY: 18(I4S25),0(I1S26),27(I2S29)/36,9
|
||||
PAYLOAD MEMORY: 22(I4S25),0(I1S26),11(I2S29)/22,33
|
||||
INSTANCE MEMORY: 16(I2),0(I4),8(I1)/-
|
||||
RTPS Operation GET_MIN_SN (Expected SN 25)
|
||||
RTPS Operation GET_MAX_SN (Expected SN 29)
|
||||
RTPS Operation GET_CACHE_CHANGE SN 25
|
||||
RTPS Operation GET_CACHE_CHANGE SN 26
|
||||
RTPS Operation GET_CACHE_CHANGE SN 29
|
||||
DDS Operation WRITE [TS 30s, Instance 2, Aligned Payload] (ACCEPTED)
|
||||
SAMPLE MEMORY: 18(I4S25),0(I1S26),27(I2S29),36(I2S30)/9
|
||||
PAYLOAD MEMORY: 22(I4S25),0(I1S26),11(I2S29),22(I2S30)/33
|
||||
INSTANCE MEMORY: 16(I2),0(I4),8(I1)/-
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 25
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 26
|
||||
DDS Operation WRITE [TS 31s, Instance 4, Aligned Payload] (ACCEPTED)
|
||||
SAMPLE MEMORY: 0(I1S26),27(I2S29),36(I2S30),9(I4S31)/18
|
||||
PAYLOAD MEMORY: 0(I1S26),11(I2S29),22(I2S30),33(I4S31)/22
|
||||
INSTANCE MEMORY: 16(I2),0(I4),8(I1)/-
|
||||
RTPS Operation REMOVE_CACHE_CHANGE SN 31
|
||||
SAMPLE MEMORY: 0(I1S26),27(I2S29),36(I2S30)/18,9
|
||||
PAYLOAD MEMORY: 0(I1S26),11(I2S29),22(I2S30)/33,22
|
||||
INSTANCE MEMORY: 16(I2),0(I4),8(I1)/-
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 29
|
||||
RTPS Operation ACK_CACHE_CHANGE SN 30
|
||||
DDS Operation WRITE [TS 32s, Instance 2, Aligned Payload] (ACCEPTED)
|
||||
SAMPLE MEMORY: 0(I1S26),36(I2S30),18(I2S32)/9,27
|
||||
PAYLOAD MEMORY: 0(I1S26),22(I2S30),33(I2S32)/11,22
|
||||
INSTANCE MEMORY: 16(I2),0(I4),8(I1)/-
|
||||
File diff suppressed because it is too large
Load Diff
709
src/Tests/Level_0/L0_dds_writer_test2.vhd
Normal file
709
src/Tests/Level_0/L0_dds_writer_test2.vhd
Normal file
@ -0,0 +1,709 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library osvvm; -- Utility Library
|
||||
context osvvm.OsvvmContext;
|
||||
|
||||
use work.rtps_package.all;
|
||||
use work.user_config.all;
|
||||
use work.rtps_config_package.all;
|
||||
use work.rtps_test_package.all;
|
||||
|
||||
-- This testbench tests the DDS WAIT_FOR_ACKNOWLEDGEMENTS Operation of the DDS Writer.
|
||||
|
||||
entity L0_dds_writer_test2 is
|
||||
end entity;
|
||||
|
||||
architecture testbench of L0_dds_writer_test2 is
|
||||
|
||||
-- *CONSTANT DECLARATION*
|
||||
constant MAX_REMOTE_ENDPOINTS : natural := 3;
|
||||
constant NUM_WRITERS : natural := 2;
|
||||
|
||||
impure function gen_test_config return CONFIG_ARRAY_TYPE is
|
||||
variable ret : CONFIG_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => DEFAULT_WRITER_CONFIG);
|
||||
begin
|
||||
-- aik
|
||||
ret(0).HISTORY_QOS := KEEP_ALL_HISTORY_QOS;
|
||||
ret(0).DEADLINE_QOS := DURATION_INFINITE;
|
||||
ret(0).LIFESPAN_QOS := DURATION_INFINITE;
|
||||
ret(0).LEASE_DURATION := DURATION_INFINITE;
|
||||
ret(0).WITH_KEY := TRUE;
|
||||
ret(0).MAX_SAMPLES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH));
|
||||
ret(0).MAX_INSTANCES := std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH));
|
||||
ret(0).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH));
|
||||
ret(0).MAX_PAYLOAD_SIZE := 40;
|
||||
-- ain
|
||||
ret(1).HISTORY_QOS := KEEP_ALL_HISTORY_QOS;
|
||||
ret(1).DEADLINE_QOS := DURATION_INFINITE;
|
||||
ret(1).LIFESPAN_QOS := DURATION_INFINITE;
|
||||
ret(1).LEASE_DURATION := DURATION_INFINITE;
|
||||
ret(1).WITH_KEY := FALSE;
|
||||
ret(1).MAX_SAMPLES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH));
|
||||
ret(1).MAX_INSTANCES := std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH));
|
||||
ret(1).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH));
|
||||
ret(1).MAX_PAYLOAD_SIZE := 40;
|
||||
return ret;
|
||||
end function;
|
||||
constant TEST_CONFIG : CONFIG_ARRAY_TYPE := gen_test_config;
|
||||
|
||||
-- *TYPE DECLARATION*
|
||||
type DDS_STAGE_TYPE is (IDLE, START, PUSH, DONE);
|
||||
type RTPS_STAGE_TYPE is (IDLE, START, DONE, CHECK);
|
||||
|
||||
-- *SIGNAL DECLARATION*
|
||||
signal clk : std_logic := '0';
|
||||
signal reset : std_logic := '1';
|
||||
signal check_time : TIME_TYPE := TIME_ZERO;
|
||||
signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds, w_map : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0');
|
||||
signal opcode_rtps : HISTORY_CACHE_OPCODE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => NOP);
|
||||
signal opcode_dds : DDS_WRITER_OPCODE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => NOP);
|
||||
signal ret_rtps : HISTORY_CACHE_RESPONSE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => ERROR);
|
||||
signal seq_nr_rtps, cc_seq_nr : SEQUENCENUMBER_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => SEQUENCENUMBER_UNKNOWN);
|
||||
signal ready_out_rtps, valid_out_rtps, last_word_out_rtps : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0');
|
||||
signal ready_in_dds, ready_out_dds, valid_in_dds, valid_out_dds, last_word_in_dds, last_word_out_dds : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0');
|
||||
signal data_out_rtps, data_in_dds, data_out_dds : WORD_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => (others => '0'));
|
||||
signal get_data_rtps, liveliness_assertion, data_available : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0');
|
||||
signal cc_source_timestamp, source_ts_dds : TIME_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => TIME_INVALID);
|
||||
signal cc_kind : CACHE_CHANGE_KIND_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => ALIVE);
|
||||
signal cc_instance_handle, instance_handle_in_dds, instance_handle_out_dds : INSTANCE_HANDLE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => HANDLE_NIL);
|
||||
signal max_wait_dds : DURATION_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => DURATION_INFINITE);
|
||||
signal return_code_dds : RETURN_CODE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => (others => '0'));
|
||||
signal status : STATUS_KIND_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => (others => '0'));
|
||||
|
||||
signal ind : natural := 0;
|
||||
signal dds1_start, dds2_start, dds1_done, dds2_done, rtps_start, rtps_done : std_logic := '0';
|
||||
signal dds1_cnt, dds2_cnt, rtps_cnt : natural := 0;
|
||||
signal dds1_stage, dds2_stage : DDS_STAGE_TYPE := IDLE;
|
||||
signal rtps_stage : RTPS_STAGE_TYPE := IDLE;
|
||||
shared variable dds1, dds2 : DDS_WRITER_TEST_TYPE := DEFAULT_DDS_WRITER_TEST;
|
||||
shared variable rtps : RTPS_WRITER_TEST_TYPE := DEFAULT_RTPS_WRITER_TEST;
|
||||
signal inst_id, kind_id, sn_id, ts_id, data_id, ret_id, ih_id : AlertLogIDType;
|
||||
|
||||
-- *FUNCTION DECLARATION*
|
||||
function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is
|
||||
variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
|
||||
begin
|
||||
for i in 0 to 3 loop
|
||||
ret(i) := not payload.data(i);
|
||||
end loop;
|
||||
|
||||
return ret;
|
||||
end function;
|
||||
|
||||
function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is
|
||||
variable ret : SEQUENCENUMBER_TYPE;
|
||||
begin
|
||||
ret(0) := (others => '0');
|
||||
ret(1) := unsigned(int(input, WORD_WIDTH));
|
||||
return ret;
|
||||
end function;
|
||||
|
||||
procedure wait_on_sig(signal sig : std_logic) is
|
||||
begin
|
||||
if (sig /= '1') then
|
||||
wait on sig until sig = '1';
|
||||
end if;
|
||||
end procedure;
|
||||
|
||||
begin
|
||||
|
||||
-- Unit Under Test
|
||||
uut : entity work.dds_writer(arch)
|
||||
generic map(
|
||||
NUM_WRITERS => NUM_WRITERS,
|
||||
CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(TEST_CONFIG)
|
||||
)
|
||||
port map (
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
time => check_time,
|
||||
start_rtps => start_rtps,
|
||||
opcode_rtps => opcode_rtps,
|
||||
ack_rtps => ack_rtps,
|
||||
done_rtps => done_rtps,
|
||||
ret_rtps => ret_rtps,
|
||||
seq_nr_rtps => seq_nr_rtps,
|
||||
get_data_rtps => get_data_rtps,
|
||||
data_out_rtps => data_out_rtps,
|
||||
valid_out_rtps => valid_out_rtps,
|
||||
ready_out_rtps => ready_out_rtps,
|
||||
last_word_out_rtps => last_word_out_rtps,
|
||||
liveliness_assertion => liveliness_assertion,
|
||||
data_available => data_available,
|
||||
cc_instance_handle => cc_instance_handle,
|
||||
cc_kind => cc_kind,
|
||||
cc_source_timestamp => cc_source_timestamp,
|
||||
cc_seq_nr => cc_seq_nr,
|
||||
start_dds => start_dds,
|
||||
ack_dds => ack_dds,
|
||||
opcode_dds => opcode_dds,
|
||||
instance_handle_in_dds => instance_handle_in_dds,
|
||||
source_ts_dds => source_ts_dds,
|
||||
max_wait_dds => max_wait_dds,
|
||||
done_dds => done_dds,
|
||||
return_code_dds => return_code_dds,
|
||||
instance_handle_out_dds => instance_handle_out_dds,
|
||||
ready_in_dds => ready_in_dds,
|
||||
valid_in_dds => valid_in_dds,
|
||||
data_in_dds => data_in_dds,
|
||||
last_word_in_dds => last_word_in_dds,
|
||||
ready_out_dds => ready_out_dds,
|
||||
valid_out_dds => valid_out_dds,
|
||||
data_out_dds => data_out_dds,
|
||||
last_word_out_dds => last_word_out_dds,
|
||||
status => status
|
||||
);
|
||||
|
||||
stimulus_prc : process
|
||||
variable RV : RandomPType;
|
||||
variable kh1, kh2, kh3, kh4 : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
|
||||
variable cc1, cc2, cc3, cc4, cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE;
|
||||
|
||||
alias idle_sig is <<signal uut.idle_sig : std_logic>>;
|
||||
|
||||
impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is
|
||||
variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
|
||||
begin
|
||||
assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE;
|
||||
|
||||
for i in 0 to len-1 loop
|
||||
if (i < 4) then
|
||||
-- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc
|
||||
ret.data(ret.length) := not key_hash(i);
|
||||
else
|
||||
ret.data(ret.length) := RV.RandSlv(WORD_WIDTH);
|
||||
end if;
|
||||
ret.length := ret.length + 1;
|
||||
end loop;
|
||||
ret.last(ret.length-1) := '1';
|
||||
|
||||
return ret;
|
||||
end function;
|
||||
|
||||
impure function gen_key_hash return KEY_HASH_TYPE is
|
||||
variable ret : KEY_HASH_TYPE := KEY_HASH_NIL;
|
||||
begin
|
||||
for i in 0 to KEY_HASH_TYPE'length-1 loop
|
||||
ret(i) := RV.RandSlv(WORD_WIDTH);
|
||||
end loop;
|
||||
return ret;
|
||||
end function;
|
||||
|
||||
procedure start_dds1 is
|
||||
begin
|
||||
dds1_start <= '1';
|
||||
wait until rising_edge(clk);
|
||||
dds1_start <= '0';
|
||||
wait until rising_edge(clk);
|
||||
end procedure;
|
||||
|
||||
procedure start_dds2 is
|
||||
begin
|
||||
dds2_start <= '1';
|
||||
wait until rising_edge(clk);
|
||||
dds2_start <= '0';
|
||||
wait until rising_edge(clk);
|
||||
end procedure;
|
||||
|
||||
procedure start_rtps is
|
||||
begin
|
||||
rtps_start <= '1';
|
||||
wait until rising_edge(clk);
|
||||
rtps_start <= '0';
|
||||
wait until rising_edge(clk);
|
||||
end procedure;
|
||||
|
||||
procedure wait_on_completion is
|
||||
begin
|
||||
if (rtps_done /= '1' or dds1_done /= '1' or dds2_done /= '1') then
|
||||
wait until rtps_done = '1' and dds1_done = '1' and dds2_done = '1';
|
||||
end if;
|
||||
end procedure;
|
||||
|
||||
-- NOTE: This procedure waits until the idle_sig is high for at least
|
||||
-- two consecutive clock cycles.
|
||||
procedure wait_on_idle is
|
||||
variable first : boolean := TRUE;
|
||||
begin
|
||||
loop
|
||||
if (idle_sig /= '1') then
|
||||
wait until idle_sig = '1';
|
||||
elsif (not first) then
|
||||
exit;
|
||||
end if;
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
first := FALSE;
|
||||
end loop;
|
||||
end procedure;
|
||||
|
||||
begin
|
||||
|
||||
SetAlertLogName("L0_dds_writer_test2 - Wait For Acknowledgements");
|
||||
SetAlertEnable(FAILURE, TRUE);
|
||||
SetAlertEnable(ERROR, TRUE);
|
||||
SetAlertEnable(WARNING, TRUE);
|
||||
SetLogEnable(DEBUG, FALSE);
|
||||
SetLogEnable(PASSED, FALSE);
|
||||
SetLogEnable(INFO, TRUE);
|
||||
RV.InitSeed(RV'instance_name);
|
||||
inst_id <= GetAlertLogID("Instance", ALERTLOG_BASE_ID);
|
||||
kind_id <= GetAlertLogID("Cache Change Kind", ALERTLOG_BASE_ID);
|
||||
sn_id <= GetAlertLogID("SequenceNumber", ALERTLOG_BASE_ID);
|
||||
ts_id <= GetAlertLogID("TimeStamp", ALERTLOG_BASE_ID);
|
||||
ih_id <= GetAlertLogID("Instance Handle", ALERTLOG_BASE_ID);
|
||||
data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID);
|
||||
ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID);
|
||||
|
||||
-- Key Hashes
|
||||
kh1 := gen_key_hash;
|
||||
kh2 := gen_key_hash;
|
||||
kh3 := gen_key_hash;
|
||||
kh4 := gen_key_hash;
|
||||
|
||||
|
||||
Log("Initiating Test", INFO);
|
||||
Log("Current Time: 0s", INFO);
|
||||
max_wait_dds <= (others => DURATION_ZERO);
|
||||
check_time <= TIME_ZERO;
|
||||
reset <= '1';
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
reset <= '0';
|
||||
|
||||
Log("W0,W1: DDS Operation WAIT_FOR_ACKNOWLEDGEMENTS [max_wait 0s]", INFO);
|
||||
Log("W0,W1: OK", DEBUG);
|
||||
dds1 := DEFAULT_DDS_WRITER_TEST;
|
||||
dds1.opcode := WAIT_FOR_ACKNOWLEDGEMENTS;
|
||||
dds1.ret_code := RETCODE_OK;
|
||||
dds2 := dds1;
|
||||
max_wait_dds <= (others => gen_duration(0 sec));
|
||||
start_dds1;
|
||||
start_dds2;
|
||||
wait_on_sig(dds1_done);
|
||||
wait_on_sig(dds2_done);
|
||||
wait_on_idle;
|
||||
|
||||
cc := DEFAULT_CACHE_CHANGE;
|
||||
cc.serialized_key := FALSE;
|
||||
cc.kind := ALIVE;
|
||||
cc.instance := kh1;
|
||||
cc.payload := gen_payload(kh1,10);
|
||||
cc.seq_nr := gen_sn(1);
|
||||
cc.src_timestamp := gen_duration(1 sec);
|
||||
|
||||
Log("W0,W1: DDS Operation WRITE [TS 1s, Instance 1, HANDLE_NIL, Aligned Payload]", INFO);
|
||||
Log("W0,W1: ACCEPTED", DEBUG);
|
||||
dds1 := DEFAULT_DDS_WRITER_TEST;
|
||||
dds1.opcode := WRITE;
|
||||
dds1.cc := cc;
|
||||
dds1.cc.instance:= HANDLE_NIL;
|
||||
dds1.ret_code := RETCODE_OK;
|
||||
dds2 := dds1;
|
||||
start_dds1;
|
||||
start_dds2;
|
||||
wait_on_sig(dds1_done);
|
||||
wait_on_sig(dds2_done);
|
||||
wait_on_idle;
|
||||
cc1 := cc;
|
||||
|
||||
cc := DEFAULT_CACHE_CHANGE;
|
||||
cc.serialized_key := FALSE;
|
||||
cc.kind := ALIVE;
|
||||
cc.instance := kh2;
|
||||
cc.payload := gen_payload(kh2,10);
|
||||
cc.seq_nr := gen_sn(2);
|
||||
cc.src_timestamp := gen_duration(2 sec);
|
||||
|
||||
Log("W0,W1: DDS Operation WRITE [TS 2s, Instance 2, HANDLE_NIL, Aligned Payload]", INFO);
|
||||
Log("W0,W1: ACCEPTED", DEBUG);
|
||||
dds1 := DEFAULT_DDS_WRITER_TEST;
|
||||
dds1.opcode := WRITE;
|
||||
dds1.cc := cc;
|
||||
dds1.cc.instance:= HANDLE_NIL;
|
||||
dds1.ret_code := RETCODE_OK;
|
||||
dds2 := dds1;
|
||||
start_dds1;
|
||||
start_dds2;
|
||||
wait_on_sig(dds1_done);
|
||||
wait_on_sig(dds2_done);
|
||||
wait_on_idle;
|
||||
cc2 := cc;
|
||||
|
||||
Log("W0,W1: DDS Operation WAIT_FOR_ACKNOWLEDGEMENTS [max_wait 0s]", INFO);
|
||||
Log("W0,W1: WAIT_FOR_ACKNOWLEDGEMENTS Return TIMEOUT", DEBUG);
|
||||
dds1 := DEFAULT_DDS_WRITER_TEST;
|
||||
dds1.opcode := WAIT_FOR_ACKNOWLEDGEMENTS;
|
||||
dds1.ret_code := RETCODE_TIMEOUT;
|
||||
max_wait_dds <= (others => gen_duration(0 sec));
|
||||
dds2 := dds1;
|
||||
start_dds1;
|
||||
start_dds2;
|
||||
wait_on_sig(dds1_done);
|
||||
wait_on_sig(dds2_done);
|
||||
wait_on_idle;
|
||||
|
||||
Log("W0: DDS Operation WAIT_FOR_ACKNOWLEDGEMENTS [max_wait 1s]", INFO);
|
||||
Log("W1: DDS Operation WAIT_FOR_ACKNOWLEDGEMENTS [max_wait 2s]", INFO);
|
||||
dds1 := DEFAULT_DDS_WRITER_TEST;
|
||||
dds1.opcode := WAIT_FOR_ACKNOWLEDGEMENTS;
|
||||
dds1.ret_code := RETCODE_TIMEOUT;
|
||||
max_wait_dds(0) <= gen_duration(1 sec);
|
||||
dds2 := DEFAULT_DDS_WRITER_TEST;
|
||||
dds2.opcode := WAIT_FOR_ACKNOWLEDGEMENTS;
|
||||
dds2.ret_code := RETCODE_OK;
|
||||
max_wait_dds(1) <= gen_duration(2 sec);
|
||||
start_dds1;
|
||||
start_dds2;
|
||||
wait_on_idle;
|
||||
AlertIf(dds1_done = '1', "Writer 0 not waiting", FAILURE);
|
||||
AlertIf(dds2_done = '1', "Writer 1 not waiting", FAILURE);
|
||||
|
||||
Log("W0,W1: RTPS Operation ACK_CACHE_CHANGE SN 1", INFO);
|
||||
rtps := DEFAULT_RTPS_WRITER_TEST;
|
||||
rtps.opcode := ACK_CACHE_CHANGE;
|
||||
rtps.cc := cc1;
|
||||
-- WRITER 0
|
||||
ind <= 0;
|
||||
start_rtps;
|
||||
wait_on_sig(rtps_done);
|
||||
-- WRITER 1
|
||||
ind <= 1;
|
||||
start_rtps;
|
||||
wait_on_sig(rtps_done);
|
||||
wait_on_idle;
|
||||
|
||||
Log("Current Time: 1s", INFO);
|
||||
Log("W0: WAIT_FOR_ACKNOWLEDGEMENTS Return TIMEOUT", DEBUG);
|
||||
check_time <= gen_duration(1 sec);
|
||||
wait until rising_edge(clk);
|
||||
wait_on_sig(dds1_done);
|
||||
wait_on_idle;
|
||||
AlertIf(dds2_done = '1', "Writer 1 not waiting", FAILURE);
|
||||
|
||||
cc := DEFAULT_CACHE_CHANGE;
|
||||
cc.serialized_key := FALSE;
|
||||
cc.kind := ALIVE;
|
||||
cc.instance := kh1;
|
||||
cc.payload := gen_payload(kh1,10);
|
||||
cc.seq_nr := gen_sn(3);
|
||||
cc.src_timestamp := gen_duration(3 sec);
|
||||
|
||||
Log("W0: DDS Operation WRITE [TS 3s, Instance 1, HANDLE_NIL, Aligned Payload]", INFO);
|
||||
Log("W0: ACCEPTED", DEBUG);
|
||||
dds1 := DEFAULT_DDS_WRITER_TEST;
|
||||
dds1.opcode := WRITE;
|
||||
dds1.cc := cc;
|
||||
dds1.cc.instance:= HANDLE_NIL;
|
||||
dds1.ret_code := RETCODE_OK;
|
||||
start_dds1;
|
||||
wait_on_sig(dds1_done);
|
||||
wait_on_idle;
|
||||
cc3 := cc;
|
||||
AlertIf(dds2_done = '1', "Writer 1 not waiting", FAILURE);
|
||||
|
||||
Log("W0: DDS Operation WAIT_FOR_ACKNOWLEDGEMENTS [max_wait 2s]", INFO);
|
||||
dds1 := DEFAULT_DDS_WRITER_TEST;
|
||||
dds1.opcode := WAIT_FOR_ACKNOWLEDGEMENTS;
|
||||
dds1.ret_code := RETCODE_OK;
|
||||
max_wait_dds(0) <= gen_duration(2 sec);
|
||||
start_dds1;
|
||||
AlertIf(dds1_done = '1', "Writer 0 not waiting", FAILURE);
|
||||
AlertIf(dds2_done = '1', "Writer 1 not waiting", FAILURE);
|
||||
|
||||
Log("W0,W1: RTPS Operation ACK_CACHE_CHANGE SN 2", INFO);
|
||||
Log("W1: WAIT_FOR_ACKNOWLEDGEMENTS Return OK", DEBUG);
|
||||
rtps := DEFAULT_RTPS_WRITER_TEST;
|
||||
rtps.opcode := ACK_CACHE_CHANGE;
|
||||
rtps.cc := cc2;
|
||||
-- WRITER 0
|
||||
ind <= 0;
|
||||
start_rtps;
|
||||
wait_on_sig(rtps_done);
|
||||
-- WRITER 1
|
||||
ind <= 1;
|
||||
start_rtps;
|
||||
wait_on_sig(rtps_done);
|
||||
wait_on_sig(dds2_done);
|
||||
wait_on_idle;
|
||||
AlertIf(dds1_done = '1', "Writer 0 not waiting", FAILURE);
|
||||
|
||||
Log("W1: RTPS Operation NACK_CACHE_CHANGE SN 1", INFO);
|
||||
rtps := DEFAULT_RTPS_WRITER_TEST;
|
||||
rtps.opcode := NACK_CACHE_CHANGE;
|
||||
rtps.cc.seq_nr := gen_sn(1);
|
||||
-- WRITER 1
|
||||
ind <= 1;
|
||||
start_rtps;
|
||||
wait_on_sig(rtps_done);
|
||||
wait_on_idle;
|
||||
AlertIf(dds1_done = '1', "Writer 0 not waiting", FAILURE);
|
||||
|
||||
Log("W1: DDS Operation WAIT_FOR_ACKNOWLEDGEMENTS [max_wait 1s]", INFO);
|
||||
dds2 := DEFAULT_DDS_WRITER_TEST;
|
||||
dds2.opcode := WAIT_FOR_ACKNOWLEDGEMENTS;
|
||||
dds2.ret_code := RETCODE_TIMEOUT;
|
||||
max_wait_dds(1) <= gen_duration(1 sec);
|
||||
start_dds2;
|
||||
AlertIf(dds1_done = '1', "Writer 0 not waiting", FAILURE);
|
||||
AlertIf(dds2_done = '1', "Writer 1 not waiting", FAILURE);
|
||||
|
||||
Log("Current Time: 2s", INFO);
|
||||
Log("W1: WAIT_FOR_ACKNOWLEDGEMENTS Return TIMEOUT", DEBUG);
|
||||
check_time <= gen_duration(2 sec);
|
||||
wait until rising_edge(clk);
|
||||
wait_on_sig(dds2_done);
|
||||
wait_on_idle;
|
||||
AlertIf(dds1_done = '1', "Writer 0 not waiting", FAILURE);
|
||||
|
||||
Log("W0: RTPS Operation ACK_CACHE_CHANGE SN 3", INFO);
|
||||
Log("W0: WAIT_FOR_ACKNOWLEDGEMENTS Return OK", DEBUG);
|
||||
rtps := DEFAULT_RTPS_WRITER_TEST;
|
||||
rtps.opcode := ACK_CACHE_CHANGE;
|
||||
rtps.cc := cc3;
|
||||
-- WRITER 0
|
||||
ind <= 0;
|
||||
start_rtps;
|
||||
wait_on_sig(rtps_done);
|
||||
wait_on_sig(dds1_done);
|
||||
wait_on_idle;
|
||||
|
||||
wait_on_completion;
|
||||
TranscriptOpen(RESULTS_FILE, APPEND_MODE);
|
||||
SetTranscriptMirror;
|
||||
ReportAlerts;
|
||||
TranscriptClose;
|
||||
std.env.stop;
|
||||
wait;
|
||||
end process;
|
||||
|
||||
clock_prc : process
|
||||
begin
|
||||
clk <= '0';
|
||||
wait for 25 ns;
|
||||
clk <= '1';
|
||||
wait for 25 ns;
|
||||
end process;
|
||||
|
||||
dds1_prc : process(all)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
dds1_done <= '0';
|
||||
case (dds1_stage) is
|
||||
when IDLE =>
|
||||
if (dds1_start = '1') then
|
||||
dds1_stage <= START;
|
||||
else
|
||||
dds1_done <= '1';
|
||||
end if;
|
||||
when START =>
|
||||
if (ack_dds(0) = '1') then
|
||||
case (dds1.opcode) is
|
||||
when WAIT_FOR_ACKNOWLEDGEMENTS =>
|
||||
dds1_stage <= DONE;
|
||||
dds1_cnt <= 0;
|
||||
when others =>
|
||||
dds1_stage <= PUSH;
|
||||
dds1_cnt <= 0;
|
||||
end case;
|
||||
end if;
|
||||
when PUSH =>
|
||||
if (ready_in_dds(0) = '1') then
|
||||
dds1_cnt <= dds1_cnt + 1;
|
||||
if (dds1_cnt = dds1.cc.payload.length-1) then
|
||||
-- DEFAULT
|
||||
dds1_stage <= DONE;
|
||||
end if;
|
||||
end if;
|
||||
when DONE =>
|
||||
if (done_dds(0) = '1') then
|
||||
if (dds1.opcode = REGISTER_INSTANCE or dds1.opcode = LOOKUP_INSTANCE) then
|
||||
AffirmIfEqual(ih_id, to_unsigned(instance_handle_out_dds(0)), to_unsigned(dds1.cc.instance));
|
||||
else
|
||||
AffirmIfEqual(ret_id, return_code_dds(0), dds1.ret_code);
|
||||
end if;
|
||||
dds1_stage <= IDLE;
|
||||
end if;
|
||||
end case;
|
||||
end if;
|
||||
|
||||
-- DEFAULT
|
||||
start_dds(0) <= '0';
|
||||
opcode_dds(0) <= NOP;
|
||||
valid_in_dds(0) <= '0';
|
||||
last_word_in_dds(0) <= '0';
|
||||
data_in_dds(0) <= (others => '0');
|
||||
instance_handle_in_dds(0) <= HANDLE_NIL;
|
||||
source_ts_dds(0) <= TIME_INVALID;
|
||||
ready_out_dds(0) <= '0';
|
||||
|
||||
case (dds1_stage) is
|
||||
when START =>
|
||||
start_dds(0) <= '1';
|
||||
opcode_dds(0) <= dds1.opcode;
|
||||
instance_handle_in_dds(0) <= dds1.cc.instance;
|
||||
source_ts_dds(0) <= dds1.cc.src_timestamp;
|
||||
when PUSH =>
|
||||
valid_in_dds(0) <= '1';
|
||||
data_in_dds(0) <= dds1.cc.payload.data(dds1_cnt);
|
||||
last_word_in_dds(0) <= dds1.cc.payload.last(dds1_cnt);
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
dds2_prc : process(all)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
dds2_done <= '0';
|
||||
case (dds2_stage) is
|
||||
when IDLE =>
|
||||
if (dds2_start = '1') then
|
||||
dds2_stage <= START;
|
||||
else
|
||||
dds2_done <= '1';
|
||||
end if;
|
||||
when START =>
|
||||
if (ack_dds(1) = '1') then
|
||||
case (dds2.opcode) is
|
||||
when WAIT_FOR_ACKNOWLEDGEMENTS =>
|
||||
dds2_stage <= DONE;
|
||||
dds2_cnt <= 0;
|
||||
when others =>
|
||||
dds2_stage <= PUSH;
|
||||
dds2_cnt <= 0;
|
||||
end case;
|
||||
end if;
|
||||
when PUSH =>
|
||||
if (ready_in_dds(1) = '1') then
|
||||
dds2_cnt <= dds2_cnt + 1;
|
||||
if (dds2_cnt = dds2.cc.payload.length-1) then
|
||||
-- DEFAULT
|
||||
dds2_stage <= DONE;
|
||||
end if;
|
||||
end if;
|
||||
when DONE =>
|
||||
if (done_dds(1) = '1') then
|
||||
if (dds2.opcode = REGISTER_INSTANCE or dds2.opcode = LOOKUP_INSTANCE) then
|
||||
AffirmIfEqual(ih_id, to_unsigned(instance_handle_out_dds(1)), to_unsigned(dds2.cc.instance));
|
||||
else
|
||||
AffirmIfEqual(ret_id, return_code_dds(1), dds2.ret_code);
|
||||
end if;
|
||||
dds2_stage <= IDLE;
|
||||
end if;
|
||||
end case;
|
||||
end if;
|
||||
|
||||
-- DEFAULT
|
||||
start_dds(1) <= '0';
|
||||
opcode_dds(1) <= NOP;
|
||||
valid_in_dds(1) <= '0';
|
||||
last_word_in_dds(1) <= '0';
|
||||
data_in_dds(1) <= (others => '0');
|
||||
instance_handle_in_dds(1) <= HANDLE_NIL;
|
||||
source_ts_dds(1) <= TIME_INVALID;
|
||||
ready_out_dds(1) <= '0';
|
||||
|
||||
case (dds2_stage) is
|
||||
when START =>
|
||||
start_dds(1) <= '1';
|
||||
opcode_dds(1) <= dds2.opcode;
|
||||
instance_handle_in_dds(1) <= dds2.cc.instance;
|
||||
source_ts_dds(1) <= dds2.cc.src_timestamp;
|
||||
when PUSH =>
|
||||
valid_in_dds(1) <= '1';
|
||||
data_in_dds(1) <= dds2.cc.payload.data(dds2_cnt);
|
||||
last_word_in_dds(1) <= dds2.cc.payload.last(dds2_cnt);
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
rtps_prc : process(all)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
rtps_done <= '0';
|
||||
case (rtps_stage) is
|
||||
when IDLE =>
|
||||
if (rtps_start = '1') then
|
||||
rtps_stage <= START;
|
||||
else
|
||||
rtps_done <= '1';
|
||||
end if;
|
||||
when START =>
|
||||
if (ack_rtps(ind) = '1') then
|
||||
rtps_stage <= DONE;
|
||||
end if;
|
||||
when DONE =>
|
||||
if (done_rtps(ind) = '1') then
|
||||
-- DEFAULT
|
||||
rtps_stage <= IDLE;
|
||||
|
||||
AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps(ind)), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code));
|
||||
case (rtps.opcode) is
|
||||
when GET_CACHE_CHANGE =>
|
||||
if (rtps.ret_code = OK) then
|
||||
AffirmIfEqual(inst_id, to_unsigned(cc_instance_handle(ind)), to_unsigned(rtps.cc.instance));
|
||||
AffirmIfEqual(kind_id, CACHE_CHANGE_KIND_TYPE'pos(cc_kind(ind)), CACHE_CHANGE_KIND_TYPE'pos(rtps.cc.kind));
|
||||
AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr(ind)), to_unsigned(rtps.cc.seq_nr));
|
||||
AffirmIfEqual(ts_id, to_unsigned(cc_source_timestamp(ind)), to_unsigned(rtps.cc.src_timestamp));
|
||||
rtps_stage <= CHECK;
|
||||
rtps_cnt <= 0;
|
||||
end if;
|
||||
when GET_MIN_SN =>
|
||||
AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr(ind)), to_unsigned(rtps.cc.seq_nr));
|
||||
when GET_MAX_SN =>
|
||||
AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr(ind)), to_unsigned(rtps.cc.seq_nr));
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
when CHECK =>
|
||||
if (valid_out_rtps(ind) = '1') then
|
||||
AffirmIfEqual(data_id, last_word_out_rtps(ind) & data_out_rtps(ind), rtps.cc.payload.last(rtps_cnt) & rtps.cc.payload.data(rtps_cnt));
|
||||
rtps_cnt <= rtps_cnt + 1;
|
||||
if (rtps_cnt = rtps.cc.payload.length-1) then
|
||||
rtps_stage <= IDLE;
|
||||
end if;
|
||||
end if;
|
||||
end case;
|
||||
end if;
|
||||
|
||||
-- DEFAULT
|
||||
start_rtps <= (others => '0');
|
||||
opcode_rtps <= (others => NOP);
|
||||
seq_nr_rtps <= (others => SEQUENCENUMBER_UNKNOWN);
|
||||
get_data_rtps <= (others => '0');
|
||||
ready_out_rtps <= (others => '0');
|
||||
|
||||
case (rtps_stage) is
|
||||
when START =>
|
||||
start_rtps(ind) <= '1';
|
||||
opcode_rtps(ind) <= rtps.opcode;
|
||||
seq_nr_rtps(ind) <= rtps.cc.seq_nr;
|
||||
when DONE =>
|
||||
if (done_rtps(ind) = '1') then
|
||||
case (rtps.opcode) is
|
||||
when GET_CACHE_CHANGE =>
|
||||
get_data_rtps(ind) <= '1';
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
when CHECK =>
|
||||
ready_out_rtps(ind) <= '1';
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
watchdog : process
|
||||
begin
|
||||
wait for 1 ms;
|
||||
Alert("Test timeout", FAILURE);
|
||||
std.env.stop;
|
||||
end process;
|
||||
|
||||
end architecture;
|
||||
@ -1,500 +0,0 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library osvvm; -- Utility Library
|
||||
context osvvm.OsvvmContext;
|
||||
|
||||
use work.rtps_package.all;
|
||||
use work.user_config.all;
|
||||
use work.rtps_config_package.all;
|
||||
use work.rtps_test_package.all;
|
||||
|
||||
-- This testbench tests the DDS WAIT_FOR_ACKNOWLEDGEMENTS Operation of the DDS Writer.
|
||||
|
||||
entity L0_dds_writer_test2_aik is
|
||||
end entity;
|
||||
|
||||
architecture testbench of L0_dds_writer_test2_aik is
|
||||
|
||||
-- *CONSTANT DECLARATION*
|
||||
constant MAX_REMOTE_ENDPOINTS : natural := 3;
|
||||
|
||||
-- *TYPE DECLARATION*
|
||||
type DDS_STAGE_TYPE is (IDLE, START, PUSH, DONE);
|
||||
type RTPS_STAGE_TYPE is (IDLE, START, DONE, CHECK);
|
||||
|
||||
-- *SIGNAL DECLARATION*
|
||||
signal clk : std_logic := '0';
|
||||
signal reset : std_logic := '1';
|
||||
signal check_time : TIME_TYPE := TIME_ZERO;
|
||||
signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0';
|
||||
signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP;
|
||||
signal opcode_dds : DDS_WRITER_OPCODE_TYPE := NOP;
|
||||
signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR;
|
||||
signal seq_nr_rtps, cc_seq_nr : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN;
|
||||
signal ready_out_rtps, valid_out_rtps, last_word_out_rtps : std_logic := '0';
|
||||
signal ready_in_dds, ready_out_dds, valid_in_dds, valid_out_dds, last_word_in_dds, last_word_out_dds : std_logic := '0';
|
||||
signal data_out_rtps, data_in_dds, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
|
||||
signal get_data_rtps, liveliness_assertion, data_available : std_logic := '0';
|
||||
signal cc_source_timestamp, source_ts_dds : TIME_TYPE := TIME_INVALID;
|
||||
signal cc_kind : CACHE_CHANGE_KIND_TYPE := ALIVE;
|
||||
signal cc_instance_handle, instance_handle_in_dds, instance_handle_out_dds : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
|
||||
signal max_wait_dds : DURATION_TYPE := DURATION_INFINITE;
|
||||
signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0');
|
||||
signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0');
|
||||
|
||||
signal dds_start, dds_done, rtps_start, rtps_done : std_logic := '0';
|
||||
signal dds_cnt, rtps_cnt : natural := 0;
|
||||
signal dds_stage : DDS_STAGE_TYPE := IDLE;
|
||||
signal rtps_stage : RTPS_STAGE_TYPE := IDLE;
|
||||
shared variable dds : DDS_WRITER_TEST_TYPE := DEFAULT_DDS_WRITER_TEST;
|
||||
shared variable rtps : RTPS_WRITER_TEST_TYPE := DEFAULT_RTPS_WRITER_TEST;
|
||||
signal inst_id, kind_id, sn_id, ts_id, data_id, ret_id, ih_id : AlertLogIDType;
|
||||
|
||||
-- *FUNCTION DECLARATION*
|
||||
function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is
|
||||
variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
|
||||
begin
|
||||
for i in 0 to 3 loop
|
||||
ret(i) := not payload.data(i);
|
||||
end loop;
|
||||
|
||||
return ret;
|
||||
end function;
|
||||
|
||||
function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is
|
||||
variable ret : SEQUENCENUMBER_TYPE;
|
||||
begin
|
||||
ret(0) := (others => '0');
|
||||
ret(1) := unsigned(int(input, WORD_WIDTH));
|
||||
return ret;
|
||||
end function;
|
||||
|
||||
begin
|
||||
|
||||
-- Unit Under Test
|
||||
uut : entity work.dds_writer(arch)
|
||||
generic map(
|
||||
HISTORY_QOS => KEEP_ALL_HISTORY_QOS,
|
||||
DEADLINE_QOS => DURATION_INFINITE,
|
||||
LIFESPAN_QOS => DURATION_INFINITE,
|
||||
LEASE_DURATION => DURATION_INFINITE,
|
||||
WITH_KEY => TRUE,
|
||||
MAX_SAMPLES => std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)),
|
||||
MAX_INSTANCES => std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)),
|
||||
MAX_SAMPLES_PER_INSTANCE => std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)),
|
||||
PAYLOAD_FRAME_SIZE => 11
|
||||
)
|
||||
port map (
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
time => check_time,
|
||||
start_rtps => start_rtps,
|
||||
opcode_rtps => opcode_rtps,
|
||||
ack_rtps => ack_rtps,
|
||||
done_rtps => done_rtps,
|
||||
ret_rtps => ret_rtps,
|
||||
seq_nr_rtps => seq_nr_rtps,
|
||||
get_data_rtps => get_data_rtps,
|
||||
data_out_rtps => data_out_rtps,
|
||||
valid_out_rtps => valid_out_rtps,
|
||||
ready_out_rtps => ready_out_rtps,
|
||||
last_word_out_rtps => last_word_out_rtps,
|
||||
liveliness_assertion => liveliness_assertion,
|
||||
data_available => data_available,
|
||||
cc_instance_handle => cc_instance_handle,
|
||||
cc_kind => cc_kind,
|
||||
cc_source_timestamp => cc_source_timestamp,
|
||||
cc_seq_nr => cc_seq_nr,
|
||||
start_dds => start_dds,
|
||||
ack_dds => ack_dds,
|
||||
opcode_dds => opcode_dds,
|
||||
instance_handle_in_dds => instance_handle_in_dds,
|
||||
source_ts_dds => source_ts_dds,
|
||||
max_wait_dds => max_wait_dds,
|
||||
done_dds => done_dds,
|
||||
return_code_dds => return_code_dds,
|
||||
ready_in_dds => ready_in_dds,
|
||||
valid_in_dds => valid_in_dds,
|
||||
data_in_dds => data_in_dds,
|
||||
last_word_in_dds => last_word_in_dds,
|
||||
ready_out_dds => ready_out_dds,
|
||||
valid_out_dds => valid_out_dds,
|
||||
data_out_dds => data_out_dds,
|
||||
last_word_out_dds => last_word_out_dds,
|
||||
status => status
|
||||
);
|
||||
|
||||
stimulus_prc : process
|
||||
variable RV : RandomPType;
|
||||
variable kh1, kh2, kh3, kh4 : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
|
||||
variable cc1, cc2, cc3, cc4, cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE;
|
||||
|
||||
impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is
|
||||
variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
|
||||
begin
|
||||
assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE;
|
||||
|
||||
for i in 0 to len-1 loop
|
||||
if (i < 4) then
|
||||
-- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc
|
||||
ret.data(ret.length) := not key_hash(i);
|
||||
else
|
||||
ret.data(ret.length) := RV.RandSlv(WORD_WIDTH);
|
||||
end if;
|
||||
ret.length := ret.length + 1;
|
||||
end loop;
|
||||
ret.last(ret.length-1) := '1';
|
||||
|
||||
return ret;
|
||||
end function;
|
||||
|
||||
impure function gen_key_hash return KEY_HASH_TYPE is
|
||||
variable ret : KEY_HASH_TYPE := KEY_HASH_NIL;
|
||||
begin
|
||||
for i in 0 to KEY_HASH_TYPE'length-1 loop
|
||||
ret(i) := RV.RandSlv(WORD_WIDTH);
|
||||
end loop;
|
||||
return ret;
|
||||
end function;
|
||||
|
||||
procedure start_dds is
|
||||
begin
|
||||
dds_start <= '1';
|
||||
wait until rising_edge(clk);
|
||||
dds_start <= '0';
|
||||
wait until rising_edge(clk);
|
||||
end procedure;
|
||||
|
||||
procedure start_rtps is
|
||||
begin
|
||||
rtps_start <= '1';
|
||||
wait until rising_edge(clk);
|
||||
rtps_start <= '0';
|
||||
wait until rising_edge(clk);
|
||||
end procedure;
|
||||
|
||||
procedure wait_on_dds is
|
||||
begin
|
||||
if (dds_done /= '1') then
|
||||
wait until dds_done = '1';
|
||||
end if;
|
||||
end procedure;
|
||||
|
||||
procedure wait_on_rtps is
|
||||
begin
|
||||
if (rtps_done /= '1') then
|
||||
wait until rtps_done = '1';
|
||||
end if;
|
||||
end procedure;
|
||||
|
||||
procedure wait_on_completion is
|
||||
begin
|
||||
if (rtps_done /= '1' or dds_done /= '1') then
|
||||
wait until rtps_done = '1' and dds_done = '1';
|
||||
end if;
|
||||
end procedure;
|
||||
|
||||
begin
|
||||
|
||||
SetAlertLogName("L0_dds_writer_test2_aik - (KEEP ALL, Infinite Lifespan, Keyed) - Wait For Acknowledgements");
|
||||
SetAlertEnable(FAILURE, TRUE);
|
||||
SetAlertEnable(ERROR, TRUE);
|
||||
SetAlertEnable(WARNING, TRUE);
|
||||
SetLogEnable(DEBUG, FALSE);
|
||||
SetLogEnable(PASSED, FALSE);
|
||||
SetLogEnable(INFO, TRUE);
|
||||
RV.InitSeed(RV'instance_name);
|
||||
inst_id <= GetAlertLogID("Instance", ALERTLOG_BASE_ID);
|
||||
kind_id <= GetAlertLogID("Cache Change Kind", ALERTLOG_BASE_ID);
|
||||
sn_id <= GetAlertLogID("SequenceNumber", ALERTLOG_BASE_ID);
|
||||
ts_id <= GetAlertLogID("TimeStamp", ALERTLOG_BASE_ID);
|
||||
ih_id <= GetAlertLogID("Instance Handle", ALERTLOG_BASE_ID);
|
||||
data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID);
|
||||
ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID);
|
||||
|
||||
-- Key Hashes
|
||||
kh1 := gen_key_hash;
|
||||
kh2 := gen_key_hash;
|
||||
kh3 := gen_key_hash;
|
||||
kh4 := gen_key_hash;
|
||||
|
||||
|
||||
|
||||
Log("Initiating Test", INFO);
|
||||
Log("Current Time: 0s", INFO);
|
||||
check_time <= TIME_ZERO;
|
||||
reset <= '1';
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
reset <= '0';
|
||||
-- Stored CC: 0, 0, 0, 0
|
||||
|
||||
Log("DDS Operation WAIT_FOR_ACKNOWLEDGEMENTS [max_wait 0s] (OK)", INFO);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := WAIT_FOR_ACKNOWLEDGEMENTS;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
max_wait_dds <= gen_duration(0,0);
|
||||
start_dds;
|
||||
wait_on_dds;
|
||||
|
||||
cc := DEFAULT_CACHE_CHANGE;
|
||||
cc.serialized_key := FALSE;
|
||||
cc.kind := ALIVE;
|
||||
cc.instance := kh1;
|
||||
cc.payload := gen_payload(kh1,10);
|
||||
cc.seq_nr := gen_sn(1);
|
||||
cc.src_timestamp := gen_duration(1,0);
|
||||
|
||||
Log("DDS Operation WRITE [TS 1s, Instance 1, HANDLE_NIL, Aligned Payload] (ACCEPTED)", INFO);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := WRITE;
|
||||
dds.cc := cc;
|
||||
dds.cc.instance:= HANDLE_NIL;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
start_dds;
|
||||
wait_on_dds;
|
||||
cc1 := cc;
|
||||
-- Stored CC: I1S1, 0, 0, 0
|
||||
|
||||
cc := DEFAULT_CACHE_CHANGE;
|
||||
cc.serialized_key := FALSE;
|
||||
cc.kind := ALIVE;
|
||||
cc.instance := kh2;
|
||||
cc.payload := gen_payload(kh2,10);
|
||||
cc.seq_nr := gen_sn(2);
|
||||
cc.src_timestamp := gen_duration(2,0);
|
||||
|
||||
Log("DDS Operation WRITE [TS 2s, Instance 2, HANDLE_NIL, Aligned Payload] (ACCEPTED)", INFO);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := WRITE;
|
||||
dds.cc := cc;
|
||||
dds.cc.instance:= HANDLE_NIL;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
start_dds;
|
||||
wait_on_dds;
|
||||
cc2 := cc;
|
||||
-- Stored CC: I1S1, I2S2, 0, 0
|
||||
|
||||
Log("DDS Operation WAIT_FOR_ACKNOWLEDGEMENTS [max_wait 0s] (TIMEOUT)", INFO);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := WAIT_FOR_ACKNOWLEDGEMENTS;
|
||||
dds.ret_code := RETCODE_TIMEOUT;
|
||||
max_wait_dds <= gen_duration(0,0);
|
||||
start_dds;
|
||||
wait_on_dds;
|
||||
|
||||
Log("DDS Operation WAIT_FOR_ACKNOWLEDGEMENTS [max_wait 1s]", INFO);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := WAIT_FOR_ACKNOWLEDGEMENTS;
|
||||
dds.ret_code := RETCODE_TIMEOUT;
|
||||
max_wait_dds <= gen_duration(1,0);
|
||||
start_dds;
|
||||
|
||||
Log("RTPS Operation ACK_CACHE_CHANGE SN 1", INFO);
|
||||
rtps := DEFAULT_RTPS_WRITER_TEST;
|
||||
rtps.opcode := ACK_CACHE_CHANGE;
|
||||
rtps.cc := cc1;
|
||||
start_rtps;
|
||||
wait_on_rtps;
|
||||
|
||||
Log("Current Time: 1s", INFO);
|
||||
Log("WAIT_FOR_ACKNOWLEDGEMENTS Return (TIMEOUT)", INFO);
|
||||
check_time <= gen_duration(1,0);
|
||||
wait until rising_edge(clk);
|
||||
wait_on_dds;
|
||||
|
||||
Log("DDS Operation WAIT_FOR_ACKNOWLEDGEMENTS [max_wait 1s]", INFO);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := WAIT_FOR_ACKNOWLEDGEMENTS;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
max_wait_dds <= gen_duration(1,0);
|
||||
start_dds;
|
||||
|
||||
Log("RTPS Operation ACK_CACHE_CHANGE SN 2", INFO);
|
||||
Log("WAIT_FOR_ACKNOWLEDGEMENTS Return (OK)", INFO);
|
||||
rtps := DEFAULT_RTPS_WRITER_TEST;
|
||||
rtps.opcode := ACK_CACHE_CHANGE;
|
||||
rtps.cc := cc2;
|
||||
start_rtps;
|
||||
wait_on_rtps;
|
||||
wait_on_dds;
|
||||
|
||||
wait_on_completion;
|
||||
TranscriptOpen(RESULTS_FILE, APPEND_MODE);
|
||||
SetTranscriptMirror;
|
||||
ReportAlerts;
|
||||
TranscriptClose;
|
||||
std.env.stop;
|
||||
wait;
|
||||
end process;
|
||||
|
||||
clock_prc : process
|
||||
begin
|
||||
clk <= '0';
|
||||
wait for 25 ns;
|
||||
clk <= '1';
|
||||
wait for 25 ns;
|
||||
end process;
|
||||
|
||||
alert_prc : process(all)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
-- TODO
|
||||
end if;
|
||||
end process;
|
||||
|
||||
dds_prc : process(all)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
dds_done <= '0';
|
||||
case (dds_stage) is
|
||||
when IDLE =>
|
||||
if (dds_start = '1') then
|
||||
dds_stage <= START;
|
||||
else
|
||||
dds_done <= '1';
|
||||
end if;
|
||||
when START =>
|
||||
if (ack_dds = '1') then
|
||||
case (dds.opcode) is
|
||||
when WAIT_FOR_ACKNOWLEDGEMENTS =>
|
||||
dds_stage <= DONE;
|
||||
dds_cnt <= 0;
|
||||
when others =>
|
||||
dds_stage <= PUSH;
|
||||
dds_cnt <= 0;
|
||||
end case;
|
||||
end if;
|
||||
when PUSH =>
|
||||
if (ready_in_dds = '1') then
|
||||
dds_cnt <= dds_cnt + 1;
|
||||
if (dds_cnt = dds.cc.payload.length-1) then
|
||||
-- DEFAULT
|
||||
dds_stage <= DONE;
|
||||
end if;
|
||||
end if;
|
||||
when DONE =>
|
||||
if (done_dds = '1') then
|
||||
if (dds.opcode = REGISTER_INSTANCE or dds.opcode = LOOKUP_INSTANCE) then
|
||||
AffirmIfEqual(ih_id, to_unsigned(instance_handle_out_dds), to_unsigned(dds.cc.instance));
|
||||
else
|
||||
AffirmIfEqual(ret_id, return_code_dds, dds.ret_code);
|
||||
end if;
|
||||
dds_stage <= IDLE;
|
||||
end if;
|
||||
end case;
|
||||
end if;
|
||||
|
||||
-- DEFAULT
|
||||
start_dds <= '0';
|
||||
opcode_dds <= NOP;
|
||||
valid_in_dds <= '0';
|
||||
last_word_in_dds <= '0';
|
||||
data_in_dds <= (others => '0');
|
||||
instance_handle_in_dds <= HANDLE_NIL;
|
||||
source_ts_dds <= TIME_INVALID;
|
||||
ready_out_dds <= '0';
|
||||
|
||||
case (dds_stage) is
|
||||
when START =>
|
||||
start_dds <= '1';
|
||||
opcode_dds <= dds.opcode;
|
||||
instance_handle_in_dds <= dds.cc.instance;
|
||||
source_ts_dds <= dds.cc.src_timestamp;
|
||||
when PUSH =>
|
||||
valid_in_dds <= '1';
|
||||
data_in_dds <= dds.cc.payload.data(dds_cnt);
|
||||
last_word_in_dds <= dds.cc.payload.last(dds_cnt);
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
rtps_prc : process(all)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
rtps_done <= '0';
|
||||
case (rtps_stage) is
|
||||
when IDLE =>
|
||||
if (rtps_start = '1') then
|
||||
rtps_stage <= START;
|
||||
else
|
||||
rtps_done <= '1';
|
||||
end if;
|
||||
when START =>
|
||||
if (ack_rtps = '1') then
|
||||
rtps_stage <= DONE;
|
||||
end if;
|
||||
when DONE =>
|
||||
if (done_rtps = '1') then
|
||||
-- DEFAULT
|
||||
rtps_stage <= IDLE;
|
||||
|
||||
AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code));
|
||||
case (rtps.opcode) is
|
||||
when GET_CACHE_CHANGE =>
|
||||
if (rtps.ret_code = OK) then
|
||||
AffirmIfEqual(inst_id, to_unsigned(cc_instance_handle), to_unsigned(rtps.cc.instance));
|
||||
AffirmIfEqual(kind_id, CACHE_CHANGE_KIND_TYPE'pos(cc_kind), CACHE_CHANGE_KIND_TYPE'pos(rtps.cc.kind));
|
||||
AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr));
|
||||
AffirmIfEqual(ts_id, to_unsigned(cc_source_timestamp), to_unsigned(rtps.cc.src_timestamp));
|
||||
rtps_stage <= CHECK;
|
||||
rtps_cnt <= 0;
|
||||
end if;
|
||||
when GET_MIN_SN =>
|
||||
AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr));
|
||||
when GET_MAX_SN =>
|
||||
AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr));
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
when CHECK =>
|
||||
if (valid_out_rtps = '1') then
|
||||
AffirmIfEqual(data_id, last_word_out_rtps & data_out_rtps, rtps.cc.payload.last(rtps_cnt) & rtps.cc.payload.data(rtps_cnt));
|
||||
rtps_cnt <= rtps_cnt + 1;
|
||||
if (rtps_cnt = rtps.cc.payload.length-1) then
|
||||
rtps_stage <= IDLE;
|
||||
end if;
|
||||
end if;
|
||||
end case;
|
||||
end if;
|
||||
|
||||
-- DEFAULT
|
||||
start_rtps <= '0';
|
||||
opcode_rtps <= NOP;
|
||||
seq_nr_rtps <= SEQUENCENUMBER_UNKNOWN;
|
||||
get_data_rtps <= '0';
|
||||
ready_out_rtps <= '0';
|
||||
|
||||
case (rtps_stage) is
|
||||
when START =>
|
||||
start_rtps <= '1';
|
||||
opcode_rtps <= rtps.opcode;
|
||||
seq_nr_rtps <= rtps.cc.seq_nr;
|
||||
when DONE =>
|
||||
if (done_rtps = '1') then
|
||||
case (rtps.opcode) is
|
||||
when GET_CACHE_CHANGE =>
|
||||
get_data_rtps <= '1';
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
when CHECK =>
|
||||
ready_out_rtps <= '1';
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
watchdog : process
|
||||
begin
|
||||
wait for 1 ms;
|
||||
Alert("Test timeout", FAILURE);
|
||||
std.env.stop;
|
||||
end process;
|
||||
|
||||
end architecture;
|
||||
806
src/Tests/Level_0/L0_dds_writer_test3.vhd
Normal file
806
src/Tests/Level_0/L0_dds_writer_test3.vhd
Normal file
@ -0,0 +1,806 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library osvvm; -- Utility Library
|
||||
context osvvm.OsvvmContext;
|
||||
|
||||
use work.rtps_package.all;
|
||||
use work.user_config.all;
|
||||
use work.rtps_config_package.all;
|
||||
use work.rtps_test_package.all;
|
||||
|
||||
-- This testbench tests the Deadline Handling of the DDS Writer, and more specifically the GET_OFFERED_DEADLINE_MISSED_STATUS DDS Operation.
|
||||
|
||||
entity L0_dds_writer_test3 is
|
||||
end entity;
|
||||
|
||||
architecture testbench of L0_dds_writer_test3 is
|
||||
|
||||
-- *CONSTANT DECLARATION*
|
||||
constant MAX_REMOTE_ENDPOINTS : natural := 3;
|
||||
constant NUM_WRITERS : natural := 3;
|
||||
|
||||
impure function gen_test_config return CONFIG_ARRAY_TYPE is
|
||||
variable ret : CONFIG_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => DEFAULT_WRITER_CONFIG);
|
||||
begin
|
||||
-- aik
|
||||
ret(0).HISTORY_QOS := KEEP_ALL_HISTORY_QOS;
|
||||
ret(0).DEADLINE_QOS := gen_duration(1 sec);
|
||||
ret(0).LIFESPAN_QOS := DURATION_INFINITE;
|
||||
ret(0).LEASE_DURATION := DURATION_INFINITE;
|
||||
ret(0).WITH_KEY := TRUE;
|
||||
ret(0).MAX_SAMPLES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH));
|
||||
ret(0).MAX_INSTANCES := std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH));
|
||||
ret(0).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH));
|
||||
ret(0).MAX_PAYLOAD_SIZE := 40;
|
||||
-- ain
|
||||
ret(1).HISTORY_QOS := KEEP_ALL_HISTORY_QOS;
|
||||
ret(1).DEADLINE_QOS := gen_duration(1 sec);
|
||||
ret(1).LIFESPAN_QOS := DURATION_INFINITE;
|
||||
ret(1).LEASE_DURATION := DURATION_INFINITE;
|
||||
ret(1).WITH_KEY := FALSE;
|
||||
ret(1).MAX_SAMPLES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH));
|
||||
ret(1).MAX_INSTANCES := std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH));
|
||||
ret(1).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH));
|
||||
ret(1).MAX_PAYLOAD_SIZE := 40;
|
||||
-- aik
|
||||
ret(2).HISTORY_QOS := KEEP_ALL_HISTORY_QOS;
|
||||
ret(2).DEADLINE_QOS := gen_duration(2 sec);
|
||||
ret(2).LIFESPAN_QOS := DURATION_INFINITE;
|
||||
ret(2).LEASE_DURATION := DURATION_INFINITE;
|
||||
ret(2).WITH_KEY := TRUE;
|
||||
ret(2).MAX_SAMPLES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH));
|
||||
ret(2).MAX_INSTANCES := std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH));
|
||||
ret(2).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH));
|
||||
ret(2).MAX_PAYLOAD_SIZE := 40;
|
||||
return ret;
|
||||
end function;
|
||||
constant TEST_CONFIG : CONFIG_ARRAY_TYPE := gen_test_config;
|
||||
|
||||
-- *TYPE DECLARATION*
|
||||
type DDS_STAGE_TYPE is (IDLE, START, PUSH, DONE, CHECK_DEADLINE);
|
||||
type RTPS_STAGE_TYPE is (IDLE, START, DONE, CHECK);
|
||||
|
||||
-- *SIGNAL DECLARATION*
|
||||
signal clk : std_logic := '0';
|
||||
signal reset : std_logic := '1';
|
||||
signal check_time : TIME_TYPE := TIME_ZERO;
|
||||
signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds, w_map : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0');
|
||||
signal opcode_rtps : HISTORY_CACHE_OPCODE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => NOP);
|
||||
signal opcode_dds : DDS_WRITER_OPCODE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => NOP);
|
||||
signal ret_rtps : HISTORY_CACHE_RESPONSE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => ERROR);
|
||||
signal seq_nr_rtps, cc_seq_nr : SEQUENCENUMBER_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => SEQUENCENUMBER_UNKNOWN);
|
||||
signal ready_out_rtps, valid_out_rtps, last_word_out_rtps : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0');
|
||||
signal ready_in_dds, ready_out_dds, valid_in_dds, valid_out_dds, last_word_in_dds, last_word_out_dds : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0');
|
||||
signal data_out_rtps, data_in_dds, data_out_dds : WORD_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => (others => '0'));
|
||||
signal get_data_rtps, liveliness_assertion, data_available : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0');
|
||||
signal cc_source_timestamp, source_ts_dds : TIME_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => TIME_INVALID);
|
||||
signal cc_kind : CACHE_CHANGE_KIND_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => ALIVE);
|
||||
signal cc_instance_handle, instance_handle_in_dds, instance_handle_out_dds : INSTANCE_HANDLE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => HANDLE_NIL);
|
||||
signal max_wait_dds : DURATION_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => DURATION_INFINITE);
|
||||
signal return_code_dds : RETURN_CODE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => (others => '0'));
|
||||
signal status : STATUS_KIND_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => (others => '0'));
|
||||
|
||||
signal ind : natural := 0;
|
||||
signal dds_start, dds_done, rtps_start, rtps_done : std_logic := '0';
|
||||
signal dds_cnt, rtps_cnt : natural := 0;
|
||||
signal dds_stage : DDS_STAGE_TYPE := IDLE;
|
||||
signal rtps_stage : RTPS_STAGE_TYPE := IDLE;
|
||||
shared variable dds : DDS_WRITER_TEST_TYPE := DEFAULT_DDS_WRITER_TEST;
|
||||
shared variable rtps : RTPS_WRITER_TEST_TYPE := DEFAULT_RTPS_WRITER_TEST;
|
||||
signal inst_id, kind_id, sn_id, ts_id, data_id, ret_id, status_id, ih_id : AlertLogIDType;
|
||||
|
||||
-- *FUNCTION DECLARATION*
|
||||
function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is
|
||||
variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
|
||||
begin
|
||||
for i in 0 to 3 loop
|
||||
ret(i) := not payload.data(i);
|
||||
end loop;
|
||||
|
||||
return ret;
|
||||
end function;
|
||||
|
||||
function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is
|
||||
variable ret : SEQUENCENUMBER_TYPE;
|
||||
begin
|
||||
ret(0) := (others => '0');
|
||||
ret(1) := unsigned(int(input, WORD_WIDTH));
|
||||
return ret;
|
||||
end function;
|
||||
|
||||
procedure wait_on_sig(signal sig : std_logic) is
|
||||
begin
|
||||
if (sig /= '1') then
|
||||
wait on sig until sig = '1';
|
||||
end if;
|
||||
end procedure;
|
||||
|
||||
begin
|
||||
|
||||
-- Unit Under Test
|
||||
uut : entity work.dds_writer(arch)
|
||||
generic map(
|
||||
NUM_WRITERS => NUM_WRITERS,
|
||||
CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(TEST_CONFIG)
|
||||
)
|
||||
port map (
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
time => check_time,
|
||||
start_rtps => start_rtps,
|
||||
opcode_rtps => opcode_rtps,
|
||||
ack_rtps => ack_rtps,
|
||||
done_rtps => done_rtps,
|
||||
ret_rtps => ret_rtps,
|
||||
seq_nr_rtps => seq_nr_rtps,
|
||||
get_data_rtps => get_data_rtps,
|
||||
data_out_rtps => data_out_rtps,
|
||||
valid_out_rtps => valid_out_rtps,
|
||||
ready_out_rtps => ready_out_rtps,
|
||||
last_word_out_rtps => last_word_out_rtps,
|
||||
liveliness_assertion => liveliness_assertion,
|
||||
data_available => data_available,
|
||||
cc_instance_handle => cc_instance_handle,
|
||||
cc_kind => cc_kind,
|
||||
cc_source_timestamp => cc_source_timestamp,
|
||||
cc_seq_nr => cc_seq_nr,
|
||||
start_dds => start_dds,
|
||||
ack_dds => ack_dds,
|
||||
opcode_dds => opcode_dds,
|
||||
instance_handle_in_dds => instance_handle_in_dds,
|
||||
source_ts_dds => source_ts_dds,
|
||||
max_wait_dds => max_wait_dds,
|
||||
done_dds => done_dds,
|
||||
return_code_dds => return_code_dds,
|
||||
instance_handle_out_dds => instance_handle_out_dds,
|
||||
ready_in_dds => ready_in_dds,
|
||||
valid_in_dds => valid_in_dds,
|
||||
data_in_dds => data_in_dds,
|
||||
last_word_in_dds => last_word_in_dds,
|
||||
ready_out_dds => ready_out_dds,
|
||||
valid_out_dds => valid_out_dds,
|
||||
data_out_dds => data_out_dds,
|
||||
last_word_out_dds => last_word_out_dds,
|
||||
status => status
|
||||
);
|
||||
|
||||
stimulus_prc : process
|
||||
variable RV : RandomPType;
|
||||
variable kh1, kh2, kh3, kh4 : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
|
||||
variable cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE;
|
||||
|
||||
alias idle_sig is <<signal uut.idle_sig : std_logic>>;
|
||||
|
||||
impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is
|
||||
variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
|
||||
begin
|
||||
assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE;
|
||||
|
||||
for i in 0 to len-1 loop
|
||||
if (i < 4) then
|
||||
-- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc
|
||||
ret.data(ret.length) := not key_hash(i);
|
||||
else
|
||||
ret.data(ret.length) := RV.RandSlv(WORD_WIDTH);
|
||||
end if;
|
||||
ret.length := ret.length + 1;
|
||||
end loop;
|
||||
ret.last(ret.length-1) := '1';
|
||||
|
||||
return ret;
|
||||
end function;
|
||||
|
||||
impure function gen_key_hash return KEY_HASH_TYPE is
|
||||
variable ret : KEY_HASH_TYPE := KEY_HASH_NIL;
|
||||
begin
|
||||
for i in 0 to KEY_HASH_TYPE'length-1 loop
|
||||
ret(i) := RV.RandSlv(WORD_WIDTH);
|
||||
end loop;
|
||||
return ret;
|
||||
end function;
|
||||
|
||||
procedure start_dds is
|
||||
begin
|
||||
dds_start <= '1';
|
||||
wait until rising_edge(clk);
|
||||
dds_start <= '0';
|
||||
wait until rising_edge(clk);
|
||||
end procedure;
|
||||
|
||||
procedure start_rtps is
|
||||
begin
|
||||
rtps_start <= '1';
|
||||
wait until rising_edge(clk);
|
||||
rtps_start <= '0';
|
||||
wait until rising_edge(clk);
|
||||
end procedure;
|
||||
|
||||
procedure wait_on_completion is
|
||||
begin
|
||||
if (rtps_done /= '1' or dds_done /= '1') then
|
||||
wait until rtps_done = '1' and dds_done = '1';
|
||||
end if;
|
||||
end procedure;
|
||||
|
||||
-- NOTE: This procedure waits until the idle_sig is high for at least
|
||||
-- two consecutive clock cycles.
|
||||
procedure wait_on_idle is
|
||||
variable first : boolean := TRUE;
|
||||
begin
|
||||
loop
|
||||
if (idle_sig /= '1') then
|
||||
wait until idle_sig = '1';
|
||||
elsif (not first) then
|
||||
exit;
|
||||
end if;
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
first := FALSE;
|
||||
end loop;
|
||||
end procedure;
|
||||
|
||||
begin
|
||||
|
||||
SetAlertLogName("L0_dds_writer_test3 - Deadline Handling");
|
||||
SetAlertEnable(FAILURE, TRUE);
|
||||
SetAlertEnable(ERROR, TRUE);
|
||||
SetAlertEnable(WARNING, TRUE);
|
||||
SetLogEnable(DEBUG, FALSE);
|
||||
SetLogEnable(PASSED, FALSE);
|
||||
SetLogEnable(INFO, TRUE);
|
||||
RV.InitSeed(RV'instance_name);
|
||||
inst_id <= GetAlertLogID("Instance", ALERTLOG_BASE_ID);
|
||||
kind_id <= GetAlertLogID("Cache Change Kind", ALERTLOG_BASE_ID);
|
||||
sn_id <= GetAlertLogID("SequenceNumber", ALERTLOG_BASE_ID);
|
||||
ts_id <= GetAlertLogID("TimeStamp", ALERTLOG_BASE_ID);
|
||||
ih_id <= GetAlertLogID("Instance Handle", ALERTLOG_BASE_ID);
|
||||
data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID);
|
||||
ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID);
|
||||
status_id <= GetAlertLogID("Communication Status", ALERTLOG_BASE_ID);
|
||||
|
||||
-- Key Hashes
|
||||
kh1 := gen_key_hash;
|
||||
kh2 := gen_key_hash;
|
||||
kh3 := gen_key_hash;
|
||||
kh4 := gen_key_hash;
|
||||
|
||||
|
||||
|
||||
Log("Initiating Test", INFO);
|
||||
Log("Current Time: 0s", INFO);
|
||||
check_time <= TIME_ZERO;
|
||||
reset <= '1';
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
reset <= '0';
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
||||
AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
||||
AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
||||
|
||||
Log("Current Time: 1s", INFO);
|
||||
check_time <= gen_duration(1 sec);
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
||||
AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
||||
AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
||||
|
||||
cc := DEFAULT_CACHE_CHANGE;
|
||||
cc.serialized_key := FALSE;
|
||||
cc.kind := ALIVE;
|
||||
cc.instance := kh1;
|
||||
cc.payload := gen_payload(kh1,10);
|
||||
|
||||
Log("W0,W1,W2: DDS Operation WRITE [Instance 1, HANDLE_NIL, Aligned Payload]", INFO);
|
||||
Log("W0,W1,W2: ACCEPTED", DEBUG);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := WRITE;
|
||||
dds.cc := cc;
|
||||
dds.cc.instance:= HANDLE_NIL;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
-- WRITER 0
|
||||
ind <= 0;
|
||||
start_dds;
|
||||
wait_on_sig(dds_done);
|
||||
-- WRITER 1
|
||||
ind <= 1;
|
||||
start_dds;
|
||||
wait_on_sig(dds_done);
|
||||
-- WRITER 2
|
||||
ind <= 2;
|
||||
start_dds;
|
||||
wait_on_sig(dds_done);
|
||||
wait_on_idle;
|
||||
|
||||
cc := DEFAULT_CACHE_CHANGE;
|
||||
cc.serialized_key := FALSE;
|
||||
cc.kind := ALIVE;
|
||||
cc.instance := kh2;
|
||||
cc.payload := gen_payload(kh2,10);
|
||||
|
||||
Log("W0,W2: DDS Operation WRITE [Instance 2, HANDLE_NIL, Aligned Payload]", INFO);
|
||||
Log("W0,W2: ACCEPTED", DEBUG);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := WRITE;
|
||||
dds.cc := cc;
|
||||
dds.cc.instance:= HANDLE_NIL;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
-- WRITER 0
|
||||
ind <= 0;
|
||||
start_dds;
|
||||
wait_on_sig(dds_done);
|
||||
-- WRITER 2
|
||||
ind <= 2;
|
||||
start_dds;
|
||||
wait_on_sig(dds_done);
|
||||
wait_on_idle;
|
||||
|
||||
Log("Current Time: 2s", INFO);
|
||||
check_time <= gen_duration(2 sec);
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
||||
AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
||||
AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
||||
|
||||
cc := DEFAULT_CACHE_CHANGE;
|
||||
cc.serialized_key := FALSE;
|
||||
cc.kind := ALIVE;
|
||||
cc.instance := kh1;
|
||||
cc.payload := gen_payload(kh1,10);
|
||||
|
||||
Log("W0,W2: DDS Operation WRITE [Instance 1, Aligned Payload]", INFO);
|
||||
Log("W0,W2: ACCEPTED", DEBUG);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := WRITE;
|
||||
dds.cc := cc;
|
||||
dds.cc.instance:= HANDLE_NIL;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
-- WRITER 0
|
||||
ind <= 0;
|
||||
start_dds;
|
||||
wait_on_sig(dds_done);
|
||||
-- WRITER 2
|
||||
ind <= 2;
|
||||
start_dds;
|
||||
wait_on_sig(dds_done);
|
||||
wait_on_idle;
|
||||
|
||||
Log("Current Time: 3s", INFO);
|
||||
check_time <= gen_duration(3 sec);
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
|
||||
AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
|
||||
AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
||||
|
||||
Log("W0: DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS", INFO);
|
||||
Log("W0: Expected [count 1, change 1, Instance 2]", DEBUG);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := GET_OFFERED_DEADLINE_MISSED_STATUS;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
dds.count := 1;
|
||||
dds.change := 1;
|
||||
dds.inst := kh2;
|
||||
-- WRITER 0
|
||||
ind <= 0;
|
||||
start_dds;
|
||||
wait_on_sig(dds_done);
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
||||
AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
|
||||
AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
||||
|
||||
Log("W1: DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS", INFO);
|
||||
Log("W1: Expected [count 1, change 1]", DEBUG);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := GET_OFFERED_DEADLINE_MISSED_STATUS;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
dds.count := 1;
|
||||
dds.change := 1;
|
||||
dds.inst := HANDLE_NIL;
|
||||
-- WRITER 1
|
||||
ind <= 1;
|
||||
start_dds;
|
||||
wait_on_sig(dds_done);
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
||||
AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
||||
AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
||||
|
||||
Log("W2: DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS", INFO);
|
||||
Log("W2: Expected [count 0, change 0, HANDLE_NIL]", DEBUG);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := GET_OFFERED_DEADLINE_MISSED_STATUS;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
dds.count := 0;
|
||||
dds.change := 0;
|
||||
dds.inst := HANDLE_NIL;
|
||||
-- WRITER 2
|
||||
ind <= 2;
|
||||
start_dds;
|
||||
wait_on_sig(dds_done);
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
||||
AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
||||
AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
||||
|
||||
cc := DEFAULT_CACHE_CHANGE;
|
||||
cc.serialized_key := FALSE;
|
||||
cc.kind := ALIVE;
|
||||
cc.instance := kh3;
|
||||
cc.payload := gen_payload(kh3,10);
|
||||
|
||||
Log("W0,W2: DDS Operation WRITE [Instance 3, Aligned Payload]", INFO);
|
||||
Log("W0,W2: ACCEPTED", DEBUG);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := WRITE;
|
||||
dds.cc := cc;
|
||||
dds.cc.instance:= HANDLE_NIL;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
-- WRITER 0
|
||||
ind <= 0;
|
||||
start_dds;
|
||||
wait_on_sig(dds_done);
|
||||
-- WRITER 2
|
||||
ind <= 2;
|
||||
start_dds;
|
||||
wait_on_sig(dds_done);
|
||||
wait_on_idle;
|
||||
|
||||
Log("Current Time: 4s", INFO);
|
||||
check_time <= gen_duration(4 sec);
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
|
||||
AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
|
||||
AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
|
||||
|
||||
Log("W0: DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS", INFO);
|
||||
Log("W0: Expected [count 3, change 2, Instance 1]", DEBUG);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := GET_OFFERED_DEADLINE_MISSED_STATUS;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
dds.count := 3;
|
||||
dds.change := 2;
|
||||
dds.inst := kh1;
|
||||
-- WRITER 0
|
||||
ind <= 0;
|
||||
start_dds;
|
||||
wait_on_sig(dds_done);
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
||||
AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
|
||||
AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
|
||||
|
||||
Log("W2: DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS", INFO);
|
||||
Log("W2: Expected [count 1, change 1, Instance 2]", DEBUG);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := GET_OFFERED_DEADLINE_MISSED_STATUS;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
dds.count := 1;
|
||||
dds.change := 1;
|
||||
dds.inst := kh2;
|
||||
-- WRITER 2
|
||||
ind <= 2;
|
||||
start_dds;
|
||||
wait_on_sig(dds_done);
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
||||
AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
|
||||
AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
||||
|
||||
Log("Current Time: 5s", INFO);
|
||||
check_time <= gen_duration(5 sec);
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
|
||||
AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
|
||||
AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
||||
|
||||
cc := DEFAULT_CACHE_CHANGE;
|
||||
cc.serialized_key := FALSE;
|
||||
cc.kind := ALIVE;
|
||||
cc.instance := kh1;
|
||||
cc.payload := gen_payload(kh1,10);
|
||||
|
||||
Log("W1: DDS Operation WRITE [Instance 1, Aligned Payload]", INFO);
|
||||
Log("W1: ACCEPTED", DEBUG);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := WRITE;
|
||||
dds.cc := cc;
|
||||
dds.cc.instance:= HANDLE_NIL;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
-- WRITER 1
|
||||
ind <= 1;
|
||||
start_dds;
|
||||
wait_on_sig(dds_done);
|
||||
wait_on_idle;
|
||||
|
||||
Log("Current Time: 6s", INFO);
|
||||
check_time <= gen_duration(6 sec);
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
|
||||
AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
|
||||
AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
|
||||
|
||||
Log("W0: DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS", INFO);
|
||||
Log("W0: Expected [count 9, change 6, Instance 1]", DEBUG);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := GET_OFFERED_DEADLINE_MISSED_STATUS;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
dds.count := 9;
|
||||
dds.change := 6;
|
||||
dds.inst := kh1;
|
||||
-- WRITER 0
|
||||
ind <= 0;
|
||||
start_dds;
|
||||
wait_on_sig(dds_done);
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
||||
AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
|
||||
AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
|
||||
|
||||
Log("W1: DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS", INFO);
|
||||
Log("W1: Expected [count 3, change 2]", DEBUG);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := GET_OFFERED_DEADLINE_MISSED_STATUS;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
dds.count := 3;
|
||||
dds.change := 2;
|
||||
dds.inst := HANDLE_NIL;
|
||||
-- WRITER 1
|
||||
ind <= 1;
|
||||
start_dds;
|
||||
wait_on_sig(dds_done);
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
||||
AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
||||
AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
|
||||
|
||||
Log("W2: DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS", INFO);
|
||||
Log("W2: Expected [count 4, change 3, Instance 1]", DEBUG);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := GET_OFFERED_DEADLINE_MISSED_STATUS;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
dds.count := 4;
|
||||
dds.change := 3;
|
||||
dds.inst := kh1;
|
||||
-- WRITER 2
|
||||
ind <= 2;
|
||||
start_dds;
|
||||
wait_on_sig(dds_done);
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
||||
AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
||||
AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
||||
|
||||
wait_on_completion;
|
||||
TranscriptOpen(RESULTS_FILE, APPEND_MODE);
|
||||
SetTranscriptMirror;
|
||||
ReportAlerts;
|
||||
TranscriptClose;
|
||||
std.env.stop;
|
||||
wait;
|
||||
end process;
|
||||
|
||||
clock_prc : process
|
||||
begin
|
||||
clk <= '0';
|
||||
wait for 25 ns;
|
||||
clk <= '1';
|
||||
wait for 25 ns;
|
||||
end process;
|
||||
|
||||
dds_prc : process(all)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
dds_done <= '0';
|
||||
case (dds_stage) is
|
||||
when IDLE =>
|
||||
if (dds_start = '1') then
|
||||
dds_stage <= START;
|
||||
else
|
||||
dds_done <= '1';
|
||||
end if;
|
||||
when START =>
|
||||
if (ack_dds(ind) = '1') then
|
||||
case (dds.opcode) is
|
||||
when GET_OFFERED_DEADLINE_MISSED_STATUS =>
|
||||
dds_stage <= DONE;
|
||||
dds_cnt <= 0;
|
||||
when others =>
|
||||
dds_stage <= PUSH;
|
||||
dds_cnt <= 0;
|
||||
end case;
|
||||
end if;
|
||||
when PUSH =>
|
||||
if (ready_in_dds(ind) = '1') then
|
||||
dds_cnt <= dds_cnt + 1;
|
||||
if (dds_cnt = dds.cc.payload.length-1) then
|
||||
-- DEFAULT
|
||||
dds_stage <= DONE;
|
||||
end if;
|
||||
end if;
|
||||
when DONE =>
|
||||
if (done_dds(ind) = '1') then
|
||||
if (dds.opcode = REGISTER_INSTANCE or dds.opcode = LOOKUP_INSTANCE) then
|
||||
AffirmIfEqual(ih_id, to_unsigned(instance_handle_out_dds(ind)), to_unsigned(dds.cc.instance));
|
||||
else
|
||||
AffirmIfEqual(ret_id, return_code_dds(ind), dds.ret_code);
|
||||
case (dds.opcode) is
|
||||
when GET_OFFERED_DEADLINE_MISSED_STATUS =>
|
||||
if (dds.ret_code = RETCODE_OK) then
|
||||
dds_stage <= CHECK_DEADLINE;
|
||||
dds_cnt <= 0;
|
||||
else
|
||||
dds_stage <= IDLE;
|
||||
end if;
|
||||
when others =>
|
||||
dds_stage <= IDLE;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
when CHECK_DEADLINE =>
|
||||
if (valid_out_dds(ind) = '1') then
|
||||
dds_cnt <= dds_cnt + 1;
|
||||
case (dds_cnt) is
|
||||
when 0 =>
|
||||
AffirmIfEqual(data_id, data_out_dds(ind), std_logic_vector(to_unsigned(dds.count,CDR_LONG_WIDTH)));
|
||||
when 1 =>
|
||||
AffirmIfEqual(data_id, data_out_dds(ind), std_logic_vector(to_unsigned(dds.change,CDR_LONG_WIDTH)));
|
||||
when 2 =>
|
||||
AffirmIfEqual(data_id, data_out_dds(ind), std_logic_vector(dds.inst(0)));
|
||||
when 3 =>
|
||||
AffirmIfEqual(data_id, data_out_dds(ind), std_logic_vector(dds.inst(1)));
|
||||
when 4 =>
|
||||
AffirmIfEqual(data_id, data_out_dds(ind), std_logic_vector(dds.inst(2)));
|
||||
when 5 =>
|
||||
AffirmIfEqual(data_id, data_out_dds(ind), std_logic_vector(dds.inst(3)));
|
||||
AlertIf(data_id, last_word_out_dds(ind) /= '1', "Last Word Signal not pulled High", ERROR);
|
||||
dds_stage <= IDLE;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
end case;
|
||||
end if;
|
||||
|
||||
-- DEFAULT
|
||||
start_dds <= (others => '0');
|
||||
opcode_dds <= (others => NOP);
|
||||
valid_in_dds <= (others => '0');
|
||||
last_word_in_dds <= (others => '0');
|
||||
data_in_dds <= (others => (others => '0'));
|
||||
instance_handle_in_dds <= (others => HANDLE_NIL);
|
||||
source_ts_dds <= (others => TIME_INVALID);
|
||||
ready_out_dds <= (others => '0');
|
||||
|
||||
case (dds_stage) is
|
||||
when START =>
|
||||
start_dds(ind) <= '1';
|
||||
opcode_dds(ind) <= dds.opcode;
|
||||
instance_handle_in_dds(ind) <= dds.cc.instance;
|
||||
source_ts_dds(ind) <= dds.cc.src_timestamp;
|
||||
when PUSH =>
|
||||
valid_in_dds(ind) <= '1';
|
||||
data_in_dds(ind) <= dds.cc.payload.data(dds_cnt);
|
||||
last_word_in_dds(ind) <= dds.cc.payload.last(dds_cnt);
|
||||
when CHECK_DEADLINE =>
|
||||
ready_out_dds(ind) <= '1';
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
rtps_prc : process(all)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
rtps_done <= '0';
|
||||
case (rtps_stage) is
|
||||
when IDLE =>
|
||||
if (rtps_start = '1') then
|
||||
rtps_stage <= START;
|
||||
else
|
||||
rtps_done <= '1';
|
||||
end if;
|
||||
when START =>
|
||||
if (ack_rtps(ind) = '1') then
|
||||
rtps_stage <= DONE;
|
||||
end if;
|
||||
when DONE =>
|
||||
if (done_rtps(ind) = '1') then
|
||||
-- DEFAULT
|
||||
rtps_stage <= IDLE;
|
||||
|
||||
AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps(ind)), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code));
|
||||
case (rtps.opcode) is
|
||||
when GET_CACHE_CHANGE =>
|
||||
if (rtps.ret_code = OK) then
|
||||
AffirmIfEqual(inst_id, to_unsigned(cc_instance_handle(ind)), to_unsigned(rtps.cc.instance));
|
||||
AffirmIfEqual(kind_id, CACHE_CHANGE_KIND_TYPE'pos(cc_kind(ind)), CACHE_CHANGE_KIND_TYPE'pos(rtps.cc.kind));
|
||||
AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr(ind)), to_unsigned(rtps.cc.seq_nr));
|
||||
AffirmIfEqual(ts_id, to_unsigned(cc_source_timestamp(ind)), to_unsigned(rtps.cc.src_timestamp));
|
||||
rtps_stage <= CHECK;
|
||||
rtps_cnt <= 0;
|
||||
end if;
|
||||
when GET_MIN_SN =>
|
||||
AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr(ind)), to_unsigned(rtps.cc.seq_nr));
|
||||
when GET_MAX_SN =>
|
||||
AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr(ind)), to_unsigned(rtps.cc.seq_nr));
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
when CHECK =>
|
||||
if (valid_out_rtps(ind) = '1') then
|
||||
AffirmIfEqual(data_id, last_word_out_rtps(ind) & data_out_rtps(ind), rtps.cc.payload.last(rtps_cnt) & rtps.cc.payload.data(rtps_cnt));
|
||||
rtps_cnt <= rtps_cnt + 1;
|
||||
if (rtps_cnt = rtps.cc.payload.length-1) then
|
||||
rtps_stage <= IDLE;
|
||||
end if;
|
||||
end if;
|
||||
end case;
|
||||
end if;
|
||||
|
||||
-- DEFAULT
|
||||
start_rtps <= (others => '0');
|
||||
opcode_rtps <= (others => NOP);
|
||||
seq_nr_rtps <= (others => SEQUENCENUMBER_UNKNOWN);
|
||||
get_data_rtps <= (others => '0');
|
||||
ready_out_rtps <= (others => '0');
|
||||
|
||||
case (rtps_stage) is
|
||||
when START =>
|
||||
start_rtps(ind) <= '1';
|
||||
opcode_rtps(ind) <= rtps.opcode;
|
||||
seq_nr_rtps(ind) <= rtps.cc.seq_nr;
|
||||
when DONE =>
|
||||
if (done_rtps(ind) = '1') then
|
||||
case (rtps.opcode) is
|
||||
when GET_CACHE_CHANGE =>
|
||||
get_data_rtps(ind) <= '1';
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
when CHECK =>
|
||||
ready_out_rtps(ind) <= '1';
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
watchdog : process
|
||||
begin
|
||||
wait for 1 ms;
|
||||
Alert("Test timeout", FAILURE);
|
||||
std.env.stop;
|
||||
end process;
|
||||
|
||||
end architecture;
|
||||
@ -1,628 +0,0 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library osvvm; -- Utility Library
|
||||
context osvvm.OsvvmContext;
|
||||
|
||||
use work.rtps_package.all;
|
||||
use work.user_config.all;
|
||||
use work.rtps_config_package.all;
|
||||
use work.rtps_test_package.all;
|
||||
|
||||
-- This testbench tests the Deadline Handling of the DDS Writer, and more specifically the GET_OFFERED_DEADLINE_MISSED_STATUS DDS Operation.
|
||||
|
||||
entity L0_dds_writer_test3_aik is
|
||||
end entity;
|
||||
|
||||
architecture testbench of L0_dds_writer_test3_aik is
|
||||
|
||||
-- *CONSTANT DECLARATION*
|
||||
constant MAX_REMOTE_ENDPOINTS : natural := 3;
|
||||
|
||||
-- *TYPE DECLARATION*
|
||||
type DDS_STAGE_TYPE is (IDLE, START, PUSH, DONE, CHECK_DEADLINE);
|
||||
type RTPS_STAGE_TYPE is (IDLE, START, DONE, CHECK);
|
||||
|
||||
-- *SIGNAL DECLARATION*
|
||||
signal clk : std_logic := '0';
|
||||
signal reset : std_logic := '1';
|
||||
signal check_time : TIME_TYPE := TIME_ZERO;
|
||||
signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0';
|
||||
signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP;
|
||||
signal opcode_dds : DDS_WRITER_OPCODE_TYPE := NOP;
|
||||
signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR;
|
||||
signal seq_nr_rtps, cc_seq_nr : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN;
|
||||
signal ready_out_rtps, valid_out_rtps, last_word_out_rtps : std_logic := '0';
|
||||
signal ready_in_dds, ready_out_dds, valid_in_dds, valid_out_dds, last_word_in_dds, last_word_out_dds : std_logic := '0';
|
||||
signal data_out_rtps, data_in_dds, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
|
||||
signal get_data_rtps, liveliness_assertion, data_available : std_logic := '0';
|
||||
signal cc_source_timestamp, source_ts_dds : TIME_TYPE := TIME_INVALID;
|
||||
signal cc_kind : CACHE_CHANGE_KIND_TYPE := ALIVE;
|
||||
signal cc_instance_handle, instance_handle_in_dds, instance_handle_out_dds : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
|
||||
signal max_wait_dds : DURATION_TYPE := DURATION_INFINITE;
|
||||
signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0');
|
||||
signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0');
|
||||
|
||||
signal dds_start, dds_done, rtps_start, rtps_done : std_logic := '0';
|
||||
signal dds_cnt, rtps_cnt : natural := 0;
|
||||
signal dds_stage : DDS_STAGE_TYPE := IDLE;
|
||||
signal rtps_stage : RTPS_STAGE_TYPE := IDLE;
|
||||
shared variable dds : DDS_WRITER_TEST_TYPE := DEFAULT_DDS_WRITER_TEST;
|
||||
shared variable rtps : RTPS_WRITER_TEST_TYPE := DEFAULT_RTPS_WRITER_TEST;
|
||||
signal inst_id, kind_id, sn_id, ts_id, data_id, ret_id, status_id, ih_id : AlertLogIDType;
|
||||
|
||||
-- *FUNCTION DECLARATION*
|
||||
function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is
|
||||
variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
|
||||
begin
|
||||
for i in 0 to 3 loop
|
||||
ret(i) := not payload.data(i);
|
||||
end loop;
|
||||
|
||||
return ret;
|
||||
end function;
|
||||
|
||||
function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is
|
||||
variable ret : SEQUENCENUMBER_TYPE;
|
||||
begin
|
||||
ret(0) := (others => '0');
|
||||
ret(1) := unsigned(int(input, WORD_WIDTH));
|
||||
return ret;
|
||||
end function;
|
||||
|
||||
begin
|
||||
|
||||
-- Unit Under Test
|
||||
uut : entity work.dds_writer(arch)
|
||||
generic map(
|
||||
HISTORY_QOS => KEEP_ALL_HISTORY_QOS,
|
||||
DEADLINE_QOS => gen_duration(1,0),
|
||||
LIFESPAN_QOS => DURATION_INFINITE,
|
||||
LEASE_DURATION => DURATION_INFINITE,
|
||||
WITH_KEY => TRUE,
|
||||
MAX_SAMPLES => std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)),
|
||||
MAX_INSTANCES => std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)),
|
||||
MAX_SAMPLES_PER_INSTANCE => std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)),
|
||||
PAYLOAD_FRAME_SIZE => 11
|
||||
)
|
||||
port map (
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
time => check_time,
|
||||
start_rtps => start_rtps,
|
||||
opcode_rtps => opcode_rtps,
|
||||
ack_rtps => ack_rtps,
|
||||
done_rtps => done_rtps,
|
||||
ret_rtps => ret_rtps,
|
||||
seq_nr_rtps => seq_nr_rtps,
|
||||
get_data_rtps => get_data_rtps,
|
||||
data_out_rtps => data_out_rtps,
|
||||
valid_out_rtps => valid_out_rtps,
|
||||
ready_out_rtps => ready_out_rtps,
|
||||
last_word_out_rtps => last_word_out_rtps,
|
||||
liveliness_assertion => liveliness_assertion,
|
||||
data_available => data_available,
|
||||
cc_instance_handle => cc_instance_handle,
|
||||
cc_kind => cc_kind,
|
||||
cc_source_timestamp => cc_source_timestamp,
|
||||
cc_seq_nr => cc_seq_nr,
|
||||
start_dds => start_dds,
|
||||
ack_dds => ack_dds,
|
||||
opcode_dds => opcode_dds,
|
||||
instance_handle_in_dds => instance_handle_in_dds,
|
||||
source_ts_dds => source_ts_dds,
|
||||
max_wait_dds => max_wait_dds,
|
||||
done_dds => done_dds,
|
||||
return_code_dds => return_code_dds,
|
||||
instance_handle_out_dds => instance_handle_out_dds,
|
||||
ready_in_dds => ready_in_dds,
|
||||
valid_in_dds => valid_in_dds,
|
||||
data_in_dds => data_in_dds,
|
||||
last_word_in_dds => last_word_in_dds,
|
||||
ready_out_dds => ready_out_dds,
|
||||
valid_out_dds => valid_out_dds,
|
||||
data_out_dds => data_out_dds,
|
||||
last_word_out_dds => last_word_out_dds,
|
||||
status => status
|
||||
);
|
||||
|
||||
stimulus_prc : process
|
||||
variable RV : RandomPType;
|
||||
variable kh1, kh2, kh3, kh4 : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
|
||||
variable cc1, cc2, cc3, cc4, cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE;
|
||||
|
||||
alias idle_sig is <<signal uut.idle_sig : std_logic>>;
|
||||
|
||||
impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is
|
||||
variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
|
||||
begin
|
||||
assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE;
|
||||
|
||||
for i in 0 to len-1 loop
|
||||
if (i < 4) then
|
||||
-- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc
|
||||
ret.data(ret.length) := not key_hash(i);
|
||||
else
|
||||
ret.data(ret.length) := RV.RandSlv(WORD_WIDTH);
|
||||
end if;
|
||||
ret.length := ret.length + 1;
|
||||
end loop;
|
||||
ret.last(ret.length-1) := '1';
|
||||
|
||||
return ret;
|
||||
end function;
|
||||
|
||||
impure function gen_key_hash return KEY_HASH_TYPE is
|
||||
variable ret : KEY_HASH_TYPE := KEY_HASH_NIL;
|
||||
begin
|
||||
for i in 0 to KEY_HASH_TYPE'length-1 loop
|
||||
ret(i) := RV.RandSlv(WORD_WIDTH);
|
||||
end loop;
|
||||
return ret;
|
||||
end function;
|
||||
|
||||
procedure start_dds is
|
||||
begin
|
||||
dds_start <= '1';
|
||||
wait until rising_edge(clk);
|
||||
dds_start <= '0';
|
||||
wait until rising_edge(clk);
|
||||
end procedure;
|
||||
|
||||
procedure start_rtps is
|
||||
begin
|
||||
rtps_start <= '1';
|
||||
wait until rising_edge(clk);
|
||||
rtps_start <= '0';
|
||||
wait until rising_edge(clk);
|
||||
end procedure;
|
||||
|
||||
procedure wait_on_dds is
|
||||
begin
|
||||
if (dds_done /= '1') then
|
||||
wait until dds_done = '1';
|
||||
end if;
|
||||
end procedure;
|
||||
|
||||
procedure wait_on_rtps is
|
||||
begin
|
||||
if (rtps_done /= '1') then
|
||||
wait until rtps_done = '1';
|
||||
end if;
|
||||
end procedure;
|
||||
|
||||
procedure wait_on_completion is
|
||||
begin
|
||||
if (rtps_done /= '1' or dds_done /= '1') then
|
||||
wait until rtps_done = '1' and dds_done = '1';
|
||||
end if;
|
||||
end procedure;
|
||||
|
||||
-- NOTE: This procedure waits until the idle_sig is high for at least
|
||||
-- two consecutive clock cycles.
|
||||
procedure wait_on_idle is
|
||||
begin
|
||||
loop
|
||||
if (idle_sig /= '1') then
|
||||
wait until idle_sig = '1';
|
||||
else
|
||||
exit;
|
||||
end if;
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
end loop;
|
||||
end procedure;
|
||||
|
||||
begin
|
||||
|
||||
SetAlertLogName("L0_dds_writer_test3_aik - (KEEP ALL, Infinite Lifespan, Keyed) - Deadline Handling");
|
||||
SetAlertEnable(FAILURE, TRUE);
|
||||
SetAlertEnable(ERROR, TRUE);
|
||||
SetAlertEnable(WARNING, TRUE);
|
||||
SetLogEnable(DEBUG, FALSE);
|
||||
SetLogEnable(PASSED, FALSE);
|
||||
SetLogEnable(INFO, TRUE);
|
||||
RV.InitSeed(RV'instance_name);
|
||||
inst_id <= GetAlertLogID("Instance", ALERTLOG_BASE_ID);
|
||||
kind_id <= GetAlertLogID("Cache Change Kind", ALERTLOG_BASE_ID);
|
||||
sn_id <= GetAlertLogID("SequenceNumber", ALERTLOG_BASE_ID);
|
||||
ts_id <= GetAlertLogID("TimeStamp", ALERTLOG_BASE_ID);
|
||||
ih_id <= GetAlertLogID("Instance Handle", ALERTLOG_BASE_ID);
|
||||
data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID);
|
||||
ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID);
|
||||
status_id <= GetAlertLogID("Communication Status", ALERTLOG_BASE_ID);
|
||||
|
||||
-- Key Hashes
|
||||
kh1 := gen_key_hash;
|
||||
kh2 := gen_key_hash;
|
||||
kh3 := gen_key_hash;
|
||||
kh4 := gen_key_hash;
|
||||
|
||||
|
||||
|
||||
Log("Initiating Test", INFO);
|
||||
Log("Current Time: 0s", INFO);
|
||||
check_time <= TIME_ZERO;
|
||||
reset <= '1';
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
reset <= '0';
|
||||
wait_on_idle;
|
||||
-- Stored CC: 0, 0, 0, 0
|
||||
|
||||
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
||||
|
||||
Log("Current Time: 1s", INFO);
|
||||
check_time <= gen_duration(1,0);
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
||||
|
||||
cc := DEFAULT_CACHE_CHANGE;
|
||||
cc.serialized_key := FALSE;
|
||||
cc.kind := ALIVE;
|
||||
cc.instance := kh1;
|
||||
cc.payload := gen_payload(kh1,10);
|
||||
cc.seq_nr := gen_sn(1);
|
||||
|
||||
Log("DDS Operation WRITE [Instance 1, HANDLE_NIL, Aligned Payload] (ACCEPTED)", INFO);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := WRITE;
|
||||
dds.cc := cc;
|
||||
dds.cc.instance:= HANDLE_NIL;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
start_dds;
|
||||
wait_on_dds;
|
||||
cc1 := cc;
|
||||
-- Stored CC: I1S1, 0, 0, 0
|
||||
|
||||
cc := DEFAULT_CACHE_CHANGE;
|
||||
cc.serialized_key := FALSE;
|
||||
cc.kind := ALIVE;
|
||||
cc.instance := kh2;
|
||||
cc.payload := gen_payload(kh2,10);
|
||||
cc.seq_nr := gen_sn(2);
|
||||
|
||||
Log("DDS Operation WRITE [Instance 2, HANDLE_NIL, Aligned Payload] (ACCEPTED)", INFO);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := WRITE;
|
||||
dds.cc := cc;
|
||||
dds.cc.instance:= HANDLE_NIL;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
start_dds;
|
||||
wait_on_dds;
|
||||
cc2 := cc;
|
||||
-- Stored CC: I1S1, I2S2, 0, 0
|
||||
|
||||
Log("Current Time: 2s", INFO);
|
||||
check_time <= gen_duration(2,0);
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
||||
|
||||
cc := DEFAULT_CACHE_CHANGE;
|
||||
cc.serialized_key := FALSE;
|
||||
cc.kind := ALIVE;
|
||||
cc.instance := kh1;
|
||||
cc.payload := gen_payload(kh1,10);
|
||||
cc.seq_nr := gen_sn(3);
|
||||
|
||||
Log("DDS Operation WRITE [Instance 1, Aligned Payload] (ACCEPTED)", INFO);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := WRITE;
|
||||
dds.cc := cc;
|
||||
dds.cc.instance:= HANDLE_NIL;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
start_dds;
|
||||
wait_on_dds;
|
||||
cc3 := cc;
|
||||
-- Stored CC: I1S1, I2S2, I1S3, 0
|
||||
|
||||
Log("Current Time: 3s", INFO);
|
||||
check_time <= gen_duration(3,0);
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
|
||||
|
||||
Log("DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS (Expected: count 1, change 1, Instance 2)", INFO);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := GET_OFFERED_DEADLINE_MISSED_STATUS;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
dds.count := 1;
|
||||
dds.change := 1;
|
||||
dds.inst := kh2;
|
||||
start_dds;
|
||||
wait_on_dds;
|
||||
|
||||
wait_on_idle;
|
||||
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
||||
|
||||
cc := DEFAULT_CACHE_CHANGE;
|
||||
cc.serialized_key := FALSE;
|
||||
cc.kind := ALIVE;
|
||||
cc.instance := kh3;
|
||||
cc.payload := gen_payload(kh3,10);
|
||||
cc.seq_nr := gen_sn(4);
|
||||
|
||||
Log("DDS Operation WRITE [Instance 3, Aligned Payload] (ACCEPTED)", INFO);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := WRITE;
|
||||
dds.cc := cc;
|
||||
dds.cc.instance:= HANDLE_NIL;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
start_dds;
|
||||
wait_on_dds;
|
||||
cc4 := cc;
|
||||
-- Stored CC: I1S1, I2S2, I1S3, I3S4
|
||||
|
||||
Log("Current Time: 4s", INFO);
|
||||
check_time <= gen_duration(4,0);
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
|
||||
|
||||
Log("DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS (Expected: count 3, change 2, Instance 1)", INFO);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := GET_OFFERED_DEADLINE_MISSED_STATUS;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
dds.count := 3;
|
||||
dds.change := 2;
|
||||
dds.inst := kh1;
|
||||
start_dds;
|
||||
wait_on_dds;
|
||||
|
||||
wait_on_idle;
|
||||
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
||||
|
||||
Log("Current Time: 5s", INFO);
|
||||
check_time <= gen_duration(5,0);
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
|
||||
|
||||
Log("Current Time: 6s", INFO);
|
||||
check_time <= gen_duration(6,0);
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
|
||||
|
||||
Log("DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS (Expected: count 9, change 6, Instance 1)", INFO);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := GET_OFFERED_DEADLINE_MISSED_STATUS;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
dds.count := 9;
|
||||
dds.change := 6;
|
||||
dds.inst := kh1;
|
||||
start_dds;
|
||||
wait_on_dds;
|
||||
|
||||
wait_on_idle;
|
||||
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
||||
|
||||
wait_on_completion;
|
||||
TranscriptOpen(RESULTS_FILE, APPEND_MODE);
|
||||
SetTranscriptMirror;
|
||||
ReportAlerts;
|
||||
TranscriptClose;
|
||||
std.env.stop;
|
||||
wait;
|
||||
end process;
|
||||
|
||||
clock_prc : process
|
||||
begin
|
||||
clk <= '0';
|
||||
wait for 25 ns;
|
||||
clk <= '1';
|
||||
wait for 25 ns;
|
||||
end process;
|
||||
|
||||
alert_prc : process(all)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
-- TODO
|
||||
end if;
|
||||
end process;
|
||||
|
||||
dds_prc : process(all)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
dds_done <= '0';
|
||||
case (dds_stage) is
|
||||
when IDLE =>
|
||||
if (dds_start = '1') then
|
||||
dds_stage <= START;
|
||||
else
|
||||
dds_done <= '1';
|
||||
end if;
|
||||
when START =>
|
||||
if (ack_dds = '1') then
|
||||
case (dds.opcode) is
|
||||
when GET_OFFERED_DEADLINE_MISSED_STATUS =>
|
||||
dds_stage <= DONE;
|
||||
dds_cnt <= 0;
|
||||
when others =>
|
||||
dds_stage <= PUSH;
|
||||
dds_cnt <= 0;
|
||||
end case;
|
||||
end if;
|
||||
when PUSH =>
|
||||
if (ready_in_dds = '1') then
|
||||
dds_cnt <= dds_cnt + 1;
|
||||
if (dds_cnt = dds.cc.payload.length-1) then
|
||||
-- DEFAULT
|
||||
dds_stage <= DONE;
|
||||
end if;
|
||||
end if;
|
||||
when DONE =>
|
||||
if (done_dds = '1') then
|
||||
if (dds.opcode = REGISTER_INSTANCE or dds.opcode = LOOKUP_INSTANCE) then
|
||||
AffirmIfEqual(ih_id, to_unsigned(instance_handle_out_dds), to_unsigned(dds.cc.instance));
|
||||
else
|
||||
AffirmIfEqual(ret_id, return_code_dds, dds.ret_code);
|
||||
case (dds.opcode) is
|
||||
when GET_OFFERED_DEADLINE_MISSED_STATUS =>
|
||||
if (dds.ret_code = RETCODE_OK) then
|
||||
dds_stage <= CHECK_DEADLINE;
|
||||
dds_cnt <= 0;
|
||||
else
|
||||
dds_stage <= IDLE;
|
||||
end if;
|
||||
when others =>
|
||||
dds_stage <= IDLE;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
when CHECK_DEADLINE =>
|
||||
if (valid_out_dds = '1') then
|
||||
dds_cnt <= dds_cnt + 1;
|
||||
case (dds_cnt) is
|
||||
when 0 =>
|
||||
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(to_unsigned(dds.count,CDR_LONG_WIDTH)));
|
||||
when 1 =>
|
||||
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(to_unsigned(dds.change,CDR_LONG_WIDTH)));
|
||||
when 2 =>
|
||||
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(0)));
|
||||
when 3 =>
|
||||
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(1)));
|
||||
when 4 =>
|
||||
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(2)));
|
||||
when 5 =>
|
||||
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(3)));
|
||||
AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR);
|
||||
dds_stage <= IDLE;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
end case;
|
||||
end if;
|
||||
|
||||
-- DEFAULT
|
||||
start_dds <= '0';
|
||||
opcode_dds <= NOP;
|
||||
valid_in_dds <= '0';
|
||||
last_word_in_dds <= '0';
|
||||
data_in_dds <= (others => '0');
|
||||
instance_handle_in_dds <= HANDLE_NIL;
|
||||
source_ts_dds <= TIME_INVALID;
|
||||
ready_out_dds <= '0';
|
||||
|
||||
case (dds_stage) is
|
||||
when START =>
|
||||
start_dds <= '1';
|
||||
opcode_dds <= dds.opcode;
|
||||
instance_handle_in_dds <= dds.cc.instance;
|
||||
source_ts_dds <= dds.cc.src_timestamp;
|
||||
when PUSH =>
|
||||
valid_in_dds <= '1';
|
||||
data_in_dds <= dds.cc.payload.data(dds_cnt);
|
||||
last_word_in_dds <= dds.cc.payload.last(dds_cnt);
|
||||
when CHECK_DEADLINE =>
|
||||
ready_out_dds <= '1';
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
rtps_prc : process(all)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
rtps_done <= '0';
|
||||
case (rtps_stage) is
|
||||
when IDLE =>
|
||||
if (rtps_start = '1') then
|
||||
rtps_stage <= START;
|
||||
else
|
||||
rtps_done <= '1';
|
||||
end if;
|
||||
when START =>
|
||||
if (ack_rtps = '1') then
|
||||
rtps_stage <= DONE;
|
||||
end if;
|
||||
when DONE =>
|
||||
if (done_rtps = '1') then
|
||||
-- DEFAULT
|
||||
rtps_stage <= IDLE;
|
||||
|
||||
AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code));
|
||||
case (rtps.opcode) is
|
||||
when GET_CACHE_CHANGE =>
|
||||
if (rtps.ret_code = OK) then
|
||||
AffirmIfEqual(inst_id, cc_instance_handle(0), rtps.cc.instance(0));
|
||||
AffirmIfEqual(inst_id, cc_instance_handle(1), rtps.cc.instance(1));
|
||||
AffirmIfEqual(inst_id, cc_instance_handle(2), rtps.cc.instance(2));
|
||||
AffirmIfEqual(inst_id, cc_instance_handle(3), rtps.cc.instance(3));
|
||||
AffirmIfEqual(kind_id, CACHE_CHANGE_KIND_TYPE'pos(cc_kind), CACHE_CHANGE_KIND_TYPE'pos(rtps.cc.kind));
|
||||
AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr));
|
||||
AffirmIfEqual(ts_id, to_unsigned(cc_source_timestamp), to_unsigned(rtps.cc.src_timestamp));
|
||||
rtps_stage <= CHECK;
|
||||
rtps_cnt <= 0;
|
||||
end if;
|
||||
when GET_MIN_SN =>
|
||||
AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr));
|
||||
when GET_MAX_SN =>
|
||||
AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr));
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
when CHECK =>
|
||||
if (valid_out_rtps = '1') then
|
||||
AffirmIfEqual(data_id, last_word_out_rtps & data_out_rtps, rtps.cc.payload.last(rtps_cnt) & rtps.cc.payload.data(rtps_cnt));
|
||||
rtps_cnt <= rtps_cnt + 1;
|
||||
if (rtps_cnt = rtps.cc.payload.length-1) then
|
||||
rtps_stage <= IDLE;
|
||||
end if;
|
||||
end if;
|
||||
end case;
|
||||
end if;
|
||||
|
||||
-- DEFAULT
|
||||
start_rtps <= '0';
|
||||
opcode_rtps <= NOP;
|
||||
seq_nr_rtps <= SEQUENCENUMBER_UNKNOWN;
|
||||
get_data_rtps <= '0';
|
||||
ready_out_rtps <= '0';
|
||||
|
||||
case (rtps_stage) is
|
||||
when START =>
|
||||
start_rtps <= '1';
|
||||
opcode_rtps <= rtps.opcode;
|
||||
seq_nr_rtps <= rtps.cc.seq_nr;
|
||||
when DONE =>
|
||||
if (done_rtps = '1') then
|
||||
case (rtps.opcode) is
|
||||
when GET_CACHE_CHANGE =>
|
||||
get_data_rtps <= '1';
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
when CHECK =>
|
||||
ready_out_rtps <= '1';
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
watchdog : process
|
||||
begin
|
||||
wait for 1 ms;
|
||||
Alert("Test timeout", FAILURE);
|
||||
std.env.stop;
|
||||
end process;
|
||||
|
||||
end architecture;
|
||||
@ -1,543 +0,0 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library osvvm; -- Utility Library
|
||||
context osvvm.OsvvmContext;
|
||||
|
||||
use work.rtps_package.all;
|
||||
use work.user_config.all;
|
||||
use work.rtps_config_package.all;
|
||||
use work.rtps_test_package.all;
|
||||
|
||||
-- This testbench tests the Deadline Handling of the DDS Writer, and more specifically the GET_OFFERED_DEADLINE_MISSED_STATUS DDS Operation.
|
||||
|
||||
entity L0_dds_writer_test3_ain is
|
||||
end entity;
|
||||
|
||||
architecture testbench of L0_dds_writer_test3_ain is
|
||||
|
||||
-- *CONSTANT DECLARATION*
|
||||
constant MAX_REMOTE_ENDPOINTS : natural := 3;
|
||||
|
||||
-- *TYPE DECLARATION*
|
||||
type DDS_STAGE_TYPE is (IDLE, START, PUSH, DONE, CHECK_DEADLINE);
|
||||
type RTPS_STAGE_TYPE is (IDLE, START, DONE, CHECK);
|
||||
|
||||
-- *SIGNAL DECLARATION*
|
||||
signal clk : std_logic := '0';
|
||||
signal reset : std_logic := '1';
|
||||
signal check_time : TIME_TYPE := TIME_ZERO;
|
||||
signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0';
|
||||
signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP;
|
||||
signal opcode_dds : DDS_WRITER_OPCODE_TYPE := NOP;
|
||||
signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR;
|
||||
signal seq_nr_rtps, cc_seq_nr : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN;
|
||||
signal ready_out_rtps, valid_out_rtps, last_word_out_rtps : std_logic := '0';
|
||||
signal ready_in_dds, ready_out_dds, valid_in_dds, valid_out_dds, last_word_in_dds, last_word_out_dds : std_logic := '0';
|
||||
signal data_out_rtps, data_in_dds, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
|
||||
signal get_data_rtps, liveliness_assertion, data_available : std_logic := '0';
|
||||
signal cc_source_timestamp, source_ts_dds : TIME_TYPE := TIME_INVALID;
|
||||
signal cc_kind : CACHE_CHANGE_KIND_TYPE := ALIVE;
|
||||
signal cc_instance_handle, instance_handle_in_dds, instance_handle_out_dds : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
|
||||
signal max_wait_dds : DURATION_TYPE := DURATION_INFINITE;
|
||||
signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0');
|
||||
signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0');
|
||||
|
||||
signal dds_start, dds_done, rtps_start, rtps_done : std_logic := '0';
|
||||
signal dds_cnt, rtps_cnt : natural := 0;
|
||||
signal dds_stage : DDS_STAGE_TYPE := IDLE;
|
||||
signal rtps_stage : RTPS_STAGE_TYPE := IDLE;
|
||||
shared variable dds : DDS_WRITER_TEST_TYPE := DEFAULT_DDS_WRITER_TEST;
|
||||
shared variable rtps : RTPS_WRITER_TEST_TYPE := DEFAULT_RTPS_WRITER_TEST;
|
||||
signal inst_id, kind_id, sn_id, ts_id, ih_id, ret_id, status_id, data_id : AlertLogIDType;
|
||||
|
||||
-- *FUNCTION DECLARATION*
|
||||
function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is
|
||||
variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
|
||||
begin
|
||||
for i in 0 to 3 loop
|
||||
ret(i) := not payload.data(i);
|
||||
end loop;
|
||||
|
||||
return ret;
|
||||
end function;
|
||||
|
||||
function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is
|
||||
variable ret : SEQUENCENUMBER_TYPE;
|
||||
begin
|
||||
ret(0) := (others => '0');
|
||||
ret(1) := unsigned(int(input, WORD_WIDTH));
|
||||
return ret;
|
||||
end function;
|
||||
|
||||
begin
|
||||
|
||||
-- Unit Under Test
|
||||
uut : entity work.dds_writer(arch)
|
||||
generic map(
|
||||
HISTORY_QOS => KEEP_ALL_HISTORY_QOS,
|
||||
DEADLINE_QOS => gen_duration(1,0),
|
||||
LIFESPAN_QOS => DURATION_INFINITE,
|
||||
LEASE_DURATION => DURATION_INFINITE,
|
||||
WITH_KEY => FALSE,
|
||||
MAX_SAMPLES => std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)),
|
||||
MAX_INSTANCES => std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)),
|
||||
MAX_SAMPLES_PER_INSTANCE => std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)),
|
||||
PAYLOAD_FRAME_SIZE => 11
|
||||
)
|
||||
port map (
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
time => check_time,
|
||||
start_rtps => start_rtps,
|
||||
opcode_rtps => opcode_rtps,
|
||||
ack_rtps => ack_rtps,
|
||||
done_rtps => done_rtps,
|
||||
ret_rtps => ret_rtps,
|
||||
seq_nr_rtps => seq_nr_rtps,
|
||||
get_data_rtps => get_data_rtps,
|
||||
data_out_rtps => data_out_rtps,
|
||||
valid_out_rtps => valid_out_rtps,
|
||||
ready_out_rtps => ready_out_rtps,
|
||||
last_word_out_rtps => last_word_out_rtps,
|
||||
liveliness_assertion => liveliness_assertion,
|
||||
data_available => data_available,
|
||||
cc_instance_handle => cc_instance_handle,
|
||||
cc_kind => cc_kind,
|
||||
cc_source_timestamp => cc_source_timestamp,
|
||||
cc_seq_nr => cc_seq_nr,
|
||||
start_dds => start_dds,
|
||||
ack_dds => ack_dds,
|
||||
opcode_dds => opcode_dds,
|
||||
instance_handle_in_dds => instance_handle_in_dds,
|
||||
source_ts_dds => source_ts_dds,
|
||||
max_wait_dds => max_wait_dds,
|
||||
done_dds => done_dds,
|
||||
return_code_dds => return_code_dds,
|
||||
instance_handle_out_dds => instance_handle_out_dds,
|
||||
ready_in_dds => ready_in_dds,
|
||||
valid_in_dds => valid_in_dds,
|
||||
data_in_dds => data_in_dds,
|
||||
last_word_in_dds => last_word_in_dds,
|
||||
ready_out_dds => ready_out_dds,
|
||||
valid_out_dds => valid_out_dds,
|
||||
data_out_dds => data_out_dds,
|
||||
last_word_out_dds => last_word_out_dds,
|
||||
status => status
|
||||
);
|
||||
|
||||
stimulus_prc : process
|
||||
variable RV : RandomPType;
|
||||
variable kh1, kh2, kh3, kh4 : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
|
||||
variable cc1, cc2, cc3, cc4, cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE;
|
||||
|
||||
alias idle_sig is <<signal uut.idle_sig : std_logic>>;
|
||||
|
||||
impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is
|
||||
variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
|
||||
begin
|
||||
assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE;
|
||||
|
||||
for i in 0 to len-1 loop
|
||||
if (i < 4) then
|
||||
-- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc
|
||||
ret.data(ret.length) := not key_hash(i);
|
||||
else
|
||||
ret.data(ret.length) := RV.RandSlv(WORD_WIDTH);
|
||||
end if;
|
||||
ret.length := ret.length + 1;
|
||||
end loop;
|
||||
ret.last(ret.length-1) := '1';
|
||||
|
||||
return ret;
|
||||
end function;
|
||||
|
||||
impure function gen_key_hash return KEY_HASH_TYPE is
|
||||
variable ret : KEY_HASH_TYPE := KEY_HASH_NIL;
|
||||
begin
|
||||
for i in 0 to KEY_HASH_TYPE'length-1 loop
|
||||
ret(i) := RV.RandSlv(WORD_WIDTH);
|
||||
end loop;
|
||||
return ret;
|
||||
end function;
|
||||
|
||||
procedure start_dds is
|
||||
begin
|
||||
dds_start <= '1';
|
||||
wait until rising_edge(clk);
|
||||
dds_start <= '0';
|
||||
wait until rising_edge(clk);
|
||||
end procedure;
|
||||
|
||||
procedure start_rtps is
|
||||
begin
|
||||
rtps_start <= '1';
|
||||
wait until rising_edge(clk);
|
||||
rtps_start <= '0';
|
||||
wait until rising_edge(clk);
|
||||
end procedure;
|
||||
|
||||
procedure wait_on_dds is
|
||||
begin
|
||||
if (dds_done /= '1') then
|
||||
wait until dds_done = '1';
|
||||
end if;
|
||||
end procedure;
|
||||
|
||||
procedure wait_on_rtps is
|
||||
begin
|
||||
if (rtps_done /= '1') then
|
||||
wait until rtps_done = '1';
|
||||
end if;
|
||||
end procedure;
|
||||
|
||||
procedure wait_on_completion is
|
||||
begin
|
||||
if (rtps_done /= '1' or dds_done /= '1') then
|
||||
wait until rtps_done = '1' and dds_done = '1';
|
||||
end if;
|
||||
end procedure;
|
||||
|
||||
-- NOTE: This procedure waits until the idle_sig is high for at least
|
||||
-- two consecutive clock cycles.
|
||||
procedure wait_on_idle is
|
||||
begin
|
||||
loop
|
||||
if (idle_sig /= '1') then
|
||||
wait until idle_sig = '1';
|
||||
else
|
||||
exit;
|
||||
end if;
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
end loop;
|
||||
end procedure;
|
||||
|
||||
begin
|
||||
|
||||
SetAlertLogName("L0_dds_writer_test3_ain - (KEEP ALL, Infinite Lifespan, Keyed) - Deadline Handling");
|
||||
SetAlertEnable(FAILURE, TRUE);
|
||||
SetAlertEnable(ERROR, TRUE);
|
||||
SetAlertEnable(WARNING, TRUE);
|
||||
SetLogEnable(DEBUG, FALSE);
|
||||
SetLogEnable(PASSED, FALSE);
|
||||
SetLogEnable(INFO, TRUE);
|
||||
RV.InitSeed(RV'instance_name);
|
||||
inst_id <= GetAlertLogID("Instance", ALERTLOG_BASE_ID);
|
||||
kind_id <= GetAlertLogID("Cache Change Kind", ALERTLOG_BASE_ID);
|
||||
sn_id <= GetAlertLogID("SequenceNumber", ALERTLOG_BASE_ID);
|
||||
ts_id <= GetAlertLogID("TimeStamp", ALERTLOG_BASE_ID);
|
||||
ih_id <= GetAlertLogID("Instance Handle", ALERTLOG_BASE_ID);
|
||||
data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID);
|
||||
ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID);
|
||||
status_id <= GetAlertLogID("Communication Status", ALERTLOG_BASE_ID);
|
||||
|
||||
-- Key Hashes
|
||||
kh1 := gen_key_hash;
|
||||
kh2 := gen_key_hash;
|
||||
kh3 := gen_key_hash;
|
||||
kh4 := gen_key_hash;
|
||||
|
||||
|
||||
|
||||
Log("Initiating Test", INFO);
|
||||
Log("Current Time: 0s", INFO);
|
||||
check_time <= TIME_ZERO;
|
||||
reset <= '1';
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
reset <= '0';
|
||||
wait_on_idle;
|
||||
-- Stored CC: 0, 0, 0, 0
|
||||
|
||||
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
||||
|
||||
Log("Current Time: 1s", INFO);
|
||||
check_time <= gen_duration(1,0);
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
|
||||
|
||||
Log("DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS (Expected: count 1, change 1)", INFO);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := GET_OFFERED_DEADLINE_MISSED_STATUS;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
dds.count := 1;
|
||||
dds.change := 1;
|
||||
start_dds;
|
||||
wait_on_dds;
|
||||
|
||||
wait_on_idle;
|
||||
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
||||
|
||||
cc := DEFAULT_CACHE_CHANGE;
|
||||
cc.serialized_key := FALSE;
|
||||
cc.kind := ALIVE;
|
||||
cc.instance := kh1;
|
||||
cc.payload := gen_payload(kh1,10);
|
||||
cc.seq_nr := gen_sn(1);
|
||||
|
||||
Log("DDS Operation WRITE [Aligned Payload] (ACCEPTED)", INFO);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := WRITE;
|
||||
dds.cc := cc;
|
||||
dds.cc.instance:= HANDLE_NIL;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
start_dds;
|
||||
wait_on_dds;
|
||||
cc1 := cc;
|
||||
-- Stored CC: I1S1, 0, 0, 0
|
||||
|
||||
Log("Current Time: 2s", INFO);
|
||||
check_time <= gen_duration(2,0);
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
||||
|
||||
Log("Current Time: 3s", INFO);
|
||||
check_time <= gen_duration(3,0);
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
|
||||
|
||||
Log("Current Time: 4s", INFO);
|
||||
check_time <= gen_duration(4,0);
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
|
||||
|
||||
Log("DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS (Expected: count 3, change 2)", INFO);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := GET_OFFERED_DEADLINE_MISSED_STATUS;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
dds.count := 3;
|
||||
dds.change := 2;
|
||||
start_dds;
|
||||
wait_on_dds;
|
||||
|
||||
wait_on_idle;
|
||||
AffirmIf(status_id,(status and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
||||
|
||||
wait_on_completion;
|
||||
TranscriptOpen(RESULTS_FILE, APPEND_MODE);
|
||||
SetTranscriptMirror;
|
||||
ReportAlerts;
|
||||
TranscriptClose;
|
||||
std.env.stop;
|
||||
wait;
|
||||
end process;
|
||||
|
||||
clock_prc : process
|
||||
begin
|
||||
clk <= '0';
|
||||
wait for 25 ns;
|
||||
clk <= '1';
|
||||
wait for 25 ns;
|
||||
end process;
|
||||
|
||||
alert_prc : process(all)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
-- TODO
|
||||
end if;
|
||||
end process;
|
||||
|
||||
dds_prc : process(all)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
dds_done <= '0';
|
||||
case (dds_stage) is
|
||||
when IDLE =>
|
||||
if (dds_start = '1') then
|
||||
dds_stage <= START;
|
||||
else
|
||||
dds_done <= '1';
|
||||
end if;
|
||||
when START =>
|
||||
if (ack_dds = '1') then
|
||||
case (dds.opcode) is
|
||||
when GET_OFFERED_DEADLINE_MISSED_STATUS =>
|
||||
dds_stage <= DONE;
|
||||
dds_cnt <= 0;
|
||||
when others =>
|
||||
dds_stage <= PUSH;
|
||||
dds_cnt <= 0;
|
||||
end case;
|
||||
end if;
|
||||
when PUSH =>
|
||||
if (ready_in_dds = '1') then
|
||||
dds_cnt <= dds_cnt + 1;
|
||||
if (dds_cnt = dds.cc.payload.length-1) then
|
||||
-- DEFAULT
|
||||
dds_stage <= DONE;
|
||||
end if;
|
||||
end if;
|
||||
when DONE =>
|
||||
if (done_dds = '1') then
|
||||
if (dds.opcode = REGISTER_INSTANCE or dds.opcode = LOOKUP_INSTANCE) then
|
||||
AffirmIfEqual(ih_id, to_unsigned(instance_handle_out_dds), to_unsigned(dds.cc.instance));
|
||||
else
|
||||
AffirmIfEqual(ret_id, return_code_dds, dds.ret_code);
|
||||
case (dds.opcode) is
|
||||
when GET_OFFERED_DEADLINE_MISSED_STATUS =>
|
||||
if (dds.ret_code = RETCODE_OK) then
|
||||
dds_stage <= CHECK_DEADLINE;
|
||||
dds_cnt <= 0;
|
||||
else
|
||||
dds_stage <= IDLE;
|
||||
end if;
|
||||
when others =>
|
||||
dds_stage <= IDLE;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
when CHECK_DEADLINE =>
|
||||
if (valid_out_dds = '1') then
|
||||
dds_cnt <= dds_cnt + 1;
|
||||
case (dds_cnt) is
|
||||
when 0 =>
|
||||
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(to_unsigned(dds.count,CDR_LONG_WIDTH)));
|
||||
when 1 =>
|
||||
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(to_unsigned(dds.change,CDR_LONG_WIDTH)));
|
||||
when 2 =>
|
||||
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(0)));
|
||||
when 3 =>
|
||||
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(1)));
|
||||
when 4 =>
|
||||
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(2)));
|
||||
when 5 =>
|
||||
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(dds.inst(3)));
|
||||
AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR);
|
||||
dds_stage <= IDLE;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
end case;
|
||||
end if;
|
||||
|
||||
-- DEFAULT
|
||||
start_dds <= '0';
|
||||
opcode_dds <= NOP;
|
||||
valid_in_dds <= '0';
|
||||
last_word_in_dds <= '0';
|
||||
data_in_dds <= (others => '0');
|
||||
instance_handle_in_dds <= HANDLE_NIL;
|
||||
source_ts_dds <= TIME_INVALID;
|
||||
ready_out_dds <= '0';
|
||||
|
||||
case (dds_stage) is
|
||||
when START =>
|
||||
start_dds <= '1';
|
||||
opcode_dds <= dds.opcode;
|
||||
instance_handle_in_dds <= dds.cc.instance;
|
||||
source_ts_dds <= dds.cc.src_timestamp;
|
||||
when PUSH =>
|
||||
valid_in_dds <= '1';
|
||||
data_in_dds <= dds.cc.payload.data(dds_cnt);
|
||||
last_word_in_dds <= dds.cc.payload.last(dds_cnt);
|
||||
when CHECK_DEADLINE =>
|
||||
ready_out_dds <= '1';
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
rtps_prc : process(all)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
rtps_done <= '0';
|
||||
case (rtps_stage) is
|
||||
when IDLE =>
|
||||
if (rtps_start = '1') then
|
||||
rtps_stage <= START;
|
||||
else
|
||||
rtps_done <= '1';
|
||||
end if;
|
||||
when START =>
|
||||
if (ack_rtps = '1') then
|
||||
rtps_stage <= DONE;
|
||||
end if;
|
||||
when DONE =>
|
||||
if (done_rtps = '1') then
|
||||
-- DEFAULT
|
||||
rtps_stage <= IDLE;
|
||||
|
||||
AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code));
|
||||
case (rtps.opcode) is
|
||||
when GET_CACHE_CHANGE =>
|
||||
if (rtps.ret_code = OK) then
|
||||
AffirmIfEqual(inst_id, cc_instance_handle(0), rtps.cc.instance(0));
|
||||
AffirmIfEqual(inst_id, cc_instance_handle(1), rtps.cc.instance(1));
|
||||
AffirmIfEqual(inst_id, cc_instance_handle(2), rtps.cc.instance(2));
|
||||
AffirmIfEqual(inst_id, cc_instance_handle(3), rtps.cc.instance(3));
|
||||
AffirmIfEqual(kind_id, CACHE_CHANGE_KIND_TYPE'pos(cc_kind), CACHE_CHANGE_KIND_TYPE'pos(rtps.cc.kind));
|
||||
AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr));
|
||||
AffirmIfEqual(ts_id, to_unsigned(cc_source_timestamp), to_unsigned(rtps.cc.src_timestamp));
|
||||
rtps_stage <= CHECK;
|
||||
rtps_cnt <= 0;
|
||||
end if;
|
||||
when GET_MIN_SN =>
|
||||
AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr));
|
||||
when GET_MAX_SN =>
|
||||
AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr));
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
when CHECK =>
|
||||
if (valid_out_rtps = '1') then
|
||||
AffirmIfEqual(data_id, last_word_out_rtps & data_out_rtps, rtps.cc.payload.last(rtps_cnt) & rtps.cc.payload.data(rtps_cnt));
|
||||
rtps_cnt <= rtps_cnt + 1;
|
||||
if (rtps_cnt = rtps.cc.payload.length-1) then
|
||||
rtps_stage <= IDLE;
|
||||
end if;
|
||||
end if;
|
||||
end case;
|
||||
end if;
|
||||
|
||||
-- DEFAULT
|
||||
start_rtps <= '0';
|
||||
opcode_rtps <= NOP;
|
||||
seq_nr_rtps <= SEQUENCENUMBER_UNKNOWN;
|
||||
get_data_rtps <= '0';
|
||||
ready_out_rtps <= '0';
|
||||
|
||||
case (rtps_stage) is
|
||||
when START =>
|
||||
start_rtps <= '1';
|
||||
opcode_rtps <= rtps.opcode;
|
||||
seq_nr_rtps <= rtps.cc.seq_nr;
|
||||
when DONE =>
|
||||
if (done_rtps = '1') then
|
||||
case (rtps.opcode) is
|
||||
when GET_CACHE_CHANGE =>
|
||||
get_data_rtps <= '1';
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
when CHECK =>
|
||||
ready_out_rtps <= '1';
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
watchdog : process
|
||||
begin
|
||||
wait for 1 ms;
|
||||
Alert("Test timeout", FAILURE);
|
||||
std.env.stop;
|
||||
end process;
|
||||
|
||||
end architecture;
|
||||
@ -12,13 +12,41 @@ use work.rtps_test_package.all;
|
||||
|
||||
-- This testbench tests the Liveliness Handling of the DDS Writer, and more specifically the DDS GET_LIVELINESS_LOST_STATUS, and ASSERT_LIVELINESS Operations.
|
||||
|
||||
entity L0_dds_writer_test4_aik is
|
||||
entity L0_dds_writer_test4 is
|
||||
end entity;
|
||||
|
||||
architecture testbench of L0_dds_writer_test4_aik is
|
||||
architecture testbench of L0_dds_writer_test4 is
|
||||
|
||||
-- *CONSTANT DECLARATION*
|
||||
constant MAX_REMOTE_ENDPOINTS : natural := 3;
|
||||
constant MAX_REMOTE_ENDPOINTS : natural := 3;
|
||||
constant NUM_WRITERS : natural := 2;
|
||||
|
||||
impure function gen_test_config return CONFIG_ARRAY_TYPE is
|
||||
variable ret : CONFIG_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => DEFAULT_WRITER_CONFIG);
|
||||
begin
|
||||
-- aik
|
||||
ret(0).HISTORY_QOS := KEEP_ALL_HISTORY_QOS;
|
||||
ret(0).DEADLINE_QOS := DURATION_INFINITE;
|
||||
ret(0).LIFESPAN_QOS := DURATION_INFINITE;
|
||||
ret(0).LEASE_DURATION := gen_duration(1 sec);
|
||||
ret(0).WITH_KEY := TRUE;
|
||||
ret(0).MAX_SAMPLES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH));
|
||||
ret(0).MAX_INSTANCES := std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH));
|
||||
ret(0).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH));
|
||||
ret(0).MAX_PAYLOAD_SIZE := 40;
|
||||
-- ain
|
||||
ret(1).HISTORY_QOS := KEEP_ALL_HISTORY_QOS;
|
||||
ret(1).DEADLINE_QOS := DURATION_INFINITE;
|
||||
ret(1).LIFESPAN_QOS := DURATION_INFINITE;
|
||||
ret(1).LEASE_DURATION := gen_duration(2 sec);
|
||||
ret(1).WITH_KEY := FALSE;
|
||||
ret(1).MAX_SAMPLES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH));
|
||||
ret(1).MAX_INSTANCES := std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH));
|
||||
ret(1).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH));
|
||||
ret(1).MAX_PAYLOAD_SIZE := 40;
|
||||
return ret;
|
||||
end function;
|
||||
constant TEST_CONFIG : CONFIG_ARRAY_TYPE := gen_test_config;
|
||||
|
||||
-- *TYPE DECLARATION*
|
||||
type DDS_STAGE_TYPE is (IDLE, START, PUSH, DONE, CHECK_LIVELINESS);
|
||||
@ -28,22 +56,23 @@ architecture testbench of L0_dds_writer_test4_aik is
|
||||
signal clk : std_logic := '0';
|
||||
signal reset : std_logic := '1';
|
||||
signal check_time : TIME_TYPE := TIME_ZERO;
|
||||
signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0';
|
||||
signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP;
|
||||
signal opcode_dds : DDS_WRITER_OPCODE_TYPE := NOP;
|
||||
signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR;
|
||||
signal seq_nr_rtps, cc_seq_nr : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN;
|
||||
signal ready_out_rtps, valid_out_rtps, last_word_out_rtps : std_logic := '0';
|
||||
signal ready_in_dds, ready_out_dds, valid_in_dds, valid_out_dds, last_word_in_dds, last_word_out_dds : std_logic := '0';
|
||||
signal data_out_rtps, data_in_dds, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
|
||||
signal get_data_rtps, liveliness_assertion, data_available : std_logic := '0';
|
||||
signal cc_source_timestamp, source_ts_dds : TIME_TYPE := TIME_INVALID;
|
||||
signal cc_kind : CACHE_CHANGE_KIND_TYPE := ALIVE;
|
||||
signal cc_instance_handle, instance_handle_in_dds, instance_handle_out_dds : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
|
||||
signal max_wait_dds : DURATION_TYPE := DURATION_INFINITE;
|
||||
signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0');
|
||||
signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0');
|
||||
signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds, w_map : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0');
|
||||
signal opcode_rtps : HISTORY_CACHE_OPCODE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => NOP);
|
||||
signal opcode_dds : DDS_WRITER_OPCODE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => NOP);
|
||||
signal ret_rtps : HISTORY_CACHE_RESPONSE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => ERROR);
|
||||
signal seq_nr_rtps, cc_seq_nr : SEQUENCENUMBER_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => SEQUENCENUMBER_UNKNOWN);
|
||||
signal ready_out_rtps, valid_out_rtps, last_word_out_rtps : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0');
|
||||
signal ready_in_dds, ready_out_dds, valid_in_dds, valid_out_dds, last_word_in_dds, last_word_out_dds : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0');
|
||||
signal data_out_rtps, data_in_dds, data_out_dds : WORD_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => (others => '0'));
|
||||
signal get_data_rtps, liveliness_assertion, data_available : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0');
|
||||
signal cc_source_timestamp, source_ts_dds : TIME_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => TIME_INVALID);
|
||||
signal cc_kind : CACHE_CHANGE_KIND_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => ALIVE);
|
||||
signal cc_instance_handle, instance_handle_in_dds, instance_handle_out_dds : INSTANCE_HANDLE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => HANDLE_NIL);
|
||||
signal max_wait_dds : DURATION_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => DURATION_INFINITE);
|
||||
signal return_code_dds : RETURN_CODE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => (others => '0'));
|
||||
signal status : STATUS_KIND_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => (others => '0'));
|
||||
|
||||
signal ind : natural := 0;
|
||||
signal dds_start, dds_done, rtps_start, rtps_done : std_logic := '0';
|
||||
signal dds_cnt, rtps_cnt : natural := 0;
|
||||
signal dds_stage : DDS_STAGE_TYPE := IDLE;
|
||||
@ -71,20 +100,20 @@ architecture testbench of L0_dds_writer_test4_aik is
|
||||
return ret;
|
||||
end function;
|
||||
|
||||
procedure wait_on_sig(signal sig : std_logic) is
|
||||
begin
|
||||
if (sig /= '1') then
|
||||
wait on sig until sig = '1';
|
||||
end if;
|
||||
end procedure;
|
||||
|
||||
begin
|
||||
|
||||
-- Unit Under Test
|
||||
uut : entity work.dds_writer(arch)
|
||||
generic map(
|
||||
HISTORY_QOS => KEEP_ALL_HISTORY_QOS,
|
||||
DEADLINE_QOS => DURATION_INFINITE,
|
||||
LIFESPAN_QOS => DURATION_INFINITE,
|
||||
LEASE_DURATION => gen_duration(1,0),
|
||||
WITH_KEY => TRUE,
|
||||
MAX_SAMPLES => std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)),
|
||||
MAX_INSTANCES => std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH)),
|
||||
MAX_SAMPLES_PER_INSTANCE => std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)),
|
||||
PAYLOAD_FRAME_SIZE => 11
|
||||
NUM_WRITERS => NUM_WRITERS,
|
||||
CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(TEST_CONFIG)
|
||||
)
|
||||
port map (
|
||||
clk => clk,
|
||||
@ -178,20 +207,6 @@ begin
|
||||
wait until rising_edge(clk);
|
||||
end procedure;
|
||||
|
||||
procedure wait_on_dds is
|
||||
begin
|
||||
if (dds_done /= '1') then
|
||||
wait until dds_done = '1';
|
||||
end if;
|
||||
end procedure;
|
||||
|
||||
procedure wait_on_rtps is
|
||||
begin
|
||||
if (rtps_done /= '1') then
|
||||
wait until rtps_done = '1';
|
||||
end if;
|
||||
end procedure;
|
||||
|
||||
procedure wait_on_completion is
|
||||
begin
|
||||
if (rtps_done /= '1' or dds_done /= '1') then
|
||||
@ -202,21 +217,23 @@ begin
|
||||
-- NOTE: This procedure waits until the idle_sig is high for at least
|
||||
-- two consecutive clock cycles.
|
||||
procedure wait_on_idle is
|
||||
variable first : boolean := TRUE;
|
||||
begin
|
||||
loop
|
||||
if (idle_sig /= '1') then
|
||||
wait until idle_sig = '1';
|
||||
else
|
||||
elsif (not first) then
|
||||
exit;
|
||||
end if;
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
first := FALSE;
|
||||
end loop;
|
||||
end procedure;
|
||||
|
||||
begin
|
||||
|
||||
SetAlertLogName("L0_dds_writer_test4_aik - (KEEP ALL, Infinite Lifespan, Keyed) - Liveliness Handling");
|
||||
SetAlertLogName("L0_dds_writer_test4 - Liveliness Handling");
|
||||
SetAlertEnable(FAILURE, TRUE);
|
||||
SetAlertEnable(ERROR, TRUE);
|
||||
SetAlertEnable(WARNING, TRUE);
|
||||
@ -248,37 +265,59 @@ begin
|
||||
wait until rising_edge(clk);
|
||||
reset <= '0';
|
||||
wait_on_idle;
|
||||
-- Stored CC: 0, 0, 0, 0
|
||||
|
||||
AffirmIf(status_id,(status and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1");
|
||||
AffirmIf(status_id,(status(0) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1");
|
||||
AffirmIf(status_id,(status(1) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1");
|
||||
|
||||
Log("Current Time: 1s", INFO);
|
||||
check_time <= gen_duration(1,0);
|
||||
check_time <= gen_duration(1 sec);
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status and LIVELINESS_LOST_STATUS) = LIVELINESS_LOST_STATUS, "Expected: 1", "Received 0");
|
||||
AffirmIf(status_id,(status(0) and LIVELINESS_LOST_STATUS) = LIVELINESS_LOST_STATUS, "Expected: 1", "Received 0");
|
||||
AffirmIf(status_id,(status(1) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1");
|
||||
|
||||
Log("DDS Operation GET_LIVELINESS_LOST_STATUS (Expected: count 1, change 1)", INFO);
|
||||
Log("W0: DDS Operation GET_LIVELINESS_LOST_STATUS", INFO);
|
||||
Log("W0: Expected [count 1, change 1]", DEBUG);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := GET_LIVELINESS_LOST_STATUS;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
dds.count := 1;
|
||||
dds.change := 1;
|
||||
-- WRITER 0
|
||||
ind <= 0;
|
||||
start_dds;
|
||||
wait_on_dds;
|
||||
|
||||
wait_on_sig(dds_done);
|
||||
wait_on_idle;
|
||||
AffirmIf(status_id,(status and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1");
|
||||
|
||||
AffirmIf(status_id,(status(0) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1");
|
||||
AffirmIf(status_id,(status(1) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1");
|
||||
|
||||
Log("W1: DDS Operation GET_LIVELINESS_LOST_STATUS", INFO);
|
||||
Log("W1: Expected [count 0, change 0]", DEBUG);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := GET_LIVELINESS_LOST_STATUS;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
dds.count := 0;
|
||||
dds.change := 0;
|
||||
-- WRITER 1
|
||||
ind <= 1;
|
||||
start_dds;
|
||||
wait_on_sig(dds_done);
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status(0) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1");
|
||||
AffirmIf(status_id,(status(1) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1");
|
||||
|
||||
Log("Current Time: 1.5s", INFO);
|
||||
check_time <= gen_duration(1,500);
|
||||
check_time <= gen_duration(1.5 sec);
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1");
|
||||
AffirmIf(status_id,(status(0) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1");
|
||||
AffirmIf(status_id,(status(1) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1");
|
||||
|
||||
cc := DEFAULT_CACHE_CHANGE;
|
||||
cc.serialized_key := FALSE;
|
||||
@ -287,32 +326,40 @@ begin
|
||||
cc.payload := gen_payload(kh1,10);
|
||||
cc.seq_nr := gen_sn(1);
|
||||
|
||||
Log("DDS Operation WRITE [Instance 1, HANDLE_NIL, Aligned Payload] (ACCEPTED)", INFO);
|
||||
Log("W0,W1: DDS Operation WRITE [Instance 1, HANDLE_NIL, Aligned Payload]", INFO);
|
||||
Log("W0,W1: ACCEPTED", DEBUG);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := WRITE;
|
||||
dds.cc := cc;
|
||||
dds.cc.instance:= HANDLE_NIL;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
-- WRITER 0
|
||||
ind <= 0;
|
||||
start_dds;
|
||||
wait_on_dds;
|
||||
cc1 := cc;
|
||||
-- Stored CC: I1S1, 0, 0, 0
|
||||
wait_on_sig(dds_done);
|
||||
-- WRITER 1
|
||||
ind <= 1;
|
||||
start_dds;
|
||||
wait_on_sig(dds_done);
|
||||
wait_on_idle;
|
||||
|
||||
Log("Current Time: 2s", INFO);
|
||||
check_time <= gen_duration(2,0);
|
||||
check_time <= gen_duration(2 sec);
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1");
|
||||
AffirmIf(status_id,(status(0) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1");
|
||||
AffirmIf(status_id,(status(1) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1");
|
||||
|
||||
Log("Current Time: 2.4s", INFO);
|
||||
check_time <= gen_duration(2,400);
|
||||
check_time <= gen_duration(2.4 sec);
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1");
|
||||
AffirmIf(status_id,(status(0) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1");
|
||||
AffirmIf(status_id,(status(1) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1");
|
||||
|
||||
cc := DEFAULT_CACHE_CHANGE;
|
||||
cc.serialized_key := TRUE;
|
||||
@ -321,31 +368,40 @@ begin
|
||||
cc.payload := gen_payload(kh1,5);
|
||||
cc.seq_nr := gen_sn(2);
|
||||
|
||||
Log("DDS Operation DISPOSE [Instance 1] (ACCEPTED)", INFO);
|
||||
Log("W0,W1: DDS Operation DISPOSE [Instance 1]", INFO);
|
||||
Log("W0,W1: ACCEPTED", DEBUG);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := DISPOSE;
|
||||
dds.cc := cc;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
-- WRITER 0
|
||||
ind <= 0;
|
||||
start_dds;
|
||||
wait_on_dds;
|
||||
cc2 := cc;
|
||||
-- Stored CC: I1S1, I1S2, 0, 0
|
||||
wait_on_sig(dds_done);
|
||||
-- WRITER 1
|
||||
dds.cc.instance := HANDLE_NIL;
|
||||
ind <= 1;
|
||||
start_dds;
|
||||
wait_on_sig(dds_done);
|
||||
wait_on_idle;
|
||||
|
||||
Log("Current Time: 3s", INFO);
|
||||
check_time <= gen_duration(3,0);
|
||||
check_time <= gen_duration(3 sec);
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1");
|
||||
AffirmIf(status_id,(status(0) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1");
|
||||
AffirmIf(status_id,(status(1) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1");
|
||||
|
||||
Log("Current Time: 3.3s", INFO);
|
||||
check_time <= gen_duration(3,300);
|
||||
check_time <= gen_duration(3.3 sec);
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1");
|
||||
AffirmIf(status_id,(status(0) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1");
|
||||
AffirmIf(status_id,(status(1) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1");
|
||||
|
||||
cc := DEFAULT_CACHE_CHANGE;
|
||||
cc.serialized_key := TRUE;
|
||||
@ -354,75 +410,143 @@ begin
|
||||
cc.payload := gen_payload(kh1,5);
|
||||
cc.seq_nr := gen_sn(3);
|
||||
|
||||
Log("DDS Operation UNREGISTER_INSTANCE [Instance 1] (ACCEPTED)", INFO);
|
||||
Log("W0: DDS Operation UNREGISTER_INSTANCE [Instance 1]", INFO);
|
||||
Log("W0: ACCEPTED", DEBUG);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := UNREGISTER_INSTANCE;
|
||||
dds.cc := cc;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
-- WRITER 0
|
||||
ind <= 0;
|
||||
start_dds;
|
||||
wait_on_dds;
|
||||
cc3 := cc;
|
||||
-- Stored CC: I1S1, I1S2, I1S3, 0
|
||||
wait_on_sig(dds_done);
|
||||
wait_on_idle;
|
||||
|
||||
Log("Current Time: 4s", INFO);
|
||||
check_time <= gen_duration(4,0);
|
||||
check_time <= gen_duration(4 sec);
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1");
|
||||
AffirmIf(status_id,(status(0) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1");
|
||||
AffirmIf(status_id,(status(1) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1");
|
||||
|
||||
Log("Current Time: 5s", INFO);
|
||||
check_time <= gen_duration(5,0);
|
||||
check_time <= gen_duration(5 sec);
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status and LIVELINESS_LOST_STATUS) = LIVELINESS_LOST_STATUS, "Expected: 1", "Received 0");
|
||||
AffirmIf(status_id,(status(0) and LIVELINESS_LOST_STATUS) = LIVELINESS_LOST_STATUS, "Expected: 1", "Received 0");
|
||||
AffirmIf(status_id,(status(1) and LIVELINESS_LOST_STATUS) = LIVELINESS_LOST_STATUS, "Expected: 1", "Received 0");
|
||||
|
||||
Log("W1: DDS Operation ASSERT_LIVELINESS", INFO);
|
||||
Log("W1: OK", DEBUG);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := ASSERT_LIVELINESS;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
dds.assertion := '1';
|
||||
-- WRITER 1
|
||||
ind <= 1;
|
||||
start_dds;
|
||||
wait_on_sig(dds_done);
|
||||
wait_on_idle;
|
||||
|
||||
Log("Current Time: 6s", INFO);
|
||||
check_time <= gen_duration(6,0);
|
||||
check_time <= gen_duration(6 sec);
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status and LIVELINESS_LOST_STATUS) = LIVELINESS_LOST_STATUS, "Expected: 1", "Received 0");
|
||||
AffirmIf(status_id,(status(0) and LIVELINESS_LOST_STATUS) = LIVELINESS_LOST_STATUS, "Expected: 1", "Received 0");
|
||||
AffirmIf(status_id,(status(1) and LIVELINESS_LOST_STATUS) = LIVELINESS_LOST_STATUS, "Expected: 1", "Received 0");
|
||||
|
||||
Log("DDS Operation GET_LIVELINESS_LOST_STATUS (Expected: count 3, change 2)", INFO);
|
||||
Log("W0: DDS Operation GET_LIVELINESS_LOST_STATUS (Expected: count 3, change 2)", INFO);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := GET_LIVELINESS_LOST_STATUS;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
dds.count := 3;
|
||||
dds.change := 2;
|
||||
-- WRITER 0
|
||||
ind <= 0;
|
||||
start_dds;
|
||||
wait_on_dds;
|
||||
|
||||
wait_on_idle;
|
||||
AffirmIf(status_id,(status and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1");
|
||||
|
||||
Log("Current Time: 6.5s", INFO);
|
||||
check_time <= gen_duration(6,500);
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
wait_on_sig(dds_done);
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1");
|
||||
AffirmIf(status_id,(status(0) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1");
|
||||
AffirmIf(status_id,(status(1) and LIVELINESS_LOST_STATUS) = LIVELINESS_LOST_STATUS, "Expected: 1", "Received 0");
|
||||
|
||||
Log("DDS Operation ASSERT_LIVELINESS (OK)", INFO);
|
||||
Log("W1: DDS Operation GET_LIVELINESS_LOST_STATUS (Expected: count 1, change 1)", INFO);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := GET_LIVELINESS_LOST_STATUS;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
dds.count := 1;
|
||||
dds.change := 1;
|
||||
-- WRITER 1
|
||||
ind <= 1;
|
||||
start_dds;
|
||||
wait_on_sig(dds_done);
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status(0) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1");
|
||||
AffirmIf(status_id,(status(1) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1");
|
||||
|
||||
Log("W0: DDS Operation ASSERT_LIVELINESS", INFO);
|
||||
Log("W0: OK", DEBUG);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := ASSERT_LIVELINESS;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
dds.assertion := '1';
|
||||
-- WRITER 0
|
||||
ind <= 0;
|
||||
start_dds;
|
||||
wait_on_dds;
|
||||
wait_on_sig(dds_done);
|
||||
wait_on_idle;
|
||||
|
||||
Log("Current Time: 7s", INFO);
|
||||
check_time <= gen_duration(7,0);
|
||||
Log("Current Time: 6.5s", INFO);
|
||||
check_time <= gen_duration(6.5 sec);
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1");
|
||||
AffirmIf(status_id,(status(0) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1");
|
||||
AffirmIf(status_id,(status(1) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1");
|
||||
|
||||
Log("W0: DDS Operation ASSERT_LIVELINESS", INFO);
|
||||
Log("W0: OK", DEBUG);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := ASSERT_LIVELINESS;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
dds.assertion := '1';
|
||||
-- WRITER 0
|
||||
ind <= 0;
|
||||
start_dds;
|
||||
wait_on_sig(dds_done);
|
||||
wait_on_idle;
|
||||
|
||||
Log("Current Time: 7s", INFO);
|
||||
check_time <= gen_duration(7 sec);
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status(0) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1");
|
||||
AffirmIf(status_id,(status(1) and LIVELINESS_LOST_STATUS) = LIVELINESS_LOST_STATUS, "Expected: 1", "Received 0");
|
||||
|
||||
Log("W1: DDS Operation GET_LIVELINESS_LOST_STATUS (Expected: count 1, change 1)", INFO);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := GET_LIVELINESS_LOST_STATUS;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
dds.count := 2;
|
||||
dds.change := 1;
|
||||
-- WRITER 1
|
||||
ind <= 1;
|
||||
start_dds;
|
||||
wait_on_sig(dds_done);
|
||||
wait_on_idle;
|
||||
|
||||
AffirmIf(status_id,(status(0) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1");
|
||||
AffirmIf(status_id,(status(1) and LIVELINESS_LOST_STATUS) /= LIVELINESS_LOST_STATUS, "Expected: 0", "Received 1");
|
||||
|
||||
wait_on_completion;
|
||||
TranscriptOpen(RESULTS_FILE, APPEND_MODE);
|
||||
@ -441,13 +565,6 @@ begin
|
||||
wait for 25 ns;
|
||||
end process;
|
||||
|
||||
alert_prc : process(all)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
-- TODO
|
||||
end if;
|
||||
end process;
|
||||
|
||||
dds_prc : process(all)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
@ -460,7 +577,7 @@ begin
|
||||
dds_done <= '1';
|
||||
end if;
|
||||
when START =>
|
||||
if (ack_dds = '1') then
|
||||
if (ack_dds(ind) = '1') then
|
||||
case (dds.opcode) is
|
||||
when GET_LIVELINESS_LOST_STATUS =>
|
||||
dds_stage <= DONE;
|
||||
@ -474,7 +591,7 @@ begin
|
||||
end case;
|
||||
end if;
|
||||
when PUSH =>
|
||||
if (ready_in_dds = '1') then
|
||||
if (ready_in_dds(ind) = '1') then
|
||||
dds_cnt <= dds_cnt + 1;
|
||||
if (dds_cnt = dds.cc.payload.length-1) then
|
||||
-- DEFAULT
|
||||
@ -482,11 +599,11 @@ begin
|
||||
end if;
|
||||
end if;
|
||||
when DONE =>
|
||||
if (done_dds = '1') then
|
||||
if (done_dds(ind) = '1') then
|
||||
if (dds.opcode = REGISTER_INSTANCE or dds.opcode = LOOKUP_INSTANCE) then
|
||||
AffirmIfEqual(ih_id, to_unsigned(instance_handle_out_dds), to_unsigned(dds.cc.instance));
|
||||
AffirmIfEqual(ih_id, to_unsigned(instance_handle_out_dds(ind)), to_unsigned(dds.cc.instance));
|
||||
else
|
||||
AffirmIfEqual(ret_id, return_code_dds, dds.ret_code);
|
||||
AffirmIfEqual(ret_id, return_code_dds(ind), dds.ret_code);
|
||||
case (dds.opcode) is
|
||||
when GET_LIVELINESS_LOST_STATUS =>
|
||||
if (dds.ret_code = RETCODE_OK) then
|
||||
@ -496,7 +613,7 @@ begin
|
||||
dds_stage <= IDLE;
|
||||
end if;
|
||||
when ASSERT_LIVELINESS =>
|
||||
AffirmIfEqual(assert_id, liveliness_assertion, dds.assertion);
|
||||
AffirmIfEqual(assert_id, liveliness_assertion(ind), dds.assertion);
|
||||
dds_stage <= IDLE;
|
||||
when others =>
|
||||
dds_stage <= IDLE;
|
||||
@ -504,14 +621,14 @@ begin
|
||||
end if;
|
||||
end if;
|
||||
when CHECK_LIVELINESS =>
|
||||
if (valid_out_dds = '1') then
|
||||
if (valid_out_dds(ind) = '1') then
|
||||
dds_cnt <= dds_cnt + 1;
|
||||
case (dds_cnt) is
|
||||
when 0 =>
|
||||
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(to_unsigned(dds.count,CDR_LONG_WIDTH)));
|
||||
AffirmIfEqual(data_id, data_out_dds(ind), std_logic_vector(to_unsigned(dds.count,CDR_LONG_WIDTH)));
|
||||
when 1 =>
|
||||
AffirmIfEqual(data_id, data_out_dds, std_logic_vector(to_unsigned(dds.change,CDR_LONG_WIDTH)));
|
||||
AlertIf(data_id, last_word_out_dds /= '1', "Last Word Signal not pulled High", ERROR);
|
||||
AffirmIfEqual(data_id, data_out_dds(ind), std_logic_vector(to_unsigned(dds.change,CDR_LONG_WIDTH)));
|
||||
AlertIf(data_id, last_word_out_dds(ind) /= '1', "Last Word Signal not pulled High", ERROR);
|
||||
dds_stage <= IDLE;
|
||||
when others =>
|
||||
null;
|
||||
@ -521,27 +638,27 @@ begin
|
||||
end if;
|
||||
|
||||
-- DEFAULT
|
||||
start_dds <= '0';
|
||||
opcode_dds <= NOP;
|
||||
valid_in_dds <= '0';
|
||||
last_word_in_dds <= '0';
|
||||
data_in_dds <= (others => '0');
|
||||
instance_handle_in_dds <= HANDLE_NIL;
|
||||
source_ts_dds <= TIME_INVALID;
|
||||
ready_out_dds <= '0';
|
||||
start_dds <= (others => '0');
|
||||
opcode_dds <= (others => NOP);
|
||||
valid_in_dds <= (others => '0');
|
||||
last_word_in_dds <= (others => '0');
|
||||
data_in_dds <= (others => (others => '0'));
|
||||
instance_handle_in_dds <= (others => HANDLE_NIL);
|
||||
source_ts_dds <= (others => TIME_INVALID);
|
||||
ready_out_dds <= (others => '0');
|
||||
|
||||
case (dds_stage) is
|
||||
when START =>
|
||||
start_dds <= '1';
|
||||
opcode_dds <= dds.opcode;
|
||||
instance_handle_in_dds <= dds.cc.instance;
|
||||
source_ts_dds <= dds.cc.src_timestamp;
|
||||
start_dds(ind) <= '1';
|
||||
opcode_dds(ind) <= dds.opcode;
|
||||
instance_handle_in_dds(ind) <= dds.cc.instance;
|
||||
source_ts_dds(ind) <= dds.cc.src_timestamp;
|
||||
when PUSH =>
|
||||
valid_in_dds <= '1';
|
||||
data_in_dds <= dds.cc.payload.data(dds_cnt);
|
||||
last_word_in_dds <= dds.cc.payload.last(dds_cnt);
|
||||
valid_in_dds(ind) <= '1';
|
||||
data_in_dds(ind) <= dds.cc.payload.data(dds_cnt);
|
||||
last_word_in_dds(ind) <= dds.cc.payload.last(dds_cnt);
|
||||
when CHECK_LIVELINESS =>
|
||||
ready_out_dds <= '1';
|
||||
ready_out_dds(ind) <= '1';
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
@ -559,39 +676,36 @@ begin
|
||||
rtps_done <= '1';
|
||||
end if;
|
||||
when START =>
|
||||
if (ack_rtps = '1') then
|
||||
if (ack_rtps(ind) = '1') then
|
||||
rtps_stage <= DONE;
|
||||
end if;
|
||||
when DONE =>
|
||||
if (done_rtps = '1') then
|
||||
if (done_rtps(ind) = '1') then
|
||||
-- DEFAULT
|
||||
rtps_stage <= IDLE;
|
||||
|
||||
AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code));
|
||||
AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps(ind)), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code));
|
||||
case (rtps.opcode) is
|
||||
when GET_CACHE_CHANGE =>
|
||||
if (rtps.ret_code = OK) then
|
||||
AffirmIfEqual(inst_id, cc_instance_handle(0), rtps.cc.instance(0));
|
||||
AffirmIfEqual(inst_id, cc_instance_handle(1), rtps.cc.instance(1));
|
||||
AffirmIfEqual(inst_id, cc_instance_handle(2), rtps.cc.instance(2));
|
||||
AffirmIfEqual(inst_id, cc_instance_handle(3), rtps.cc.instance(3));
|
||||
AffirmIfEqual(kind_id, CACHE_CHANGE_KIND_TYPE'pos(cc_kind), CACHE_CHANGE_KIND_TYPE'pos(rtps.cc.kind));
|
||||
AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr));
|
||||
AffirmIfEqual(ts_id, to_unsigned(cc_source_timestamp), to_unsigned(rtps.cc.src_timestamp));
|
||||
AffirmIfEqual(inst_id, to_unsigned(cc_instance_handle(ind)), to_unsigned(rtps.cc.instance));
|
||||
AffirmIfEqual(kind_id, CACHE_CHANGE_KIND_TYPE'pos(cc_kind(ind)), CACHE_CHANGE_KIND_TYPE'pos(rtps.cc.kind));
|
||||
AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr(ind)), to_unsigned(rtps.cc.seq_nr));
|
||||
AffirmIfEqual(ts_id, to_unsigned(cc_source_timestamp(ind)), to_unsigned(rtps.cc.src_timestamp));
|
||||
rtps_stage <= CHECK;
|
||||
rtps_cnt <= 0;
|
||||
end if;
|
||||
when GET_MIN_SN =>
|
||||
AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr));
|
||||
AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr(ind)), to_unsigned(rtps.cc.seq_nr));
|
||||
when GET_MAX_SN =>
|
||||
AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr));
|
||||
AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr(ind)), to_unsigned(rtps.cc.seq_nr));
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
when CHECK =>
|
||||
if (valid_out_rtps = '1') then
|
||||
AffirmIfEqual(data_id, last_word_out_rtps & data_out_rtps, rtps.cc.payload.last(rtps_cnt) & rtps.cc.payload.data(rtps_cnt));
|
||||
if (valid_out_rtps(ind) = '1') then
|
||||
AffirmIfEqual(data_id, last_word_out_rtps(ind) & data_out_rtps(ind), rtps.cc.payload.last(rtps_cnt) & rtps.cc.payload.data(rtps_cnt));
|
||||
rtps_cnt <= rtps_cnt + 1;
|
||||
if (rtps_cnt = rtps.cc.payload.length-1) then
|
||||
rtps_stage <= IDLE;
|
||||
@ -601,28 +715,28 @@ begin
|
||||
end if;
|
||||
|
||||
-- DEFAULT
|
||||
start_rtps <= '0';
|
||||
opcode_rtps <= NOP;
|
||||
seq_nr_rtps <= SEQUENCENUMBER_UNKNOWN;
|
||||
get_data_rtps <= '0';
|
||||
ready_out_rtps <= '0';
|
||||
start_rtps <= (others => '0');
|
||||
opcode_rtps <= (others => NOP);
|
||||
seq_nr_rtps <= (others => SEQUENCENUMBER_UNKNOWN);
|
||||
get_data_rtps <= (others => '0');
|
||||
ready_out_rtps <= (others => '0');
|
||||
|
||||
case (rtps_stage) is
|
||||
when START =>
|
||||
start_rtps <= '1';
|
||||
opcode_rtps <= rtps.opcode;
|
||||
seq_nr_rtps <= rtps.cc.seq_nr;
|
||||
start_rtps(ind) <= '1';
|
||||
opcode_rtps(ind) <= rtps.opcode;
|
||||
seq_nr_rtps(ind) <= rtps.cc.seq_nr;
|
||||
when DONE =>
|
||||
if (done_rtps = '1') then
|
||||
if (done_rtps(ind) = '1') then
|
||||
case (rtps.opcode) is
|
||||
when GET_CACHE_CHANGE =>
|
||||
get_data_rtps <= '1';
|
||||
get_data_rtps(ind) <= '1';
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
when CHECK =>
|
||||
ready_out_rtps <= '1';
|
||||
ready_out_rtps(ind) <= '1';
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
@ -12,13 +12,41 @@ use work.rtps_test_package.all;
|
||||
|
||||
-- This testbench tests the Lifespan Handling of the DDS Writer.
|
||||
|
||||
entity L0_dds_writer_test5_afk is
|
||||
entity L0_dds_writer_test5 is
|
||||
end entity;
|
||||
|
||||
architecture testbench of L0_dds_writer_test5_afk is
|
||||
architecture testbench of L0_dds_writer_test5 is
|
||||
|
||||
-- *CONSTANT DECLARATION*
|
||||
constant MAX_REMOTE_ENDPOINTS : natural := 3;
|
||||
constant NUM_WRITERS : natural := 2;
|
||||
|
||||
impure function gen_test_config return CONFIG_ARRAY_TYPE is
|
||||
variable ret : CONFIG_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => DEFAULT_WRITER_CONFIG);
|
||||
begin
|
||||
-- aik
|
||||
ret(0).HISTORY_QOS := KEEP_ALL_HISTORY_QOS;
|
||||
ret(0).DEADLINE_QOS := DURATION_INFINITE;
|
||||
ret(0).LIFESPAN_QOS := gen_duration(2 sec);
|
||||
ret(0).LEASE_DURATION := DURATION_INFINITE;
|
||||
ret(0).WITH_KEY := TRUE;
|
||||
ret(0).MAX_SAMPLES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH));
|
||||
ret(0).MAX_INSTANCES := std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH));
|
||||
ret(0).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH));
|
||||
ret(0).MAX_PAYLOAD_SIZE := 40;
|
||||
-- ain
|
||||
ret(1).HISTORY_QOS := KEEP_ALL_HISTORY_QOS;
|
||||
ret(1).DEADLINE_QOS := DURATION_INFINITE;
|
||||
ret(1).LIFESPAN_QOS := gen_duration(3 sec);
|
||||
ret(1).LEASE_DURATION := DURATION_INFINITE;
|
||||
ret(1).WITH_KEY := FALSE;
|
||||
ret(1).MAX_SAMPLES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH));
|
||||
ret(1).MAX_INSTANCES := std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH));
|
||||
ret(1).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH));
|
||||
ret(1).MAX_PAYLOAD_SIZE := 40;
|
||||
return ret;
|
||||
end function;
|
||||
constant TEST_CONFIG : CONFIG_ARRAY_TYPE := gen_test_config;
|
||||
|
||||
-- *TYPE DECLARATION*
|
||||
type DDS_STAGE_TYPE is (IDLE, START, PUSH, DONE);
|
||||
@ -28,22 +56,23 @@ architecture testbench of L0_dds_writer_test5_afk is
|
||||
signal clk : std_logic := '0';
|
||||
signal reset : std_logic := '1';
|
||||
signal check_time : TIME_TYPE := TIME_ZERO;
|
||||
signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds : std_logic := '0';
|
||||
signal opcode_rtps : HISTORY_CACHE_OPCODE_TYPE := NOP;
|
||||
signal opcode_dds : DDS_WRITER_OPCODE_TYPE := NOP;
|
||||
signal ret_rtps : HISTORY_CACHE_RESPONSE_TYPE := ERROR;
|
||||
signal seq_nr_rtps, cc_seq_nr : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN;
|
||||
signal ready_out_rtps, valid_out_rtps, last_word_out_rtps : std_logic := '0';
|
||||
signal ready_in_dds, ready_out_dds, valid_in_dds, valid_out_dds, last_word_in_dds, last_word_out_dds : std_logic := '0';
|
||||
signal data_out_rtps, data_in_dds, data_out_dds : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
|
||||
signal get_data_rtps, liveliness_assertion, data_available : std_logic := '0';
|
||||
signal cc_source_timestamp, source_ts_dds : TIME_TYPE := TIME_INVALID;
|
||||
signal cc_kind : CACHE_CHANGE_KIND_TYPE := ALIVE;
|
||||
signal cc_instance_handle, instance_handle_in_dds, instance_handle_out_dds : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
|
||||
signal max_wait_dds : DURATION_TYPE := DURATION_INFINITE;
|
||||
signal return_code_dds : std_logic_vector(RETURN_CODE_WIDTH-1 downto 0) := (others => '0');
|
||||
signal status : std_logic_vector(STATUS_KIND_WIDTH-1 downto 0) := (others => '0');
|
||||
signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds, w_map : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0');
|
||||
signal opcode_rtps : HISTORY_CACHE_OPCODE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => NOP);
|
||||
signal opcode_dds : DDS_WRITER_OPCODE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => NOP);
|
||||
signal ret_rtps : HISTORY_CACHE_RESPONSE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => ERROR);
|
||||
signal seq_nr_rtps, cc_seq_nr : SEQUENCENUMBER_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => SEQUENCENUMBER_UNKNOWN);
|
||||
signal ready_out_rtps, valid_out_rtps, last_word_out_rtps : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0');
|
||||
signal ready_in_dds, ready_out_dds, valid_in_dds, valid_out_dds, last_word_in_dds, last_word_out_dds : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0');
|
||||
signal data_out_rtps, data_in_dds, data_out_dds : WORD_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => (others => '0'));
|
||||
signal get_data_rtps, liveliness_assertion, data_available : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0');
|
||||
signal cc_source_timestamp, source_ts_dds : TIME_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => TIME_INVALID);
|
||||
signal cc_kind : CACHE_CHANGE_KIND_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => ALIVE);
|
||||
signal cc_instance_handle, instance_handle_in_dds, instance_handle_out_dds : INSTANCE_HANDLE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => HANDLE_NIL);
|
||||
signal max_wait_dds : DURATION_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => DURATION_INFINITE);
|
||||
signal return_code_dds : RETURN_CODE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => (others => '0'));
|
||||
signal status : STATUS_KIND_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => (others => '0'));
|
||||
|
||||
signal ind : natural := 0;
|
||||
signal dds_start, dds_done, rtps_start, rtps_done : std_logic := '0';
|
||||
signal dds_cnt, rtps_cnt : natural := 0;
|
||||
signal dds_stage : DDS_STAGE_TYPE := IDLE;
|
||||
@ -71,20 +100,20 @@ architecture testbench of L0_dds_writer_test5_afk is
|
||||
return ret;
|
||||
end function;
|
||||
|
||||
procedure wait_on_sig(signal sig : std_logic) is
|
||||
begin
|
||||
if (sig /= '1') then
|
||||
wait on sig until sig = '1';
|
||||
end if;
|
||||
end procedure;
|
||||
|
||||
begin
|
||||
|
||||
-- Unit Under Test
|
||||
uut : entity work.dds_writer(arch)
|
||||
generic map(
|
||||
HISTORY_QOS => KEEP_ALL_HISTORY_QOS,
|
||||
DEADLINE_QOS => DURATION_INFINITE,
|
||||
LIFESPAN_QOS => gen_duration(2,0),
|
||||
LEASE_DURATION => DURATION_INFINITE,
|
||||
WITH_KEY => TRUE,
|
||||
MAX_SAMPLES => std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH)),
|
||||
MAX_INSTANCES => std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)),
|
||||
MAX_SAMPLES_PER_INSTANCE => std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH)),
|
||||
PAYLOAD_FRAME_SIZE => 11
|
||||
NUM_WRITERS => NUM_WRITERS,
|
||||
CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(TEST_CONFIG)
|
||||
)
|
||||
port map (
|
||||
clk => clk,
|
||||
@ -178,20 +207,6 @@ begin
|
||||
wait until rising_edge(clk);
|
||||
end procedure;
|
||||
|
||||
procedure wait_on_dds is
|
||||
begin
|
||||
if (dds_done /= '1') then
|
||||
wait until dds_done = '1';
|
||||
end if;
|
||||
end procedure;
|
||||
|
||||
procedure wait_on_rtps is
|
||||
begin
|
||||
if (rtps_done /= '1') then
|
||||
wait until rtps_done = '1';
|
||||
end if;
|
||||
end procedure;
|
||||
|
||||
procedure wait_on_completion is
|
||||
begin
|
||||
if (rtps_done /= '1' or dds_done /= '1') then
|
||||
@ -202,21 +217,23 @@ begin
|
||||
-- NOTE: This procedure waits until the idle_sig is high for at least
|
||||
-- two consecutive clock cycles.
|
||||
procedure wait_on_idle is
|
||||
variable first : boolean := TRUE;
|
||||
begin
|
||||
loop
|
||||
if (idle_sig /= '1') then
|
||||
wait until idle_sig = '1';
|
||||
else
|
||||
elsif (not first) then
|
||||
exit;
|
||||
end if;
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
first := FALSE;
|
||||
end loop;
|
||||
end procedure;
|
||||
|
||||
begin
|
||||
|
||||
SetAlertLogName("L0_dds_writer_test5_afk - (KEEP ALL, Infinite Lifespan, Keyed) - Lifespan Handling");
|
||||
SetAlertLogName("L0_dds_writer_test5 - Lifespan Handling");
|
||||
SetAlertEnable(FAILURE, TRUE);
|
||||
SetAlertEnable(ERROR, TRUE);
|
||||
SetAlertEnable(WARNING, TRUE);
|
||||
@ -248,7 +265,6 @@ begin
|
||||
wait until rising_edge(clk);
|
||||
reset <= '0';
|
||||
wait_on_idle;
|
||||
-- Stored CC: 0, 0, 0, 0
|
||||
|
||||
cc := DEFAULT_CACHE_CHANGE;
|
||||
cc.serialized_key := FALSE;
|
||||
@ -257,16 +273,22 @@ begin
|
||||
cc.payload := gen_payload(kh1,10);
|
||||
cc.seq_nr := gen_sn(1);
|
||||
|
||||
Log("DDS Operation WRITE [Instance 1, HANDLE_NIL, Aligned Payload] (ACCEPTED)", INFO);
|
||||
Log("W0,W1: DDS Operation WRITE [Instance 1, HANDLE_NIL, Aligned Payload] (ACCEPTED)", INFO);
|
||||
Log("W0,W1: ACCEPTED", DEBUG);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := WRITE;
|
||||
dds.cc := cc;
|
||||
dds.cc.instance:= HANDLE_NIL;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
-- WRITER 0
|
||||
ind <= 0;
|
||||
start_dds;
|
||||
wait_on_dds;
|
||||
cc1 := cc;
|
||||
-- Stored CC: I1S1, 0, 0, 0
|
||||
wait_on_sig(dds_done);
|
||||
-- WRITER 1
|
||||
ind <= 1;
|
||||
start_dds;
|
||||
wait_on_sig(dds_done);
|
||||
wait_on_idle;
|
||||
|
||||
cc := DEFAULT_CACHE_CHANGE;
|
||||
cc.serialized_key := FALSE;
|
||||
@ -275,19 +297,25 @@ begin
|
||||
cc.payload := gen_payload(kh2,10);
|
||||
cc.seq_nr := gen_sn(2);
|
||||
|
||||
Log("DDS Operation WRITE [Instance 2, HANDLE_NIL, Aligned Payload] (ACCEPTED)", INFO);
|
||||
Log("W0,W1: DDS Operation WRITE [Instance 2, HANDLE_NIL, Aligned Payload]", INFO);
|
||||
Log("W0,W1: ACCEPTED", DEBUG);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := WRITE;
|
||||
dds.cc := cc;
|
||||
dds.cc.instance:= HANDLE_NIL;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
-- WRITER 0
|
||||
ind <= 0;
|
||||
start_dds;
|
||||
wait_on_dds;
|
||||
cc2 := cc;
|
||||
-- Stored CC: I1S1, I2S2, 0, 0
|
||||
wait_on_sig(dds_done);
|
||||
-- WRITER 1
|
||||
ind <= 1;
|
||||
start_dds;
|
||||
wait_on_sig(dds_done);
|
||||
wait_on_idle;
|
||||
|
||||
Log("Current Time: 1s", INFO);
|
||||
check_time <= gen_duration(1,0);
|
||||
check_time <= gen_duration(1 sec);
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
wait_on_idle;
|
||||
@ -299,16 +327,22 @@ begin
|
||||
cc.payload := gen_payload(kh1,10);
|
||||
cc.seq_nr := gen_sn(3);
|
||||
|
||||
Log("DDS Operation WRITE [Instance 1, HANDLE_NIL, Aligned Payload] (ACCEPTED)", INFO);
|
||||
Log("W0,W1: DDS Operation WRITE [Instance 1, HANDLE_NIL, Aligned Payload]", INFO);
|
||||
Log("W0,W1: ACCEPTED", DEBUG);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := WRITE;
|
||||
dds.cc := cc;
|
||||
dds.cc.instance:= HANDLE_NIL;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
-- WRITER 0
|
||||
ind <= 0;
|
||||
start_dds;
|
||||
wait_on_dds;
|
||||
cc3 := cc;
|
||||
-- Stored CC: I1S1, I2S2, I1S3, 0
|
||||
wait_on_sig(dds_done);
|
||||
-- WRITER 1
|
||||
ind <= 1;
|
||||
start_dds;
|
||||
wait_on_sig(dds_done);
|
||||
wait_on_idle;
|
||||
|
||||
cc := DEFAULT_CACHE_CHANGE;
|
||||
cc.serialized_key := FALSE;
|
||||
@ -317,14 +351,24 @@ begin
|
||||
cc.payload := gen_payload(kh1,10);
|
||||
cc.seq_nr := gen_sn(4);
|
||||
|
||||
Log("DDS Operation WRITE [Instance 1, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_SAMPLES_PER_INSTANCE exceeded)", INFO);
|
||||
Log("W0,W1: DDS Operation WRITE [Instance 1, HANDLE_NIL, Aligned Payload]", INFO);
|
||||
Log("W0: REJECTED [MAX_SAMPLES_PER_INSTANCE exceeded]", DEBUG);
|
||||
Log("W1: ACCEPTED", DEBUG);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := WRITE;
|
||||
dds.cc := cc;
|
||||
dds.cc.instance:= HANDLE_NIL;
|
||||
-- WRITER 0
|
||||
dds.ret_code := RETCODE_OUT_OF_RESOURCES;
|
||||
ind <= 0;
|
||||
start_dds;
|
||||
wait_on_dds;
|
||||
wait_on_sig(dds_done);
|
||||
-- WRITER 1
|
||||
dds.ret_code := RETCODE_OK;
|
||||
ind <= 1;
|
||||
start_dds;
|
||||
wait_on_sig(dds_done);
|
||||
wait_on_idle;
|
||||
|
||||
cc := DEFAULT_CACHE_CHANGE;
|
||||
cc.serialized_key := TRUE;
|
||||
@ -333,38 +377,66 @@ begin
|
||||
cc.payload := gen_payload(kh2,5);
|
||||
cc.seq_nr := gen_sn(4);
|
||||
|
||||
Log("DDS Operation UNREGISTER_INSTANCE [Instance 2] (ACCEPTED)", INFO);
|
||||
Log("W0,W1: DDS Operation UNREGISTER_INSTANCE [Instance 2]", INFO);
|
||||
Log("W0: ACCEPTED", DEBUG);
|
||||
Log("W1: REJECTED [MAX_SAMPLES exceeded]", DEBUG);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := UNREGISTER_INSTANCE;
|
||||
dds.cc := cc;
|
||||
-- WRITER 0
|
||||
dds.ret_code := RETCODE_OK;
|
||||
ind <= 0;
|
||||
start_dds;
|
||||
wait_on_dds;
|
||||
cc4 := cc;
|
||||
-- Stored CC: I1S1, I2S2, I1S3, I2S4
|
||||
wait_on_sig(dds_done);
|
||||
-- WRITER 1
|
||||
dds.cc.instance := HANDLE_NIL;
|
||||
dds.ret_code := RETCODE_OUT_OF_RESOURCES;
|
||||
ind <= 1;
|
||||
start_dds;
|
||||
wait_on_sig(dds_done);
|
||||
wait_on_idle;
|
||||
|
||||
Log("Current Time: 2s", INFO);
|
||||
check_time <= gen_duration(2,0);
|
||||
check_time <= gen_duration(2 sec);
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
wait_on_idle;
|
||||
-- Stored CC: 0, 0, I1S3, I2S4
|
||||
|
||||
-- VALIDATE STATE
|
||||
|
||||
Log("RTPS Operation GET_MIN_SN (Expected SN 3)", INFO);
|
||||
Log("W0,W1: RTPS Operation GET_MIN_SN", INFO);
|
||||
Log("W0: Expected SN 3", DEBUG);
|
||||
Log("W1: Expected SN 1", DEBUG);
|
||||
rtps := DEFAULT_RTPS_WRITER_TEST;
|
||||
rtps.opcode := GET_MIN_SN;
|
||||
-- WRITER 0
|
||||
rtps.cc.seq_nr := gen_sn(3);
|
||||
ind <= 0;
|
||||
start_rtps;
|
||||
wait_on_rtps;
|
||||
wait_on_sig(rtps_done);
|
||||
-- WRITER 1
|
||||
rtps.cc.seq_nr := gen_sn(1);
|
||||
ind <= 1;
|
||||
start_rtps;
|
||||
wait_on_sig(rtps_done);
|
||||
wait_on_idle;
|
||||
|
||||
Log("RTPS Operation GET_MAX_SN (Expected SN 4)", INFO);
|
||||
Log("W0,W1: RTPS Operation GET_MAX_SN", INFO);
|
||||
Log("W0: Expected SN 4", DEBUG);
|
||||
Log("W1: Expected SN 4", DEBUG);
|
||||
rtps := DEFAULT_RTPS_WRITER_TEST;
|
||||
rtps.opcode := GET_MAX_SN;
|
||||
-- WRITER 0
|
||||
rtps.cc.seq_nr := gen_sn(4);
|
||||
ind <= 0;
|
||||
start_rtps;
|
||||
wait_on_rtps;
|
||||
wait_on_sig(rtps_done);
|
||||
-- WRITER 1
|
||||
rtps.cc.seq_nr := gen_sn(4);
|
||||
ind <= 1;
|
||||
start_rtps;
|
||||
wait_on_sig(rtps_done);
|
||||
wait_on_idle;
|
||||
|
||||
cc := DEFAULT_CACHE_CHANGE;
|
||||
cc.serialized_key := FALSE;
|
||||
@ -373,16 +445,24 @@ begin
|
||||
cc.payload := gen_payload(kh1,10);
|
||||
cc.seq_nr := gen_sn(5);
|
||||
|
||||
Log("DDS Operation WRITE [Instance 1, HANDLE_NIL, Aligned Payload] (ACCEPTED)", INFO);
|
||||
Log("W0,W1: DDS Operation WRITE [Instance 1, HANDLE_NIL, Aligned Payload]", INFO);
|
||||
Log("W0: ACCEPTED", DEBUG);
|
||||
Log("W1: REJECTED [MAX_SAMPLES exceeded]", DEBUG);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := WRITE;
|
||||
dds.cc := cc;
|
||||
dds.cc.instance:= HANDLE_NIL;
|
||||
-- WRITER 0
|
||||
dds.ret_code := RETCODE_OK;
|
||||
ind <= 0;
|
||||
start_dds;
|
||||
wait_on_dds;
|
||||
cc1 := cc;
|
||||
-- Stored CC: I1S5, 0, I1S3, I2S4
|
||||
wait_on_sig(dds_done);
|
||||
-- WRITER 1
|
||||
dds.ret_code := RETCODE_OUT_OF_RESOURCES;
|
||||
ind <= 1;
|
||||
start_dds;
|
||||
wait_on_sig(dds_done);
|
||||
wait_on_idle;
|
||||
|
||||
cc := DEFAULT_CACHE_CHANGE;
|
||||
cc.serialized_key := FALSE;
|
||||
@ -391,37 +471,66 @@ begin
|
||||
cc.payload := gen_payload(kh3,10);
|
||||
cc.seq_nr := gen_sn(6);
|
||||
|
||||
Log("DDS Operation WRITE [Instance 3, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)", INFO);
|
||||
Log("W0,W1: DDS Operation WRITE [Instance 3, HANDLE_NIL, Aligned Payload]", INFO);
|
||||
Log("W0: REJECTED [MAX_INSTANCES exceeded]", DEBUG);
|
||||
Log("W1: REJECTED [MAX_SAMPLES exceeded]", DEBUG);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := WRITE;
|
||||
dds.cc := cc;
|
||||
dds.cc.instance:= HANDLE_NIL;
|
||||
-- WRITER 0
|
||||
dds.ret_code := RETCODE_OUT_OF_RESOURCES;
|
||||
ind <= 0;
|
||||
start_dds;
|
||||
wait_on_dds;
|
||||
wait_on_sig(dds_done);
|
||||
-- WRITER 1
|
||||
dds.ret_code := RETCODE_OUT_OF_RESOURCES;
|
||||
ind <= 1;
|
||||
start_dds;
|
||||
wait_on_sig(dds_done);
|
||||
wait_on_idle;
|
||||
|
||||
Log("Current Time: 3s", INFO);
|
||||
check_time <= gen_duration(3,0);
|
||||
check_time <= gen_duration(3 sec);
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
wait_on_idle;
|
||||
-- Stored CC: I1S5, 0, 0, 0
|
||||
|
||||
-- VALIDATE STATE
|
||||
|
||||
Log("RTPS Operation GET_MIN_SN (Expected SN 5)", INFO);
|
||||
Log("W0,W1: RTPS Operation GET_MIN_SN", INFO);
|
||||
Log("W0: Expected SN 5", DEBUG);
|
||||
Log("W1: Expected SN 3", DEBUG);
|
||||
rtps := DEFAULT_RTPS_WRITER_TEST;
|
||||
rtps.opcode := GET_MIN_SN;
|
||||
-- WRITER 0
|
||||
rtps.cc.seq_nr := gen_sn(5);
|
||||
ind <= 0;
|
||||
start_rtps;
|
||||
wait_on_rtps;
|
||||
wait_on_sig(rtps_done);
|
||||
-- WRITER 1
|
||||
rtps.cc.seq_nr := gen_sn(3);
|
||||
ind <= 1;
|
||||
start_rtps;
|
||||
wait_on_sig(rtps_done);
|
||||
wait_on_idle;
|
||||
|
||||
Log("RTPS Operation GET_MAX_SN (Expected SN 5)", INFO);
|
||||
Log("W0,W1: RTPS Operation GET_MAX_SN", INFO);
|
||||
Log("W0: Expected SN 5", DEBUG);
|
||||
Log("W1: Expected SN 4", DEBUG);
|
||||
rtps := DEFAULT_RTPS_WRITER_TEST;
|
||||
rtps.opcode := GET_MAX_SN;
|
||||
-- WRITER 0
|
||||
rtps.cc.seq_nr := gen_sn(5);
|
||||
ind <= 0;
|
||||
start_rtps;
|
||||
wait_on_rtps;
|
||||
wait_on_sig(rtps_done);
|
||||
-- WRITER 1
|
||||
rtps.cc.seq_nr := gen_sn(4);
|
||||
ind <= 1;
|
||||
start_rtps;
|
||||
wait_on_sig(rtps_done);
|
||||
wait_on_idle;
|
||||
|
||||
cc := DEFAULT_CACHE_CHANGE;
|
||||
cc.serialized_key := FALSE;
|
||||
@ -430,16 +539,22 @@ begin
|
||||
cc.payload := gen_payload(kh3,10);
|
||||
cc.seq_nr := gen_sn(6);
|
||||
|
||||
Log("DDS Operation WRITE [Instance 3, HANDLE_NIL, Aligned Payload] (ACCEPTED)", INFO);
|
||||
Log("W0,W1: DDS Operation WRITE [Instance 3, HANDLE_NIL, Aligned Payload]", INFO);
|
||||
Log("W0,W1: ACCEPTED", DEBUG);
|
||||
dds := DEFAULT_DDS_WRITER_TEST;
|
||||
dds.opcode := WRITE;
|
||||
dds.cc := cc;
|
||||
dds.cc.instance:= HANDLE_NIL;
|
||||
dds.ret_code := RETCODE_OK;
|
||||
-- WRITER 0
|
||||
ind <= 0;
|
||||
start_dds;
|
||||
wait_on_dds;
|
||||
cc2 := cc;
|
||||
-- Stored CC: I1S5, I3S6, 0, 0
|
||||
wait_on_sig(dds_done);
|
||||
-- WRITER 1
|
||||
ind <= 1;
|
||||
start_dds;
|
||||
wait_on_sig(dds_done);
|
||||
wait_on_idle;
|
||||
|
||||
wait_on_completion;
|
||||
TranscriptOpen(RESULTS_FILE, APPEND_MODE);
|
||||
@ -458,13 +573,6 @@ begin
|
||||
wait for 25 ns;
|
||||
end process;
|
||||
|
||||
alert_prc : process(all)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
-- TODO
|
||||
end if;
|
||||
end process;
|
||||
|
||||
dds_prc : process(all)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
@ -477,15 +585,12 @@ begin
|
||||
dds_done <= '1';
|
||||
end if;
|
||||
when START =>
|
||||
if (ack_dds = '1') then
|
||||
case (dds.opcode) is
|
||||
when others =>
|
||||
dds_stage <= PUSH;
|
||||
dds_cnt <= 0;
|
||||
end case;
|
||||
if (ack_dds(ind) = '1') then
|
||||
dds_stage <= PUSH;
|
||||
dds_cnt <= 0;
|
||||
end if;
|
||||
when PUSH =>
|
||||
if (ready_in_dds = '1') then
|
||||
if (ready_in_dds(ind) = '1') then
|
||||
dds_cnt <= dds_cnt + 1;
|
||||
if (dds_cnt = dds.cc.payload.length-1) then
|
||||
-- DEFAULT
|
||||
@ -493,11 +598,11 @@ begin
|
||||
end if;
|
||||
end if;
|
||||
when DONE =>
|
||||
if (done_dds = '1') then
|
||||
if (done_dds(ind) = '1') then
|
||||
if (dds.opcode = REGISTER_INSTANCE or dds.opcode = LOOKUP_INSTANCE) then
|
||||
AffirmIfEqual(ih_id, to_unsigned(instance_handle_out_dds), to_unsigned(dds.cc.instance));
|
||||
AffirmIfEqual(ih_id, to_unsigned(instance_handle_out_dds(ind)), to_unsigned(dds.cc.instance));
|
||||
else
|
||||
AffirmIfEqual(ret_id, return_code_dds, dds.ret_code);
|
||||
AffirmIfEqual(ret_id, return_code_dds(ind), dds.ret_code);
|
||||
end if;
|
||||
dds_stage <= IDLE;
|
||||
end if;
|
||||
@ -505,25 +610,25 @@ begin
|
||||
end if;
|
||||
|
||||
-- DEFAULT
|
||||
start_dds <= '0';
|
||||
opcode_dds <= NOP;
|
||||
valid_in_dds <= '0';
|
||||
last_word_in_dds <= '0';
|
||||
data_in_dds <= (others => '0');
|
||||
instance_handle_in_dds <= HANDLE_NIL;
|
||||
source_ts_dds <= TIME_INVALID;
|
||||
ready_out_dds <= '0';
|
||||
start_dds <= (others => '0');
|
||||
opcode_dds <= (others => NOP);
|
||||
valid_in_dds <= (others => '0');
|
||||
last_word_in_dds <= (others => '0');
|
||||
data_in_dds <= (others => (others => '0'));
|
||||
instance_handle_in_dds <= (others => HANDLE_NIL);
|
||||
source_ts_dds <= (others => TIME_INVALID);
|
||||
ready_out_dds <= (others => '0');
|
||||
|
||||
case (dds_stage) is
|
||||
when START =>
|
||||
start_dds <= '1';
|
||||
opcode_dds <= dds.opcode;
|
||||
instance_handle_in_dds <= dds.cc.instance;
|
||||
source_ts_dds <= dds.cc.src_timestamp;
|
||||
start_dds(ind) <= '1';
|
||||
opcode_dds(ind) <= dds.opcode;
|
||||
instance_handle_in_dds(ind) <= dds.cc.instance;
|
||||
source_ts_dds(ind) <= dds.cc.src_timestamp;
|
||||
when PUSH =>
|
||||
valid_in_dds <= '1';
|
||||
data_in_dds <= dds.cc.payload.data(dds_cnt);
|
||||
last_word_in_dds <= dds.cc.payload.last(dds_cnt);
|
||||
valid_in_dds(ind) <= '1';
|
||||
data_in_dds(ind) <= dds.cc.payload.data(dds_cnt);
|
||||
last_word_in_dds(ind) <= dds.cc.payload.last(dds_cnt);
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
@ -541,36 +646,36 @@ begin
|
||||
rtps_done <= '1';
|
||||
end if;
|
||||
when START =>
|
||||
if (ack_rtps = '1') then
|
||||
if (ack_rtps(ind) = '1') then
|
||||
rtps_stage <= DONE;
|
||||
end if;
|
||||
when DONE =>
|
||||
if (done_rtps = '1') then
|
||||
if (done_rtps(ind) = '1') then
|
||||
-- DEFAULT
|
||||
rtps_stage <= IDLE;
|
||||
|
||||
AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code));
|
||||
AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps(ind)), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code));
|
||||
case (rtps.opcode) is
|
||||
when GET_CACHE_CHANGE =>
|
||||
if (rtps.ret_code = OK) then
|
||||
AffirmIfEqual(inst_id, to_unsigned(cc_instance_handle), to_unsigned(rtps.cc.instance));
|
||||
AffirmIfEqual(kind_id, CACHE_CHANGE_KIND_TYPE'pos(cc_kind), CACHE_CHANGE_KIND_TYPE'pos(rtps.cc.kind));
|
||||
AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr));
|
||||
AffirmIfEqual(ts_id, to_unsigned(cc_source_timestamp), to_unsigned(rtps.cc.src_timestamp));
|
||||
AffirmIfEqual(inst_id, to_unsigned(cc_instance_handle(ind)), to_unsigned(rtps.cc.instance));
|
||||
AffirmIfEqual(kind_id, CACHE_CHANGE_KIND_TYPE'pos(cc_kind(ind)), CACHE_CHANGE_KIND_TYPE'pos(rtps.cc.kind));
|
||||
AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr(ind)), to_unsigned(rtps.cc.seq_nr));
|
||||
AffirmIfEqual(ts_id, to_unsigned(cc_source_timestamp(ind)), to_unsigned(rtps.cc.src_timestamp));
|
||||
rtps_stage <= CHECK;
|
||||
rtps_cnt <= 0;
|
||||
end if;
|
||||
when GET_MIN_SN =>
|
||||
AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr));
|
||||
AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr(ind)), to_unsigned(rtps.cc.seq_nr));
|
||||
when GET_MAX_SN =>
|
||||
AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr), to_unsigned(rtps.cc.seq_nr));
|
||||
AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr(ind)), to_unsigned(rtps.cc.seq_nr));
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
when CHECK =>
|
||||
if (valid_out_rtps = '1') then
|
||||
AffirmIfEqual(data_id, last_word_out_rtps & data_out_rtps, rtps.cc.payload.last(rtps_cnt) & rtps.cc.payload.data(rtps_cnt));
|
||||
if (valid_out_rtps(ind) = '1') then
|
||||
AffirmIfEqual(data_id, last_word_out_rtps(ind) & data_out_rtps(ind), rtps.cc.payload.last(rtps_cnt) & rtps.cc.payload.data(rtps_cnt));
|
||||
rtps_cnt <= rtps_cnt + 1;
|
||||
if (rtps_cnt = rtps.cc.payload.length-1) then
|
||||
rtps_stage <= IDLE;
|
||||
@ -580,28 +685,28 @@ begin
|
||||
end if;
|
||||
|
||||
-- DEFAULT
|
||||
start_rtps <= '0';
|
||||
opcode_rtps <= NOP;
|
||||
seq_nr_rtps <= SEQUENCENUMBER_UNKNOWN;
|
||||
get_data_rtps <= '0';
|
||||
ready_out_rtps <= '0';
|
||||
start_rtps <= (others => '0');
|
||||
opcode_rtps <= (others => NOP);
|
||||
seq_nr_rtps <= (others => SEQUENCENUMBER_UNKNOWN);
|
||||
get_data_rtps <= (others => '0');
|
||||
ready_out_rtps <= (others => '0');
|
||||
|
||||
case (rtps_stage) is
|
||||
when START =>
|
||||
start_rtps <= '1';
|
||||
opcode_rtps <= rtps.opcode;
|
||||
seq_nr_rtps <= rtps.cc.seq_nr;
|
||||
start_rtps(ind) <= '1';
|
||||
opcode_rtps(ind) <= rtps.opcode;
|
||||
seq_nr_rtps(ind) <= rtps.cc.seq_nr;
|
||||
when DONE =>
|
||||
if (done_rtps = '1') then
|
||||
if (done_rtps(ind) = '1') then
|
||||
case (rtps.opcode) is
|
||||
when GET_CACHE_CHANGE =>
|
||||
get_data_rtps <= '1';
|
||||
get_data_rtps(ind) <= '1';
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
when CHECK =>
|
||||
ready_out_rtps <= '1';
|
||||
ready_out_rtps(ind) <= '1';
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
@ -1,81 +0,0 @@
|
||||
-- TEST: GET_MIN_SN/GET_MAX_SN ON EMPTY
|
||||
-- TEST: GET_MIN_SN/GET_MAX_SN ON 1 SAMPLE
|
||||
-- TEST: GET_MIN_SN/GET_MAX_SN ON >1 SAMPLE
|
||||
|
||||
-- TEST: ADD SAMPLE WITH KEY_HASH [UNKNOWN INSTANCE]
|
||||
-- TEST: ADD SAMPLE WITH KEY_HASH [KNOWN INSTANCE]
|
||||
-- TEST: ADD SAMPLE WITH HANDLE_NIL [UNKNOWN INSTANCE]
|
||||
-- TEST: ADD SAMPLE WITH HANDLE_NIL [KNOWN INSTANCE]
|
||||
|
||||
-- TEST: NORMAL WRITE
|
||||
-- TEST: WRITE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES]
|
||||
-- TEST: WRITE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES]
|
||||
-- TEST: WRITE ON DISPOSED INSTANCE
|
||||
-- TEST: WRITE ON UNREGISTERED INSTANCE
|
||||
|
||||
-- TEST: WRITE ALIGNED PAYLOAD
|
||||
-- TEST: WRITE UNALIGNED PAYLOAD [>1 SLOT]
|
||||
-- TEST: WRITE UNALIGNED PAYLOAD [<1 SLOT]
|
||||
|
||||
-- TEST: NORMAL REGISTER
|
||||
-- TEST: REGISTER INSTANCE [KNOWN INSTANCE]
|
||||
-- TEST: REGISTER INSTANCE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCE]
|
||||
-- TEST: REGISTER INSTANCE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE]
|
||||
-- TEST: REGISTER ON UNREGISTERED INSTANCE
|
||||
|
||||
-- TEST: NORMAL DISPOSE
|
||||
-- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES]
|
||||
-- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES]
|
||||
-- TEST: DISPOSE ON UNREGISTERED INSTANCE
|
||||
|
||||
-- TEST: GET_CACHE_CHANGE [UNKNOWN SN]
|
||||
-- TEST: GET_CACHE_CHANGE [KNOWN SN, ALIGNED PAYLOAD]
|
||||
-- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, >1 SLOT]
|
||||
-- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, <1 SLOT]
|
||||
|
||||
-- TEST: NORMAL ACK_CACHE_CHANGE
|
||||
-- TEST: ACK_CACHE_CHANGE [ALREADY ACKed SN]
|
||||
-- TEST: NORMAL NACK_CACHE_CHANGE
|
||||
|
||||
-- TEST: REMOVE_CACHE_CHANGE [UNKNOWN SN]
|
||||
-- TEST: REMOVE_CACHE_CHANGE [KNOWN SN]
|
||||
|
||||
-- TEST: NORMAL UNREGISTER
|
||||
-- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES]
|
||||
-- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES]
|
||||
-- TEST: UNREGISTER ON DISPOSED INSTANCE
|
||||
-- TEST: UNREGISTER UNKNOWN INSTANCE
|
||||
|
||||
-- TEST: REMOVE STALE INSTANCE WITH 0 SAMPLES
|
||||
-- TEST: REMOVE STALE INSTANCE WITH 1 SAMPLES
|
||||
-- TEST: REMOVE STALE INSTANCE WITH >1 SAMPLES
|
||||
|
||||
-- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE]
|
||||
-- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCES]
|
||||
-- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH FULLY ACKed INSTANCE, WITHOUT STALE INSTANCE]
|
||||
|
||||
-- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITHOUT ACKed SAMPLES]
|
||||
-- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES]
|
||||
-- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed INSTANCE SAMPLE]
|
||||
-- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed INSTANCE SAMPLES(>1)]
|
||||
|
||||
-- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITHOUT ACKed SAMPLES]
|
||||
-- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLE]
|
||||
-- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLES (>1)]
|
||||
|
||||
-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITHOUT ACKed SAMPLES]
|
||||
-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES]
|
||||
-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITH ACKed INSTANCE SAMPLES]
|
||||
|
||||
-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE, WITHOUT ACKed SAMPLE]
|
||||
-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITHOUT STALE INSTANCES,WITHOUT ACKed SAMPLES]
|
||||
-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITHOUT STALE INSTANCE, WITH ACKed SAMPLE]
|
||||
-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE (>0 SAMPLES)]
|
||||
-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE, WITH ACKed SAMPLE]
|
||||
|
||||
-- TEST: ADD SAMPLE ON PAYLOAD MEMORY FULL & MAX_INSTANCES [UNKNOWN INSTANCE,WITH ACKed SAMPLES,WITH STALE INSTANCE (>= 1 SAMPLE)] (Induce Double Remove)
|
||||
|
||||
-- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE [WITH ACKed SAMPLES]
|
||||
|
||||
-- TEST: INSTANCE LOOKUP [KNOWN INSTANCE]
|
||||
-- TEST: INSTANCE LOOKUP [UNKNOWN INSTANCE]
|
||||
@ -365,122 +365,114 @@ begin
|
||||
);
|
||||
end generate;
|
||||
|
||||
dds_endpoint_gen : for i in 0 to NUM_ENDPOINTS-1 generate
|
||||
dds_endpoint_if : if (i < NUM_READERS) generate
|
||||
dds_reader_inst : entity work.dds_reader(arch)
|
||||
generic map (
|
||||
TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS,
|
||||
DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS,
|
||||
MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES,
|
||||
MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE,
|
||||
MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES,
|
||||
HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS,
|
||||
RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS,
|
||||
PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS,
|
||||
DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS,
|
||||
COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS,
|
||||
ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS,
|
||||
WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY,
|
||||
PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE,
|
||||
MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS
|
||||
)
|
||||
port map (
|
||||
-- SYSTEM
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
time => time,
|
||||
-- FROM RTPS ENDPOINT
|
||||
start_rtps => start_rr_dr(i),
|
||||
opcode_rtps => opcode_rr_dr(i),
|
||||
ack_rtps => ack_dr_rr(i),
|
||||
done_rtps => done_dr_rr(i),
|
||||
ret_rtps => ret_dr_rr(i),
|
||||
valid_in_rtps => valid_rr_dr(i),
|
||||
ready_in_rtps => ready_dr_rr(i),
|
||||
data_in_rtps => data_rr_dr(i),
|
||||
last_word_in_rtps => last_word_rr_dr(i),
|
||||
-- TO USER ENTITY
|
||||
start_dds => start_ri_dr(i),
|
||||
ack_dds => ack_dr_ri(i),
|
||||
opcode_dds => opcode_ri_dr(i),
|
||||
instance_state_dds => instance_state_ri_dr(i),
|
||||
view_state_dds => view_state_ri_dr(i),
|
||||
sample_state_dds => sample_state_ri_dr(i),
|
||||
instance_handle_dds => instance_handle_ri_dr(i),
|
||||
max_samples_dds => max_samples_ri_dr(i),
|
||||
get_data_dds => get_data_ri_dr(i),
|
||||
done_dds => done_dr_ri(i),
|
||||
return_code_dds => return_code_dr_ri(i),
|
||||
valid_out_dds => valid_dr_ri(i),
|
||||
ready_out_dds => ready_ri_dr(i),
|
||||
data_out_dds => data_dr_ri(i),
|
||||
last_word_out_dds => last_word_dr_ri(i),
|
||||
sample_info => sample_info_dr_ri(i),
|
||||
sample_info_valid => sample_info_valid_dr_ri(i),
|
||||
sample_info_ack => sample_info_ack_ri_dr(i),
|
||||
eoc => eoc_dr_ri(i),
|
||||
-- Communication Status
|
||||
status => status_dr_ri(i)
|
||||
);
|
||||
else generate
|
||||
dds_writer_inst : entity work.dds_writer(arch)
|
||||
generic map (
|
||||
HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS,
|
||||
DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS,
|
||||
LIFESPAN_QOS => ENDPOINT_CONFIG(i).LIFESPAN_QOS,
|
||||
LEASE_DURATION => ENDPOINT_CONFIG(i).LEASE_DURATION,
|
||||
WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY,
|
||||
MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES,
|
||||
MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES,
|
||||
MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE,
|
||||
PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE
|
||||
)
|
||||
port map (
|
||||
-- SYSTEM
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
time => time,
|
||||
-- TO/FROM RTPS ENDPOINT
|
||||
start_rtps => start_rw_dw(i-NUM_READERS),
|
||||
opcode_rtps => opcode_rw_dw(i-NUM_READERS),
|
||||
ack_rtps => ack_dw_rw(i-NUM_READERS),
|
||||
done_rtps => done_rw_dw(i-NUM_READERS),
|
||||
ret_rtps => ret_dw_rw(i-NUM_READERS),
|
||||
seq_nr_rtps => seq_nr_rw_dw(i-NUM_READERS),
|
||||
get_data_rtps => get_data_rw_dw(i-NUM_READERS),
|
||||
valid_out_rtps => valid_dw_rw(i-NUM_READERS),
|
||||
ready_out_rtps => ready_rw_dw(i-NUM_READERS),
|
||||
data_out_rtps => data_dw_rw(i-NUM_READERS),
|
||||
last_word_out_rtps => last_word_dw_rw(i-NUM_READERS),
|
||||
liveliness_assertion => liveliness_assertion_dw_rw(i-NUM_READERS),
|
||||
data_available => data_available_dw_rw(i-NUM_READERS),
|
||||
-- Cache Change
|
||||
cc_instance_handle => cc_instance_handle_dw_rw(i-NUM_READERS),
|
||||
cc_kind => cc_kind_dw_rw(i-NUM_READERS),
|
||||
cc_source_timestamp => cc_source_timestamp_dw_rw(i-NUM_READERS),
|
||||
cc_seq_nr => cc_seq_nr_dw_rw(i-NUM_READERS),
|
||||
-- TO/FROM USER ENTITY
|
||||
start_dds => start_wi_dw(i-NUM_READERS),
|
||||
ack_dds => ack_dw_wi(i-NUM_READERS),
|
||||
opcode_dds => opcode_wi_dw(i-NUM_READERS),
|
||||
instance_handle_in_dds => instance_handle_wi_dw(i-NUM_READERS),
|
||||
source_ts_dds => source_ts_wi_dw(i-NUM_READERS),
|
||||
max_wait_dds => max_wait_wi_dw(i-NUM_READERS),
|
||||
done_dds => done_dw_wi(i-NUM_READERS),
|
||||
return_code_dds => return_code_dw_wi(i-NUM_READERS),
|
||||
instance_handle_out_dds => instance_handle_dw_wi(i-NUM_READERS),
|
||||
valid_in_dds => valid_wi_dw(i-NUM_READERS),
|
||||
ready_in_dds => ready_dw_wi(i-NUM_READERS),
|
||||
data_in_dds => data_wi_dw(i-NUM_READERS),
|
||||
last_word_in_dds => last_word_wi_dw(i-NUM_READERS),
|
||||
valid_out_dds => valid_dw_wi(i-NUM_READERS),
|
||||
ready_out_dds => ready_wi_dw(i-NUM_READERS),
|
||||
data_out_dds => data_dw_wi(i-NUM_READERS),
|
||||
last_word_out_dds => last_word_dw_wi(i-NUM_READERS),
|
||||
-- Communication Status
|
||||
status => status_dw_wi(i-NUM_READERS)
|
||||
);
|
||||
end generate;
|
||||
dds_endpoint_w_if : if (NUM_WRITERS > 0) generate
|
||||
dds_writer_inst : entity work.dds_writer(arch)
|
||||
generic map (
|
||||
NUM_WRITERS => NUM_WRITERS,
|
||||
CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(ENDPOINT_CONFIG(NUM_READERS to NUM_ENDPOINTS-1))
|
||||
)
|
||||
port map (
|
||||
-- SYSTEM
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
time => time,
|
||||
-- TO/FROM RTPS ENDPOINT
|
||||
start_rtps => start_rw_dw(0 to NUM_WRITERS-1),
|
||||
opcode_rtps => opcode_rw_dw(0 to NUM_WRITERS-1),
|
||||
ack_rtps => ack_dw_rw(0 to NUM_WRITERS-1),
|
||||
done_rtps => done_rw_dw(0 to NUM_WRITERS-1),
|
||||
ret_rtps => ret_dw_rw(0 to NUM_WRITERS-1),
|
||||
seq_nr_rtps => seq_nr_rw_dw(0 to NUM_WRITERS-1),
|
||||
get_data_rtps => get_data_rw_dw(0 to NUM_WRITERS-1),
|
||||
valid_out_rtps => valid_dw_rw(0 to NUM_WRITERS-1),
|
||||
ready_out_rtps => ready_rw_dw(0 to NUM_WRITERS-1),
|
||||
data_out_rtps => data_dw_rw(0 to NUM_WRITERS-1),
|
||||
last_word_out_rtps => last_word_dw_rw(0 to NUM_WRITERS-1),
|
||||
liveliness_assertion => liveliness_assertion_dw_rw(0 to NUM_WRITERS-1),
|
||||
data_available => data_available_dw_rw(0 to NUM_WRITERS-1),
|
||||
-- Cache Change
|
||||
cc_instance_handle => cc_instance_handle_dw_rw(0 to NUM_WRITERS-1),
|
||||
cc_kind => cc_kind_dw_rw(0 to NUM_WRITERS-1),
|
||||
cc_source_timestamp => cc_source_timestamp_dw_rw(0 to NUM_WRITERS-1),
|
||||
cc_seq_nr => cc_seq_nr_dw_rw(0 to NUM_WRITERS-1),
|
||||
-- TO/FROM USER ENTITY
|
||||
start_dds => start_wi_dw(0 to NUM_WRITERS-1),
|
||||
ack_dds => ack_dw_wi(0 to NUM_WRITERS-1),
|
||||
opcode_dds => opcode_wi_dw(0 to NUM_WRITERS-1),
|
||||
instance_handle_in_dds => instance_handle_wi_dw(0 to NUM_WRITERS-1),
|
||||
source_ts_dds => source_ts_wi_dw(0 to NUM_WRITERS-1),
|
||||
max_wait_dds => max_wait_wi_dw(0 to NUM_WRITERS-1),
|
||||
done_dds => done_dw_wi(0 to NUM_WRITERS-1),
|
||||
return_code_dds => return_code_dw_wi(0 to NUM_WRITERS-1),
|
||||
instance_handle_out_dds => instance_handle_dw_wi(0 to NUM_WRITERS-1),
|
||||
valid_in_dds => valid_wi_dw(0 to NUM_WRITERS-1),
|
||||
ready_in_dds => ready_dw_wi(0 to NUM_WRITERS-1),
|
||||
data_in_dds => data_wi_dw(0 to NUM_WRITERS-1),
|
||||
last_word_in_dds => last_word_wi_dw(0 to NUM_WRITERS-1),
|
||||
valid_out_dds => valid_dw_wi(0 to NUM_WRITERS-1),
|
||||
ready_out_dds => ready_wi_dw(0 to NUM_WRITERS-1),
|
||||
data_out_dds => data_dw_wi(0 to NUM_WRITERS-1),
|
||||
last_word_out_dds => last_word_dw_wi(0 to NUM_WRITERS-1),
|
||||
-- Communication Status
|
||||
status => status_dw_wi(0 to NUM_WRITERS-1)
|
||||
);
|
||||
end generate;
|
||||
dds_endpoint_gen : for i in 0 to NUM_READERS-1 generate
|
||||
dds_reader_inst : entity work.dds_reader(arch)
|
||||
generic map (
|
||||
TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS,
|
||||
DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS,
|
||||
MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES,
|
||||
MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE,
|
||||
MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES,
|
||||
HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS,
|
||||
RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS,
|
||||
PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS,
|
||||
DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS,
|
||||
COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS,
|
||||
ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS,
|
||||
WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY,
|
||||
PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE,
|
||||
MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS
|
||||
)
|
||||
port map (
|
||||
-- SYSTEM
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
time => time,
|
||||
-- FROM RTPS ENDPOINT
|
||||
start_rtps => start_rr_dr(i),
|
||||
opcode_rtps => opcode_rr_dr(i),
|
||||
ack_rtps => ack_dr_rr(i),
|
||||
done_rtps => done_dr_rr(i),
|
||||
ret_rtps => ret_dr_rr(i),
|
||||
valid_in_rtps => valid_rr_dr(i),
|
||||
ready_in_rtps => ready_dr_rr(i),
|
||||
data_in_rtps => data_rr_dr(i),
|
||||
last_word_in_rtps => last_word_rr_dr(i),
|
||||
-- TO USER ENTITY
|
||||
start_dds => start_ri_dr(i),
|
||||
ack_dds => ack_dr_ri(i),
|
||||
opcode_dds => opcode_ri_dr(i),
|
||||
instance_state_dds => instance_state_ri_dr(i),
|
||||
view_state_dds => view_state_ri_dr(i),
|
||||
sample_state_dds => sample_state_ri_dr(i),
|
||||
instance_handle_dds => instance_handle_ri_dr(i),
|
||||
max_samples_dds => max_samples_ri_dr(i),
|
||||
get_data_dds => get_data_ri_dr(i),
|
||||
done_dds => done_dr_ri(i),
|
||||
return_code_dds => return_code_dr_ri(i),
|
||||
valid_out_dds => valid_dr_ri(i),
|
||||
ready_out_dds => ready_ri_dr(i),
|
||||
data_out_dds => data_dr_ri(i),
|
||||
last_word_out_dds => last_word_dr_ri(i),
|
||||
sample_info => sample_info_dr_ri(i),
|
||||
sample_info_valid => sample_info_valid_dr_ri(i),
|
||||
sample_info_ack => sample_info_ack_ri_dr(i),
|
||||
eoc => eoc_dr_ri(i),
|
||||
-- Communication Status
|
||||
status => status_dr_ri(i)
|
||||
);
|
||||
end generate;
|
||||
|
||||
|
||||
|
||||
@ -372,122 +372,114 @@ begin
|
||||
);
|
||||
end generate;
|
||||
|
||||
dds_endpoint_gen : for i in 0 to NUM_ENDPOINTS-1 generate
|
||||
dds_endpoint_if : if (i < NUM_READERS) generate
|
||||
dds_reader_inst : entity work.dds_reader(arch)
|
||||
generic map (
|
||||
TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS,
|
||||
DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS,
|
||||
MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES,
|
||||
MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE,
|
||||
MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES,
|
||||
HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS,
|
||||
RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS,
|
||||
PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS,
|
||||
DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS,
|
||||
COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS,
|
||||
ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS,
|
||||
WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY,
|
||||
PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE,
|
||||
MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS
|
||||
)
|
||||
port map (
|
||||
-- SYSTEM
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
time => time,
|
||||
-- FROM RTPS ENDPOINT
|
||||
start_rtps => start_rr_dr(i),
|
||||
opcode_rtps => opcode_rr_dr(i),
|
||||
ack_rtps => ack_dr_rr(i),
|
||||
done_rtps => done_dr_rr(i),
|
||||
ret_rtps => ret_dr_rr(i),
|
||||
valid_in_rtps => valid_rr_dr(i),
|
||||
ready_in_rtps => ready_dr_rr(i),
|
||||
data_in_rtps => data_rr_dr(i),
|
||||
last_word_in_rtps => last_word_rr_dr(i),
|
||||
-- TO USER ENTITY
|
||||
start_dds => start_ri_dr(i),
|
||||
ack_dds => ack_dr_ri(i),
|
||||
opcode_dds => opcode_ri_dr(i),
|
||||
instance_state_dds => instance_state_ri_dr(i),
|
||||
view_state_dds => view_state_ri_dr(i),
|
||||
sample_state_dds => sample_state_ri_dr(i),
|
||||
instance_handle_dds => instance_handle_ri_dr(i),
|
||||
max_samples_dds => max_samples_ri_dr(i),
|
||||
get_data_dds => get_data_ri_dr(i),
|
||||
done_dds => done_dr_ri(i),
|
||||
return_code_dds => return_code_dr_ri(i),
|
||||
valid_out_dds => valid_dr_ri(i),
|
||||
ready_out_dds => ready_ri_dr(i),
|
||||
data_out_dds => data_dr_ri(i),
|
||||
last_word_out_dds => last_word_dr_ri(i),
|
||||
sample_info => sample_info_dr_ri(i),
|
||||
sample_info_valid => sample_info_valid_dr_ri(i),
|
||||
sample_info_ack => sample_info_ack_ri_dr(i),
|
||||
eoc => eoc_dr_ri(i),
|
||||
-- Communication Status
|
||||
status => status_dr_ri(i)
|
||||
);
|
||||
else generate
|
||||
dds_writer_inst : entity work.dds_writer(arch)
|
||||
generic map (
|
||||
HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS,
|
||||
DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS,
|
||||
LIFESPAN_QOS => ENDPOINT_CONFIG(i).LIFESPAN_QOS,
|
||||
LEASE_DURATION => ENDPOINT_CONFIG(i).LEASE_DURATION,
|
||||
WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY,
|
||||
MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES,
|
||||
MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES,
|
||||
MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE,
|
||||
PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE
|
||||
)
|
||||
port map (
|
||||
-- SYSTEM
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
time => time,
|
||||
-- TO/FROM RTPS ENDPOINT
|
||||
start_rtps => start_rw_dw(i-NUM_READERS),
|
||||
opcode_rtps => opcode_rw_dw(i-NUM_READERS),
|
||||
ack_rtps => ack_dw_rw(i-NUM_READERS),
|
||||
done_rtps => done_rw_dw(i-NUM_READERS),
|
||||
ret_rtps => ret_dw_rw(i-NUM_READERS),
|
||||
seq_nr_rtps => seq_nr_rw_dw(i-NUM_READERS),
|
||||
get_data_rtps => get_data_rw_dw(i-NUM_READERS),
|
||||
valid_out_rtps => valid_dw_rw(i-NUM_READERS),
|
||||
ready_out_rtps => ready_rw_dw(i-NUM_READERS),
|
||||
data_out_rtps => data_dw_rw(i-NUM_READERS),
|
||||
last_word_out_rtps => last_word_dw_rw(i-NUM_READERS),
|
||||
liveliness_assertion => liveliness_assertion_dw_rw(i-NUM_READERS),
|
||||
data_available => data_available_dw_rw(i-NUM_READERS),
|
||||
-- Cache Change
|
||||
cc_instance_handle => cc_instance_handle_dw_rw(i-NUM_READERS),
|
||||
cc_kind => cc_kind_dw_rw(i-NUM_READERS),
|
||||
cc_source_timestamp => cc_source_timestamp_dw_rw(i-NUM_READERS),
|
||||
cc_seq_nr => cc_seq_nr_dw_rw(i-NUM_READERS),
|
||||
-- TO/FROM USER ENTITY
|
||||
start_dds => start_wi_dw(i-NUM_READERS),
|
||||
ack_dds => ack_dw_wi(i-NUM_READERS),
|
||||
opcode_dds => opcode_wi_dw(i-NUM_READERS),
|
||||
instance_handle_in_dds => instance_handle_wi_dw(i-NUM_READERS),
|
||||
source_ts_dds => source_ts_wi_dw(i-NUM_READERS),
|
||||
max_wait_dds => max_wait_wi_dw(i-NUM_READERS),
|
||||
done_dds => done_dw_wi(i-NUM_READERS),
|
||||
return_code_dds => return_code_dw_wi(i-NUM_READERS),
|
||||
instance_handle_out_dds => instance_handle_dw_wi(i-NUM_READERS),
|
||||
valid_in_dds => valid_wi_dw(i-NUM_READERS),
|
||||
ready_in_dds => ready_dw_wi(i-NUM_READERS),
|
||||
data_in_dds => data_wi_dw(i-NUM_READERS),
|
||||
last_word_in_dds => last_word_wi_dw(i-NUM_READERS),
|
||||
valid_out_dds => valid_dw_wi(i-NUM_READERS),
|
||||
ready_out_dds => ready_wi_dw(i-NUM_READERS),
|
||||
data_out_dds => data_dw_wi(i-NUM_READERS),
|
||||
last_word_out_dds => last_word_dw_wi(i-NUM_READERS),
|
||||
-- Communication Status
|
||||
status => status_dw_wi(i-NUM_READERS)
|
||||
);
|
||||
end generate;
|
||||
dds_endpoint_w_if : if (NUM_WRITERS > 0) generate
|
||||
dds_writer_inst : entity work.dds_writer(arch)
|
||||
generic map (
|
||||
NUM_WRITERS => NUM_WRITERS,
|
||||
CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(ENDPOINT_CONFIG(NUM_READERS to NUM_ENDPOINTS-1))
|
||||
)
|
||||
port map (
|
||||
-- SYSTEM
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
time => time,
|
||||
-- TO/FROM RTPS ENDPOINT
|
||||
start_rtps => start_rw_dw(0 to NUM_WRITERS-1),
|
||||
opcode_rtps => opcode_rw_dw(0 to NUM_WRITERS-1),
|
||||
ack_rtps => ack_dw_rw(0 to NUM_WRITERS-1),
|
||||
done_rtps => done_rw_dw(0 to NUM_WRITERS-1),
|
||||
ret_rtps => ret_dw_rw(0 to NUM_WRITERS-1),
|
||||
seq_nr_rtps => seq_nr_rw_dw(0 to NUM_WRITERS-1),
|
||||
get_data_rtps => get_data_rw_dw(0 to NUM_WRITERS-1),
|
||||
valid_out_rtps => valid_dw_rw(0 to NUM_WRITERS-1),
|
||||
ready_out_rtps => ready_rw_dw(0 to NUM_WRITERS-1),
|
||||
data_out_rtps => data_dw_rw(0 to NUM_WRITERS-1),
|
||||
last_word_out_rtps => last_word_dw_rw(0 to NUM_WRITERS-1),
|
||||
liveliness_assertion => liveliness_assertion_dw_rw(0 to NUM_WRITERS-1),
|
||||
data_available => data_available_dw_rw(0 to NUM_WRITERS-1),
|
||||
-- Cache Change
|
||||
cc_instance_handle => cc_instance_handle_dw_rw(0 to NUM_WRITERS-1),
|
||||
cc_kind => cc_kind_dw_rw(0 to NUM_WRITERS-1),
|
||||
cc_source_timestamp => cc_source_timestamp_dw_rw(0 to NUM_WRITERS-1),
|
||||
cc_seq_nr => cc_seq_nr_dw_rw(0 to NUM_WRITERS-1),
|
||||
-- TO/FROM USER ENTITY
|
||||
start_dds => start_wi_dw(0 to NUM_WRITERS-1),
|
||||
ack_dds => ack_dw_wi(0 to NUM_WRITERS-1),
|
||||
opcode_dds => opcode_wi_dw(0 to NUM_WRITERS-1),
|
||||
instance_handle_in_dds => instance_handle_wi_dw(0 to NUM_WRITERS-1),
|
||||
source_ts_dds => source_ts_wi_dw(0 to NUM_WRITERS-1),
|
||||
max_wait_dds => max_wait_wi_dw(0 to NUM_WRITERS-1),
|
||||
done_dds => done_dw_wi(0 to NUM_WRITERS-1),
|
||||
return_code_dds => return_code_dw_wi(0 to NUM_WRITERS-1),
|
||||
instance_handle_out_dds => instance_handle_dw_wi(0 to NUM_WRITERS-1),
|
||||
valid_in_dds => valid_wi_dw(0 to NUM_WRITERS-1),
|
||||
ready_in_dds => ready_dw_wi(0 to NUM_WRITERS-1),
|
||||
data_in_dds => data_wi_dw(0 to NUM_WRITERS-1),
|
||||
last_word_in_dds => last_word_wi_dw(0 to NUM_WRITERS-1),
|
||||
valid_out_dds => valid_dw_wi(0 to NUM_WRITERS-1),
|
||||
ready_out_dds => ready_wi_dw(0 to NUM_WRITERS-1),
|
||||
data_out_dds => data_dw_wi(0 to NUM_WRITERS-1),
|
||||
last_word_out_dds => last_word_dw_wi(0 to NUM_WRITERS-1),
|
||||
-- Communication Status
|
||||
status => status_dw_wi(0 to NUM_WRITERS-1)
|
||||
);
|
||||
end generate;
|
||||
dds_endpoint_gen : for i in 0 to NUM_READERS-1 generate
|
||||
dds_reader_inst : entity work.dds_reader(arch)
|
||||
generic map (
|
||||
TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS,
|
||||
DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS,
|
||||
MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES,
|
||||
MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE,
|
||||
MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES,
|
||||
HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS,
|
||||
RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS,
|
||||
PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS,
|
||||
DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS,
|
||||
COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS,
|
||||
ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS,
|
||||
WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY,
|
||||
PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE,
|
||||
MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS
|
||||
)
|
||||
port map (
|
||||
-- SYSTEM
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
time => time,
|
||||
-- FROM RTPS ENDPOINT
|
||||
start_rtps => start_rr_dr(i),
|
||||
opcode_rtps => opcode_rr_dr(i),
|
||||
ack_rtps => ack_dr_rr(i),
|
||||
done_rtps => done_dr_rr(i),
|
||||
ret_rtps => ret_dr_rr(i),
|
||||
valid_in_rtps => valid_rr_dr(i),
|
||||
ready_in_rtps => ready_dr_rr(i),
|
||||
data_in_rtps => data_rr_dr(i),
|
||||
last_word_in_rtps => last_word_rr_dr(i),
|
||||
-- TO USER ENTITY
|
||||
start_dds => start_ri_dr(i),
|
||||
ack_dds => ack_dr_ri(i),
|
||||
opcode_dds => opcode_ri_dr(i),
|
||||
instance_state_dds => instance_state_ri_dr(i),
|
||||
view_state_dds => view_state_ri_dr(i),
|
||||
sample_state_dds => sample_state_ri_dr(i),
|
||||
instance_handle_dds => instance_handle_ri_dr(i),
|
||||
max_samples_dds => max_samples_ri_dr(i),
|
||||
get_data_dds => get_data_ri_dr(i),
|
||||
done_dds => done_dr_ri(i),
|
||||
return_code_dds => return_code_dr_ri(i),
|
||||
valid_out_dds => valid_dr_ri(i),
|
||||
ready_out_dds => ready_ri_dr(i),
|
||||
data_out_dds => data_dr_ri(i),
|
||||
last_word_out_dds => last_word_dr_ri(i),
|
||||
sample_info => sample_info_dr_ri(i),
|
||||
sample_info_valid => sample_info_valid_dr_ri(i),
|
||||
sample_info_ack => sample_info_ack_ri_dr(i),
|
||||
eoc => eoc_dr_ri(i),
|
||||
-- Communication Status
|
||||
status => status_dr_ri(i)
|
||||
);
|
||||
end generate;
|
||||
|
||||
|
||||
|
||||
@ -368,122 +368,114 @@ begin
|
||||
);
|
||||
end generate;
|
||||
|
||||
dds_endpoint_gen : for i in 0 to NUM_ENDPOINTS-1 generate
|
||||
dds_endpoint_if : if (i < NUM_READERS) generate
|
||||
dds_reader_inst : entity work.dds_reader(arch)
|
||||
generic map (
|
||||
TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS,
|
||||
DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS,
|
||||
MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES,
|
||||
MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE,
|
||||
MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES,
|
||||
HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS,
|
||||
RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS,
|
||||
PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS,
|
||||
DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS,
|
||||
COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS,
|
||||
ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS,
|
||||
WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY,
|
||||
PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE,
|
||||
MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS
|
||||
)
|
||||
port map (
|
||||
-- SYSTEM
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
time => time,
|
||||
-- FROM RTPS ENDPOINT
|
||||
start_rtps => start_rr_dr(i),
|
||||
opcode_rtps => opcode_rr_dr(i),
|
||||
ack_rtps => ack_dr_rr(i),
|
||||
done_rtps => done_dr_rr(i),
|
||||
ret_rtps => ret_dr_rr(i),
|
||||
valid_in_rtps => valid_rr_dr(i),
|
||||
ready_in_rtps => ready_dr_rr(i),
|
||||
data_in_rtps => data_rr_dr(i),
|
||||
last_word_in_rtps => last_word_rr_dr(i),
|
||||
-- TO USER ENTITY
|
||||
start_dds => start_ri_dr(i),
|
||||
ack_dds => ack_dr_ri(i),
|
||||
opcode_dds => opcode_ri_dr(i),
|
||||
instance_state_dds => instance_state_ri_dr(i),
|
||||
view_state_dds => view_state_ri_dr(i),
|
||||
sample_state_dds => sample_state_ri_dr(i),
|
||||
instance_handle_dds => instance_handle_ri_dr(i),
|
||||
max_samples_dds => max_samples_ri_dr(i),
|
||||
get_data_dds => get_data_ri_dr(i),
|
||||
done_dds => done_dr_ri(i),
|
||||
return_code_dds => return_code_dr_ri(i),
|
||||
valid_out_dds => valid_dr_ri(i),
|
||||
ready_out_dds => ready_ri_dr(i),
|
||||
data_out_dds => data_dr_ri(i),
|
||||
last_word_out_dds => last_word_dr_ri(i),
|
||||
sample_info => sample_info_dr_ri(i),
|
||||
sample_info_valid => sample_info_valid_dr_ri(i),
|
||||
sample_info_ack => sample_info_ack_ri_dr(i),
|
||||
eoc => eoc_dr_ri(i),
|
||||
-- Communication Status
|
||||
status => status_dr_ri(i)
|
||||
);
|
||||
else generate
|
||||
dds_writer_inst : entity work.dds_writer(arch)
|
||||
generic map (
|
||||
HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS,
|
||||
DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS,
|
||||
LIFESPAN_QOS => ENDPOINT_CONFIG(i).LIFESPAN_QOS,
|
||||
LEASE_DURATION => ENDPOINT_CONFIG(i).LEASE_DURATION,
|
||||
WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY,
|
||||
MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES,
|
||||
MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES,
|
||||
MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE,
|
||||
PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE
|
||||
)
|
||||
port map (
|
||||
-- SYSTEM
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
time => time,
|
||||
-- TO/FROM RTPS ENDPOINT
|
||||
start_rtps => start_rw_dw(i-NUM_READERS),
|
||||
opcode_rtps => opcode_rw_dw(i-NUM_READERS),
|
||||
ack_rtps => ack_dw_rw(i-NUM_READERS),
|
||||
done_rtps => done_rw_dw(i-NUM_READERS),
|
||||
ret_rtps => ret_dw_rw(i-NUM_READERS),
|
||||
seq_nr_rtps => seq_nr_rw_dw(i-NUM_READERS),
|
||||
get_data_rtps => get_data_rw_dw(i-NUM_READERS),
|
||||
valid_out_rtps => valid_dw_rw(i-NUM_READERS),
|
||||
ready_out_rtps => ready_rw_dw(i-NUM_READERS),
|
||||
data_out_rtps => data_dw_rw(i-NUM_READERS),
|
||||
last_word_out_rtps => last_word_dw_rw(i-NUM_READERS),
|
||||
liveliness_assertion => liveliness_assertion_dw_rw(i-NUM_READERS),
|
||||
data_available => data_available_dw_rw(i-NUM_READERS),
|
||||
-- Cache Change
|
||||
cc_instance_handle => cc_instance_handle_dw_rw(i-NUM_READERS),
|
||||
cc_kind => cc_kind_dw_rw(i-NUM_READERS),
|
||||
cc_source_timestamp => cc_source_timestamp_dw_rw(i-NUM_READERS),
|
||||
cc_seq_nr => cc_seq_nr_dw_rw(i-NUM_READERS),
|
||||
-- TO/FROM USER ENTITY
|
||||
start_dds => start_wi_dw(i-NUM_READERS),
|
||||
ack_dds => ack_dw_wi(i-NUM_READERS),
|
||||
opcode_dds => opcode_wi_dw(i-NUM_READERS),
|
||||
instance_handle_in_dds => instance_handle_wi_dw(i-NUM_READERS),
|
||||
source_ts_dds => source_ts_wi_dw(i-NUM_READERS),
|
||||
max_wait_dds => max_wait_wi_dw(i-NUM_READERS),
|
||||
done_dds => done_dw_wi(i-NUM_READERS),
|
||||
return_code_dds => return_code_dw_wi(i-NUM_READERS),
|
||||
instance_handle_out_dds => instance_handle_dw_wi(i-NUM_READERS),
|
||||
valid_in_dds => valid_wi_dw(i-NUM_READERS),
|
||||
ready_in_dds => ready_dw_wi(i-NUM_READERS),
|
||||
data_in_dds => data_wi_dw(i-NUM_READERS),
|
||||
last_word_in_dds => last_word_wi_dw(i-NUM_READERS),
|
||||
valid_out_dds => valid_dw_wi(i-NUM_READERS),
|
||||
ready_out_dds => ready_wi_dw(i-NUM_READERS),
|
||||
data_out_dds => data_dw_wi(i-NUM_READERS),
|
||||
last_word_out_dds => last_word_dw_wi(i-NUM_READERS),
|
||||
-- Communication Status
|
||||
status => status_dw_wi(i-NUM_READERS)
|
||||
);
|
||||
end generate;
|
||||
dds_endpoint_w_if : if (NUM_WRITERS > 0) generate
|
||||
dds_writer_inst : entity work.dds_writer(arch)
|
||||
generic map (
|
||||
NUM_WRITERS => NUM_WRITERS,
|
||||
CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(ENDPOINT_CONFIG(NUM_READERS to NUM_ENDPOINTS-1))
|
||||
)
|
||||
port map (
|
||||
-- SYSTEM
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
time => time,
|
||||
-- TO/FROM RTPS ENDPOINT
|
||||
start_rtps => start_rw_dw(0 to NUM_WRITERS-1),
|
||||
opcode_rtps => opcode_rw_dw(0 to NUM_WRITERS-1),
|
||||
ack_rtps => ack_dw_rw(0 to NUM_WRITERS-1),
|
||||
done_rtps => done_rw_dw(0 to NUM_WRITERS-1),
|
||||
ret_rtps => ret_dw_rw(0 to NUM_WRITERS-1),
|
||||
seq_nr_rtps => seq_nr_rw_dw(0 to NUM_WRITERS-1),
|
||||
get_data_rtps => get_data_rw_dw(0 to NUM_WRITERS-1),
|
||||
valid_out_rtps => valid_dw_rw(0 to NUM_WRITERS-1),
|
||||
ready_out_rtps => ready_rw_dw(0 to NUM_WRITERS-1),
|
||||
data_out_rtps => data_dw_rw(0 to NUM_WRITERS-1),
|
||||
last_word_out_rtps => last_word_dw_rw(0 to NUM_WRITERS-1),
|
||||
liveliness_assertion => liveliness_assertion_dw_rw(0 to NUM_WRITERS-1),
|
||||
data_available => data_available_dw_rw(0 to NUM_WRITERS-1),
|
||||
-- Cache Change
|
||||
cc_instance_handle => cc_instance_handle_dw_rw(0 to NUM_WRITERS-1),
|
||||
cc_kind => cc_kind_dw_rw(0 to NUM_WRITERS-1),
|
||||
cc_source_timestamp => cc_source_timestamp_dw_rw(0 to NUM_WRITERS-1),
|
||||
cc_seq_nr => cc_seq_nr_dw_rw(0 to NUM_WRITERS-1),
|
||||
-- TO/FROM USER ENTITY
|
||||
start_dds => start_wi_dw(0 to NUM_WRITERS-1),
|
||||
ack_dds => ack_dw_wi(0 to NUM_WRITERS-1),
|
||||
opcode_dds => opcode_wi_dw(0 to NUM_WRITERS-1),
|
||||
instance_handle_in_dds => instance_handle_wi_dw(0 to NUM_WRITERS-1),
|
||||
source_ts_dds => source_ts_wi_dw(0 to NUM_WRITERS-1),
|
||||
max_wait_dds => max_wait_wi_dw(0 to NUM_WRITERS-1),
|
||||
done_dds => done_dw_wi(0 to NUM_WRITERS-1),
|
||||
return_code_dds => return_code_dw_wi(0 to NUM_WRITERS-1),
|
||||
instance_handle_out_dds => instance_handle_dw_wi(0 to NUM_WRITERS-1),
|
||||
valid_in_dds => valid_wi_dw(0 to NUM_WRITERS-1),
|
||||
ready_in_dds => ready_dw_wi(0 to NUM_WRITERS-1),
|
||||
data_in_dds => data_wi_dw(0 to NUM_WRITERS-1),
|
||||
last_word_in_dds => last_word_wi_dw(0 to NUM_WRITERS-1),
|
||||
valid_out_dds => valid_dw_wi(0 to NUM_WRITERS-1),
|
||||
ready_out_dds => ready_wi_dw(0 to NUM_WRITERS-1),
|
||||
data_out_dds => data_dw_wi(0 to NUM_WRITERS-1),
|
||||
last_word_out_dds => last_word_dw_wi(0 to NUM_WRITERS-1),
|
||||
-- Communication Status
|
||||
status => status_dw_wi(0 to NUM_WRITERS-1)
|
||||
);
|
||||
end generate;
|
||||
dds_endpoint_gen : for i in 0 to NUM_READERS-1 generate
|
||||
dds_reader_inst : entity work.dds_reader(arch)
|
||||
generic map (
|
||||
TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS,
|
||||
DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS,
|
||||
MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES,
|
||||
MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE,
|
||||
MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES,
|
||||
HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS,
|
||||
RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS,
|
||||
PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS,
|
||||
DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS,
|
||||
COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS,
|
||||
ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS,
|
||||
WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY,
|
||||
PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE,
|
||||
MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS
|
||||
)
|
||||
port map (
|
||||
-- SYSTEM
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
time => time,
|
||||
-- FROM RTPS ENDPOINT
|
||||
start_rtps => start_rr_dr(i),
|
||||
opcode_rtps => opcode_rr_dr(i),
|
||||
ack_rtps => ack_dr_rr(i),
|
||||
done_rtps => done_dr_rr(i),
|
||||
ret_rtps => ret_dr_rr(i),
|
||||
valid_in_rtps => valid_rr_dr(i),
|
||||
ready_in_rtps => ready_dr_rr(i),
|
||||
data_in_rtps => data_rr_dr(i),
|
||||
last_word_in_rtps => last_word_rr_dr(i),
|
||||
-- TO USER ENTITY
|
||||
start_dds => start_ri_dr(i),
|
||||
ack_dds => ack_dr_ri(i),
|
||||
opcode_dds => opcode_ri_dr(i),
|
||||
instance_state_dds => instance_state_ri_dr(i),
|
||||
view_state_dds => view_state_ri_dr(i),
|
||||
sample_state_dds => sample_state_ri_dr(i),
|
||||
instance_handle_dds => instance_handle_ri_dr(i),
|
||||
max_samples_dds => max_samples_ri_dr(i),
|
||||
get_data_dds => get_data_ri_dr(i),
|
||||
done_dds => done_dr_ri(i),
|
||||
return_code_dds => return_code_dr_ri(i),
|
||||
valid_out_dds => valid_dr_ri(i),
|
||||
ready_out_dds => ready_ri_dr(i),
|
||||
data_out_dds => data_dr_ri(i),
|
||||
last_word_out_dds => last_word_dr_ri(i),
|
||||
sample_info => sample_info_dr_ri(i),
|
||||
sample_info_valid => sample_info_valid_dr_ri(i),
|
||||
sample_info_ack => sample_info_ack_ri_dr(i),
|
||||
eoc => eoc_dr_ri(i),
|
||||
-- Communication Status
|
||||
status => status_dr_ri(i)
|
||||
);
|
||||
end generate;
|
||||
|
||||
|
||||
|
||||
@ -383,122 +383,114 @@ begin
|
||||
);
|
||||
end generate;
|
||||
|
||||
dds_endpoint_gen : for i in 0 to NUM_ENDPOINTS-1 generate
|
||||
dds_endpoint_if : if (i < NUM_READERS) generate
|
||||
dds_reader_inst : entity work.dds_reader(arch)
|
||||
generic map (
|
||||
TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS,
|
||||
DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS,
|
||||
MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES,
|
||||
MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE,
|
||||
MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES,
|
||||
HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS,
|
||||
RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS,
|
||||
PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS,
|
||||
DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS,
|
||||
COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS,
|
||||
ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS,
|
||||
WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY,
|
||||
PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE,
|
||||
MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS
|
||||
)
|
||||
port map (
|
||||
-- SYSTEM
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
time => time,
|
||||
-- FROM RTPS ENDPOINT
|
||||
start_rtps => start_rr_dr(i),
|
||||
opcode_rtps => opcode_rr_dr(i),
|
||||
ack_rtps => ack_dr_rr(i),
|
||||
done_rtps => done_dr_rr(i),
|
||||
ret_rtps => ret_dr_rr(i),
|
||||
valid_in_rtps => valid_rr_dr(i),
|
||||
ready_in_rtps => ready_dr_rr(i),
|
||||
data_in_rtps => data_rr_dr(i),
|
||||
last_word_in_rtps => last_word_rr_dr(i),
|
||||
-- TO USER ENTITY
|
||||
start_dds => start_ri_dr(i),
|
||||
ack_dds => ack_dr_ri(i),
|
||||
opcode_dds => opcode_ri_dr(i),
|
||||
instance_state_dds => instance_state_ri_dr(i),
|
||||
view_state_dds => view_state_ri_dr(i),
|
||||
sample_state_dds => sample_state_ri_dr(i),
|
||||
instance_handle_dds => instance_handle_ri_dr(i),
|
||||
max_samples_dds => max_samples_ri_dr(i),
|
||||
get_data_dds => get_data_ri_dr(i),
|
||||
done_dds => done_dr_ri(i),
|
||||
return_code_dds => return_code_dr_ri(i),
|
||||
valid_out_dds => valid_dr_ri(i),
|
||||
ready_out_dds => ready_ri_dr(i),
|
||||
data_out_dds => data_dr_ri(i),
|
||||
last_word_out_dds => last_word_dr_ri(i),
|
||||
sample_info => sample_info_dr_ri(i),
|
||||
sample_info_valid => sample_info_valid_dr_ri(i),
|
||||
sample_info_ack => sample_info_ack_ri_dr(i),
|
||||
eoc => eoc_dr_ri(i),
|
||||
-- Communication Status
|
||||
status => status_dr_ri(i)
|
||||
);
|
||||
else generate
|
||||
dds_writer_inst : entity work.dds_writer(arch)
|
||||
generic map (
|
||||
HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS,
|
||||
DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS,
|
||||
LIFESPAN_QOS => ENDPOINT_CONFIG(i).LIFESPAN_QOS,
|
||||
LEASE_DURATION => ENDPOINT_CONFIG(i).LEASE_DURATION,
|
||||
WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY,
|
||||
MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES,
|
||||
MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES,
|
||||
MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE,
|
||||
PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE
|
||||
)
|
||||
port map (
|
||||
-- SYSTEM
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
time => time,
|
||||
-- TO/FROM RTPS ENDPOINT
|
||||
start_rtps => start_rw_dw(i-NUM_READERS),
|
||||
opcode_rtps => opcode_rw_dw(i-NUM_READERS),
|
||||
ack_rtps => ack_dw_rw(i-NUM_READERS),
|
||||
done_rtps => done_rw_dw(i-NUM_READERS),
|
||||
ret_rtps => ret_dw_rw(i-NUM_READERS),
|
||||
seq_nr_rtps => seq_nr_rw_dw(i-NUM_READERS),
|
||||
get_data_rtps => get_data_rw_dw(i-NUM_READERS),
|
||||
valid_out_rtps => valid_dw_rw(i-NUM_READERS),
|
||||
ready_out_rtps => ready_rw_dw(i-NUM_READERS),
|
||||
data_out_rtps => data_dw_rw(i-NUM_READERS),
|
||||
last_word_out_rtps => last_word_dw_rw(i-NUM_READERS),
|
||||
liveliness_assertion => liveliness_assertion_dw_rw(i-NUM_READERS),
|
||||
data_available => data_available_dw_rw(i-NUM_READERS),
|
||||
-- Cache Change
|
||||
cc_instance_handle => cc_instance_handle_dw_rw(i-NUM_READERS),
|
||||
cc_kind => cc_kind_dw_rw(i-NUM_READERS),
|
||||
cc_source_timestamp => cc_source_timestamp_dw_rw(i-NUM_READERS),
|
||||
cc_seq_nr => cc_seq_nr_dw_rw(i-NUM_READERS),
|
||||
-- TO/FROM USER ENTITY
|
||||
start_dds => start_wi_dw(i-NUM_READERS),
|
||||
ack_dds => ack_dw_wi(i-NUM_READERS),
|
||||
opcode_dds => opcode_wi_dw(i-NUM_READERS),
|
||||
instance_handle_in_dds => instance_handle_wi_dw(i-NUM_READERS),
|
||||
source_ts_dds => source_ts_wi_dw(i-NUM_READERS),
|
||||
max_wait_dds => max_wait_wi_dw(i-NUM_READERS),
|
||||
done_dds => done_dw_wi(i-NUM_READERS),
|
||||
return_code_dds => return_code_dw_wi(i-NUM_READERS),
|
||||
instance_handle_out_dds => instance_handle_dw_wi(i-NUM_READERS),
|
||||
valid_in_dds => valid_wi_dw(i-NUM_READERS),
|
||||
ready_in_dds => ready_dw_wi(i-NUM_READERS),
|
||||
data_in_dds => data_wi_dw(i-NUM_READERS),
|
||||
last_word_in_dds => last_word_wi_dw(i-NUM_READERS),
|
||||
valid_out_dds => valid_dw_wi(i-NUM_READERS),
|
||||
ready_out_dds => ready_wi_dw(i-NUM_READERS),
|
||||
data_out_dds => data_dw_wi(i-NUM_READERS),
|
||||
last_word_out_dds => last_word_dw_wi(i-NUM_READERS),
|
||||
-- Communication Status
|
||||
status => status_dw_wi(i-NUM_READERS)
|
||||
);
|
||||
end generate;
|
||||
dds_endpoint_w_if : if (NUM_WRITERS > 0) generate
|
||||
dds_writer_inst : entity work.dds_writer(arch)
|
||||
generic map (
|
||||
NUM_WRITERS => NUM_WRITERS,
|
||||
CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(ENDPOINT_CONFIG(NUM_READERS to NUM_ENDPOINTS-1))
|
||||
)
|
||||
port map (
|
||||
-- SYSTEM
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
time => time,
|
||||
-- TO/FROM RTPS ENDPOINT
|
||||
start_rtps => start_rw_dw(0 to NUM_WRITERS-1),
|
||||
opcode_rtps => opcode_rw_dw(0 to NUM_WRITERS-1),
|
||||
ack_rtps => ack_dw_rw(0 to NUM_WRITERS-1),
|
||||
done_rtps => done_rw_dw(0 to NUM_WRITERS-1),
|
||||
ret_rtps => ret_dw_rw(0 to NUM_WRITERS-1),
|
||||
seq_nr_rtps => seq_nr_rw_dw(0 to NUM_WRITERS-1),
|
||||
get_data_rtps => get_data_rw_dw(0 to NUM_WRITERS-1),
|
||||
valid_out_rtps => valid_dw_rw(0 to NUM_WRITERS-1),
|
||||
ready_out_rtps => ready_rw_dw(0 to NUM_WRITERS-1),
|
||||
data_out_rtps => data_dw_rw(0 to NUM_WRITERS-1),
|
||||
last_word_out_rtps => last_word_dw_rw(0 to NUM_WRITERS-1),
|
||||
liveliness_assertion => liveliness_assertion_dw_rw(0 to NUM_WRITERS-1),
|
||||
data_available => data_available_dw_rw(0 to NUM_WRITERS-1),
|
||||
-- Cache Change
|
||||
cc_instance_handle => cc_instance_handle_dw_rw(0 to NUM_WRITERS-1),
|
||||
cc_kind => cc_kind_dw_rw(0 to NUM_WRITERS-1),
|
||||
cc_source_timestamp => cc_source_timestamp_dw_rw(0 to NUM_WRITERS-1),
|
||||
cc_seq_nr => cc_seq_nr_dw_rw(0 to NUM_WRITERS-1),
|
||||
-- TO/FROM USER ENTITY
|
||||
start_dds => start_wi_dw(0 to NUM_WRITERS-1),
|
||||
ack_dds => ack_dw_wi(0 to NUM_WRITERS-1),
|
||||
opcode_dds => opcode_wi_dw(0 to NUM_WRITERS-1),
|
||||
instance_handle_in_dds => instance_handle_wi_dw(0 to NUM_WRITERS-1),
|
||||
source_ts_dds => source_ts_wi_dw(0 to NUM_WRITERS-1),
|
||||
max_wait_dds => max_wait_wi_dw(0 to NUM_WRITERS-1),
|
||||
done_dds => done_dw_wi(0 to NUM_WRITERS-1),
|
||||
return_code_dds => return_code_dw_wi(0 to NUM_WRITERS-1),
|
||||
instance_handle_out_dds => instance_handle_dw_wi(0 to NUM_WRITERS-1),
|
||||
valid_in_dds => valid_wi_dw(0 to NUM_WRITERS-1),
|
||||
ready_in_dds => ready_dw_wi(0 to NUM_WRITERS-1),
|
||||
data_in_dds => data_wi_dw(0 to NUM_WRITERS-1),
|
||||
last_word_in_dds => last_word_wi_dw(0 to NUM_WRITERS-1),
|
||||
valid_out_dds => valid_dw_wi(0 to NUM_WRITERS-1),
|
||||
ready_out_dds => ready_wi_dw(0 to NUM_WRITERS-1),
|
||||
data_out_dds => data_dw_wi(0 to NUM_WRITERS-1),
|
||||
last_word_out_dds => last_word_dw_wi(0 to NUM_WRITERS-1),
|
||||
-- Communication Status
|
||||
status => status_dw_wi(0 to NUM_WRITERS-1)
|
||||
);
|
||||
end generate;
|
||||
dds_endpoint_gen : for i in 0 to NUM_READERS-1 generate
|
||||
dds_reader_inst : entity work.dds_reader(arch)
|
||||
generic map (
|
||||
TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS,
|
||||
DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS,
|
||||
MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES,
|
||||
MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE,
|
||||
MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES,
|
||||
HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS,
|
||||
RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS,
|
||||
PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS,
|
||||
DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS,
|
||||
COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS,
|
||||
ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS,
|
||||
WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY,
|
||||
PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE,
|
||||
MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS
|
||||
)
|
||||
port map (
|
||||
-- SYSTEM
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
time => time,
|
||||
-- FROM RTPS ENDPOINT
|
||||
start_rtps => start_rr_dr(i),
|
||||
opcode_rtps => opcode_rr_dr(i),
|
||||
ack_rtps => ack_dr_rr(i),
|
||||
done_rtps => done_dr_rr(i),
|
||||
ret_rtps => ret_dr_rr(i),
|
||||
valid_in_rtps => valid_rr_dr(i),
|
||||
ready_in_rtps => ready_dr_rr(i),
|
||||
data_in_rtps => data_rr_dr(i),
|
||||
last_word_in_rtps => last_word_rr_dr(i),
|
||||
-- TO USER ENTITY
|
||||
start_dds => start_ri_dr(i),
|
||||
ack_dds => ack_dr_ri(i),
|
||||
opcode_dds => opcode_ri_dr(i),
|
||||
instance_state_dds => instance_state_ri_dr(i),
|
||||
view_state_dds => view_state_ri_dr(i),
|
||||
sample_state_dds => sample_state_ri_dr(i),
|
||||
instance_handle_dds => instance_handle_ri_dr(i),
|
||||
max_samples_dds => max_samples_ri_dr(i),
|
||||
get_data_dds => get_data_ri_dr(i),
|
||||
done_dds => done_dr_ri(i),
|
||||
return_code_dds => return_code_dr_ri(i),
|
||||
valid_out_dds => valid_dr_ri(i),
|
||||
ready_out_dds => ready_ri_dr(i),
|
||||
data_out_dds => data_dr_ri(i),
|
||||
last_word_out_dds => last_word_dr_ri(i),
|
||||
sample_info => sample_info_dr_ri(i),
|
||||
sample_info_valid => sample_info_valid_dr_ri(i),
|
||||
sample_info_ack => sample_info_ack_ri_dr(i),
|
||||
eoc => eoc_dr_ri(i),
|
||||
-- Communication Status
|
||||
status => status_dr_ri(i)
|
||||
);
|
||||
end generate;
|
||||
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
configuration key_holder_conf1 of dds_writer is
|
||||
for arch
|
||||
for key_holder_inst : key_holder
|
||||
for all : key_holder
|
||||
use entity work.key_holder(TYPE1);
|
||||
end for;
|
||||
end for;
|
||||
@ -8,7 +8,7 @@ end configuration;
|
||||
|
||||
configuration key_holder_conf2 of dds_reader is
|
||||
for arch
|
||||
for key_holder_inst : key_holder
|
||||
for all : key_holder
|
||||
use entity work.key_holder(TYPE1);
|
||||
end for;
|
||||
end for;
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
configuration key_holder_conf1 of dds_writer is
|
||||
for arch
|
||||
for key_holder_inst : key_holder
|
||||
for all : key_holder
|
||||
use entity work.key_holder(test);
|
||||
end for;
|
||||
end for;
|
||||
@ -8,7 +8,7 @@ end configuration;
|
||||
|
||||
configuration key_holder_conf2 of dds_reader is
|
||||
for arch
|
||||
for key_holder_inst : key_holder
|
||||
for all : key_holder
|
||||
use entity work.key_holder(test);
|
||||
end for;
|
||||
end for;
|
||||
|
||||
@ -204,15 +204,11 @@ analyze Level_0/L0_rtps_writer_test2.vhd
|
||||
analyze Level_1/L1_rtps_writer_test1.vhd
|
||||
analyze Level_1/L1_rtps_writer_test2.vhd
|
||||
analyze Level_1/L1_rtps_writer_test3.vhd
|
||||
analyze Level_0/L0_dds_writer_test1_aik.vhd
|
||||
analyze Level_0/L0_dds_writer_test1_ain.vhd
|
||||
analyze Level_0/L0_dds_writer_test1_lik.vhd
|
||||
analyze Level_0/L0_dds_writer_test1_afk.vhd
|
||||
analyze Level_0/L0_dds_writer_test2_aik.vhd
|
||||
analyze Level_0/L0_dds_writer_test3_aik.vhd
|
||||
analyze Level_0/L0_dds_writer_test3_ain.vhd
|
||||
analyze Level_0/L0_dds_writer_test4_aik.vhd
|
||||
analyze Level_0/L0_dds_writer_test5_afk.vhd
|
||||
analyze Level_0/L0_dds_writer_test1.vhd
|
||||
analyze Level_0/L0_dds_writer_test2.vhd
|
||||
analyze Level_0/L0_dds_writer_test3.vhd
|
||||
analyze Level_0/L0_dds_writer_test4.vhd
|
||||
analyze Level_0/L0_dds_writer_test5.vhd
|
||||
analyze Level_0/L0_dds_reader_test1_arzkriu.vhd
|
||||
analyze Level_0/L0_dds_reader_test1_lrzkriu.vhd
|
||||
analyze Level_0/L0_dds_reader_test1_lbzkriu.vhd
|
||||
@ -265,15 +261,11 @@ simulate L0_rtps_writer_test2
|
||||
simulate L1_rtps_writer_test1
|
||||
simulate L1_rtps_writer_test2
|
||||
simulate L1_rtps_writer_test3
|
||||
simulate L0_dds_writer_test1_aik
|
||||
simulate L0_dds_writer_test1_ain
|
||||
simulate L0_dds_writer_test1_lik
|
||||
simulate L0_dds_writer_test1_afk
|
||||
simulate L0_dds_writer_test2_aik
|
||||
simulate L0_dds_writer_test3_aik
|
||||
simulate L0_dds_writer_test3_ain
|
||||
simulate L0_dds_writer_test4_aik
|
||||
simulate L0_dds_writer_test5_afk
|
||||
simulate L0_dds_writer_test1
|
||||
simulate L0_dds_writer_test2
|
||||
simulate L0_dds_writer_test3
|
||||
simulate L0_dds_writer_test4
|
||||
simulate L0_dds_writer_test5
|
||||
simulate L0_dds_reader_test1_arzkriu
|
||||
simulate L0_dds_reader_test1_lrzkriu
|
||||
simulate L0_dds_reader_test1_lbzkriu
|
||||
|
||||
5093
src/dds_writer.vhd
5093
src/dds_writer.vhd
File diff suppressed because it is too large
Load Diff
@ -358,122 +358,114 @@ begin
|
||||
);
|
||||
end generate;
|
||||
|
||||
dds_endpoint_gen : for i in 0 to NUM_ENDPOINTS-2 generate
|
||||
dds_endpoint_if : if (i < NUM_READERS) generate
|
||||
dds_reader_inst : entity work.dds_reader(arch)
|
||||
generic map (
|
||||
TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS,
|
||||
DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS,
|
||||
MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES,
|
||||
MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE,
|
||||
MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES,
|
||||
HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS,
|
||||
RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS,
|
||||
PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS,
|
||||
DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS,
|
||||
COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS,
|
||||
ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS,
|
||||
WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY,
|
||||
PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE,
|
||||
MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS
|
||||
)
|
||||
port map (
|
||||
-- SYSTEM
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
time => time,
|
||||
-- FROM RTPS ENDPOINT
|
||||
start_rtps => start_rr_dr(i),
|
||||
opcode_rtps => opcode_rr_dr(i),
|
||||
ack_rtps => ack_dr_rr(i),
|
||||
done_rtps => done_dr_rr(i),
|
||||
ret_rtps => ret_dr_rr(i),
|
||||
valid_in_rtps => valid_rr_dr(i),
|
||||
ready_in_rtps => ready_dr_rr(i),
|
||||
data_in_rtps => data_rr_dr(i),
|
||||
last_word_in_rtps => last_word_rr_dr(i),
|
||||
-- TO USER ENTITY
|
||||
start_dds => start_ri_dr(i),
|
||||
ack_dds => ack_dr_ri(i),
|
||||
opcode_dds => opcode_ri_dr(i),
|
||||
instance_state_dds => instance_state_ri_dr(i),
|
||||
view_state_dds => view_state_ri_dr(i),
|
||||
sample_state_dds => sample_state_ri_dr(i),
|
||||
instance_handle_dds => instance_handle_ri_dr(i),
|
||||
max_samples_dds => max_samples_ri_dr(i),
|
||||
get_data_dds => get_data_ri_dr(i),
|
||||
done_dds => done_dr_ri(i),
|
||||
return_code_dds => return_code_dr_ri(i),
|
||||
valid_out_dds => valid_dr_ri(i),
|
||||
ready_out_dds => ready_ri_dr(i),
|
||||
data_out_dds => data_dr_ri(i),
|
||||
last_word_out_dds => last_word_dr_ri(i),
|
||||
sample_info => sample_info_dr_ri(i),
|
||||
sample_info_valid => sample_info_valid_dr_ri(i),
|
||||
sample_info_ack => sample_info_ack_ri_dr(i),
|
||||
eoc => eoc_dr_ri(i),
|
||||
-- Communication Status
|
||||
status => status_dr_ri(i)
|
||||
);
|
||||
else generate
|
||||
dds_writer_inst : entity work.dds_writer(arch)
|
||||
generic map (
|
||||
HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS,
|
||||
DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS,
|
||||
LIFESPAN_QOS => ENDPOINT_CONFIG(i).LIFESPAN_QOS,
|
||||
LEASE_DURATION => ENDPOINT_CONFIG(i).LEASE_DURATION,
|
||||
WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY,
|
||||
MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES,
|
||||
MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES,
|
||||
MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE,
|
||||
PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE
|
||||
)
|
||||
port map (
|
||||
-- SYSTEM
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
time => time,
|
||||
-- TO/FROM RTPS ENDPOINT
|
||||
start_rtps => start_rw_dw(i-NUM_READERS),
|
||||
opcode_rtps => opcode_rw_dw(i-NUM_READERS),
|
||||
ack_rtps => ack_dw_rw(i-NUM_READERS),
|
||||
done_rtps => done_rw_dw(i-NUM_READERS),
|
||||
ret_rtps => ret_dw_rw(i-NUM_READERS),
|
||||
seq_nr_rtps => seq_nr_rw_dw(i-NUM_READERS),
|
||||
get_data_rtps => get_data_rw_dw(i-NUM_READERS),
|
||||
valid_out_rtps => valid_dw_rw(i-NUM_READERS),
|
||||
ready_out_rtps => ready_rw_dw(i-NUM_READERS),
|
||||
data_out_rtps => data_dw_rw(i-NUM_READERS),
|
||||
last_word_out_rtps => last_word_dw_rw(i-NUM_READERS),
|
||||
liveliness_assertion => liveliness_assertion_dw_rw(i-NUM_READERS),
|
||||
data_available => data_available_dw_rw(i-NUM_READERS),
|
||||
-- Cache Change
|
||||
cc_instance_handle => cc_instance_handle_dw_rw(i-NUM_READERS),
|
||||
cc_kind => cc_kind_dw_rw(i-NUM_READERS),
|
||||
cc_source_timestamp => cc_source_timestamp_dw_rw(i-NUM_READERS),
|
||||
cc_seq_nr => cc_seq_nr_dw_rw(i-NUM_READERS),
|
||||
-- TO/FROM USER ENTITY
|
||||
start_dds => start_wi_dw(i-NUM_READERS),
|
||||
ack_dds => ack_dw_wi(i-NUM_READERS),
|
||||
opcode_dds => opcode_wi_dw(i-NUM_READERS),
|
||||
instance_handle_in_dds => instance_handle_wi_dw(i-NUM_READERS),
|
||||
source_ts_dds => source_ts_wi_dw(i-NUM_READERS),
|
||||
max_wait_dds => max_wait_wi_dw(i-NUM_READERS),
|
||||
done_dds => done_dw_wi(i-NUM_READERS),
|
||||
return_code_dds => return_code_dw_wi(i-NUM_READERS),
|
||||
instance_handle_out_dds => instance_handle_dw_wi(i-NUM_READERS),
|
||||
valid_in_dds => valid_wi_dw(i-NUM_READERS),
|
||||
ready_in_dds => ready_dw_wi(i-NUM_READERS),
|
||||
data_in_dds => data_wi_dw(i-NUM_READERS),
|
||||
last_word_in_dds => last_word_wi_dw(i-NUM_READERS),
|
||||
valid_out_dds => valid_dw_wi(i-NUM_READERS),
|
||||
ready_out_dds => ready_wi_dw(i-NUM_READERS),
|
||||
data_out_dds => data_dw_wi(i-NUM_READERS),
|
||||
last_word_out_dds => last_word_dw_wi(i-NUM_READERS),
|
||||
-- Communication Status
|
||||
status => status_dw_wi(i-NUM_READERS)
|
||||
);
|
||||
end generate;
|
||||
dds_endpoint_w_if : if (NUM_WRITERS > 1) generate
|
||||
dds_writer_inst : entity work.dds_writer(arch)
|
||||
generic map (
|
||||
NUM_WRITERS => NUM_WRITERS-1,
|
||||
CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(ENDPOINT_CONFIG(NUM_READERS to NUM_ENDPOINTS-2))
|
||||
)
|
||||
port map (
|
||||
-- SYSTEM
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
time => time,
|
||||
-- TO/FROM RTPS ENDPOINT
|
||||
start_rtps => start_rw_dw(0 to NUM_WRITERS-2),
|
||||
opcode_rtps => opcode_rw_dw(0 to NUM_WRITERS-2),
|
||||
ack_rtps => ack_dw_rw(0 to NUM_WRITERS-2),
|
||||
done_rtps => done_rw_dw(0 to NUM_WRITERS-2),
|
||||
ret_rtps => ret_dw_rw(0 to NUM_WRITERS-2),
|
||||
seq_nr_rtps => seq_nr_rw_dw(0 to NUM_WRITERS-2),
|
||||
get_data_rtps => get_data_rw_dw(0 to NUM_WRITERS-2),
|
||||
valid_out_rtps => valid_dw_rw(0 to NUM_WRITERS-2),
|
||||
ready_out_rtps => ready_rw_dw(0 to NUM_WRITERS-2),
|
||||
data_out_rtps => data_dw_rw(0 to NUM_WRITERS-2),
|
||||
last_word_out_rtps => last_word_dw_rw(0 to NUM_WRITERS-2),
|
||||
liveliness_assertion => liveliness_assertion_dw_rw(0 to NUM_WRITERS-2),
|
||||
data_available => data_available_dw_rw(0 to NUM_WRITERS-2),
|
||||
-- Cache Change
|
||||
cc_instance_handle => cc_instance_handle_dw_rw(0 to NUM_WRITERS-2),
|
||||
cc_kind => cc_kind_dw_rw(0 to NUM_WRITERS-2),
|
||||
cc_source_timestamp => cc_source_timestamp_dw_rw(0 to NUM_WRITERS-2),
|
||||
cc_seq_nr => cc_seq_nr_dw_rw(0 to NUM_WRITERS-2),
|
||||
-- TO/FROM USER ENTITY
|
||||
start_dds => start_wi_dw(0 to NUM_WRITERS-2),
|
||||
ack_dds => ack_dw_wi(0 to NUM_WRITERS-2),
|
||||
opcode_dds => opcode_wi_dw(0 to NUM_WRITERS-2),
|
||||
instance_handle_in_dds => instance_handle_wi_dw(0 to NUM_WRITERS-2),
|
||||
source_ts_dds => source_ts_wi_dw(0 to NUM_WRITERS-2),
|
||||
max_wait_dds => max_wait_wi_dw(0 to NUM_WRITERS-2),
|
||||
done_dds => done_dw_wi(0 to NUM_WRITERS-2),
|
||||
return_code_dds => return_code_dw_wi(0 to NUM_WRITERS-2),
|
||||
instance_handle_out_dds => instance_handle_dw_wi(0 to NUM_WRITERS-2),
|
||||
valid_in_dds => valid_wi_dw(0 to NUM_WRITERS-2),
|
||||
ready_in_dds => ready_dw_wi(0 to NUM_WRITERS-2),
|
||||
data_in_dds => data_wi_dw(0 to NUM_WRITERS-2),
|
||||
last_word_in_dds => last_word_wi_dw(0 to NUM_WRITERS-2),
|
||||
valid_out_dds => valid_dw_wi(0 to NUM_WRITERS-2),
|
||||
ready_out_dds => ready_wi_dw(0 to NUM_WRITERS-2),
|
||||
data_out_dds => data_dw_wi(0 to NUM_WRITERS-2),
|
||||
last_word_out_dds => last_word_dw_wi(0 to NUM_WRITERS-2),
|
||||
-- Communication Status
|
||||
status => status_dw_wi(0 to NUM_WRITERS-2)
|
||||
);
|
||||
end generate;
|
||||
dds_endpoint_gen : for i in 0 to NUM_READERS-1 generate
|
||||
dds_reader_inst : entity work.dds_reader(arch)
|
||||
generic map (
|
||||
TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS,
|
||||
DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS,
|
||||
MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES,
|
||||
MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE,
|
||||
MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES,
|
||||
HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS,
|
||||
RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS,
|
||||
PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS,
|
||||
DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS,
|
||||
COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS,
|
||||
ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS,
|
||||
WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY,
|
||||
PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE,
|
||||
MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS
|
||||
)
|
||||
port map (
|
||||
-- SYSTEM
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
time => time,
|
||||
-- FROM RTPS ENDPOINT
|
||||
start_rtps => start_rr_dr(i),
|
||||
opcode_rtps => opcode_rr_dr(i),
|
||||
ack_rtps => ack_dr_rr(i),
|
||||
done_rtps => done_dr_rr(i),
|
||||
ret_rtps => ret_dr_rr(i),
|
||||
valid_in_rtps => valid_rr_dr(i),
|
||||
ready_in_rtps => ready_dr_rr(i),
|
||||
data_in_rtps => data_rr_dr(i),
|
||||
last_word_in_rtps => last_word_rr_dr(i),
|
||||
-- TO USER ENTITY
|
||||
start_dds => start_ri_dr(i),
|
||||
ack_dds => ack_dr_ri(i),
|
||||
opcode_dds => opcode_ri_dr(i),
|
||||
instance_state_dds => instance_state_ri_dr(i),
|
||||
view_state_dds => view_state_ri_dr(i),
|
||||
sample_state_dds => sample_state_ri_dr(i),
|
||||
instance_handle_dds => instance_handle_ri_dr(i),
|
||||
max_samples_dds => max_samples_ri_dr(i),
|
||||
get_data_dds => get_data_ri_dr(i),
|
||||
done_dds => done_dr_ri(i),
|
||||
return_code_dds => return_code_dr_ri(i),
|
||||
valid_out_dds => valid_dr_ri(i),
|
||||
ready_out_dds => ready_ri_dr(i),
|
||||
data_out_dds => data_dr_ri(i),
|
||||
last_word_out_dds => last_word_dr_ri(i),
|
||||
sample_info => sample_info_dr_ri(i),
|
||||
sample_info_valid => sample_info_valid_dr_ri(i),
|
||||
sample_info_ack => sample_info_ack_ri_dr(i),
|
||||
eoc => eoc_dr_ri(i),
|
||||
-- Communication Status
|
||||
status => status_dr_ri(i)
|
||||
);
|
||||
end generate;
|
||||
|
||||
|
||||
|
||||
@ -366,122 +366,114 @@ begin
|
||||
);
|
||||
end generate;
|
||||
|
||||
dds_endpoint_gen : for i in 0 to NUM_ENDPOINTS-2 generate
|
||||
dds_endpoint_if : if (i < NUM_READERS) generate
|
||||
dds_reader_inst : entity work.dds_reader(arch)
|
||||
generic map (
|
||||
TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS,
|
||||
DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS,
|
||||
MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES,
|
||||
MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE,
|
||||
MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES,
|
||||
HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS,
|
||||
RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS,
|
||||
PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS,
|
||||
DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS,
|
||||
COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS,
|
||||
ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS,
|
||||
WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY,
|
||||
PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE,
|
||||
MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS
|
||||
)
|
||||
port map (
|
||||
-- SYSTEM
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
time => time,
|
||||
-- FROM RTPS ENDPOINT
|
||||
start_rtps => start_rr_dr(i),
|
||||
opcode_rtps => opcode_rr_dr(i),
|
||||
ack_rtps => ack_dr_rr(i),
|
||||
done_rtps => done_dr_rr(i),
|
||||
ret_rtps => ret_dr_rr(i),
|
||||
valid_in_rtps => valid_rr_dr(i),
|
||||
ready_in_rtps => ready_dr_rr(i),
|
||||
data_in_rtps => data_rr_dr(i),
|
||||
last_word_in_rtps => last_word_rr_dr(i),
|
||||
-- TO USER ENTITY
|
||||
start_dds => start_ri_dr(i),
|
||||
ack_dds => ack_dr_ri(i),
|
||||
opcode_dds => opcode_ri_dr(i),
|
||||
instance_state_dds => instance_state_ri_dr(i),
|
||||
view_state_dds => view_state_ri_dr(i),
|
||||
sample_state_dds => sample_state_ri_dr(i),
|
||||
instance_handle_dds => instance_handle_ri_dr(i),
|
||||
max_samples_dds => max_samples_ri_dr(i),
|
||||
get_data_dds => get_data_ri_dr(i),
|
||||
done_dds => done_dr_ri(i),
|
||||
return_code_dds => return_code_dr_ri(i),
|
||||
valid_out_dds => valid_dr_ri(i),
|
||||
ready_out_dds => ready_ri_dr(i),
|
||||
data_out_dds => data_dr_ri(i),
|
||||
last_word_out_dds => last_word_dr_ri(i),
|
||||
sample_info => sample_info_dr_ri(i),
|
||||
sample_info_valid => sample_info_valid_dr_ri(i),
|
||||
sample_info_ack => sample_info_ack_ri_dr(i),
|
||||
eoc => eoc_dr_ri(i),
|
||||
-- Communication Status
|
||||
status => status_dr_ri(i)
|
||||
);
|
||||
else generate
|
||||
dds_writer_inst : entity work.dds_writer(arch)
|
||||
generic map (
|
||||
HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS,
|
||||
DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS,
|
||||
LIFESPAN_QOS => ENDPOINT_CONFIG(i).LIFESPAN_QOS,
|
||||
LEASE_DURATION => ENDPOINT_CONFIG(i).LEASE_DURATION,
|
||||
WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY,
|
||||
MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES,
|
||||
MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES,
|
||||
MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE,
|
||||
PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE
|
||||
)
|
||||
port map (
|
||||
-- SYSTEM
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
time => time,
|
||||
-- TO/FROM RTPS ENDPOINT
|
||||
start_rtps => start_rw_dw(i-NUM_READERS),
|
||||
opcode_rtps => opcode_rw_dw(i-NUM_READERS),
|
||||
ack_rtps => ack_dw_rw(i-NUM_READERS),
|
||||
done_rtps => done_rw_dw(i-NUM_READERS),
|
||||
ret_rtps => ret_dw_rw(i-NUM_READERS),
|
||||
seq_nr_rtps => seq_nr_rw_dw(i-NUM_READERS),
|
||||
get_data_rtps => get_data_rw_dw(i-NUM_READERS),
|
||||
valid_out_rtps => valid_dw_rw(i-NUM_READERS),
|
||||
ready_out_rtps => ready_rw_dw(i-NUM_READERS),
|
||||
data_out_rtps => data_dw_rw(i-NUM_READERS),
|
||||
last_word_out_rtps => last_word_dw_rw(i-NUM_READERS),
|
||||
liveliness_assertion => liveliness_assertion_dw_rw(i-NUM_READERS),
|
||||
data_available => data_available_dw_rw(i-NUM_READERS),
|
||||
-- Cache Change
|
||||
cc_instance_handle => cc_instance_handle_dw_rw(i-NUM_READERS),
|
||||
cc_kind => cc_kind_dw_rw(i-NUM_READERS),
|
||||
cc_source_timestamp => cc_source_timestamp_dw_rw(i-NUM_READERS),
|
||||
cc_seq_nr => cc_seq_nr_dw_rw(i-NUM_READERS),
|
||||
-- TO/FROM USER ENTITY
|
||||
start_dds => start_wi_dw(i-NUM_READERS),
|
||||
ack_dds => ack_dw_wi(i-NUM_READERS),
|
||||
opcode_dds => opcode_wi_dw(i-NUM_READERS),
|
||||
instance_handle_in_dds => instance_handle_wi_dw(i-NUM_READERS),
|
||||
source_ts_dds => source_ts_wi_dw(i-NUM_READERS),
|
||||
max_wait_dds => max_wait_wi_dw(i-NUM_READERS),
|
||||
done_dds => done_dw_wi(i-NUM_READERS),
|
||||
return_code_dds => return_code_dw_wi(i-NUM_READERS),
|
||||
instance_handle_out_dds => instance_handle_dw_wi(i-NUM_READERS),
|
||||
valid_in_dds => valid_wi_dw(i-NUM_READERS),
|
||||
ready_in_dds => ready_dw_wi(i-NUM_READERS),
|
||||
data_in_dds => data_wi_dw(i-NUM_READERS),
|
||||
last_word_in_dds => last_word_wi_dw(i-NUM_READERS),
|
||||
valid_out_dds => valid_dw_wi(i-NUM_READERS),
|
||||
ready_out_dds => ready_wi_dw(i-NUM_READERS),
|
||||
data_out_dds => data_dw_wi(i-NUM_READERS),
|
||||
last_word_out_dds => last_word_dw_wi(i-NUM_READERS),
|
||||
-- Communication Status
|
||||
status => status_dw_wi(i-NUM_READERS)
|
||||
);
|
||||
end generate;
|
||||
dds_endpoint_w_if : if (NUM_WRITERS > 1) generate
|
||||
dds_writer_inst : entity work.dds_writer(arch)
|
||||
generic map (
|
||||
NUM_WRITERS => NUM_WRITERS-1,
|
||||
CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(ENDPOINT_CONFIG(NUM_READERS to NUM_ENDPOINTS-2))
|
||||
)
|
||||
port map (
|
||||
-- SYSTEM
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
time => time,
|
||||
-- TO/FROM RTPS ENDPOINT
|
||||
start_rtps => start_rw_dw(0 to NUM_WRITERS-2),
|
||||
opcode_rtps => opcode_rw_dw(0 to NUM_WRITERS-2),
|
||||
ack_rtps => ack_dw_rw(0 to NUM_WRITERS-2),
|
||||
done_rtps => done_rw_dw(0 to NUM_WRITERS-2),
|
||||
ret_rtps => ret_dw_rw(0 to NUM_WRITERS-2),
|
||||
seq_nr_rtps => seq_nr_rw_dw(0 to NUM_WRITERS-2),
|
||||
get_data_rtps => get_data_rw_dw(0 to NUM_WRITERS-2),
|
||||
valid_out_rtps => valid_dw_rw(0 to NUM_WRITERS-2),
|
||||
ready_out_rtps => ready_rw_dw(0 to NUM_WRITERS-2),
|
||||
data_out_rtps => data_dw_rw(0 to NUM_WRITERS-2),
|
||||
last_word_out_rtps => last_word_dw_rw(0 to NUM_WRITERS-2),
|
||||
liveliness_assertion => liveliness_assertion_dw_rw(0 to NUM_WRITERS-2),
|
||||
data_available => data_available_dw_rw(0 to NUM_WRITERS-2),
|
||||
-- Cache Change
|
||||
cc_instance_handle => cc_instance_handle_dw_rw(0 to NUM_WRITERS-2),
|
||||
cc_kind => cc_kind_dw_rw(0 to NUM_WRITERS-2),
|
||||
cc_source_timestamp => cc_source_timestamp_dw_rw(0 to NUM_WRITERS-2),
|
||||
cc_seq_nr => cc_seq_nr_dw_rw(0 to NUM_WRITERS-2),
|
||||
-- TO/FROM USER ENTITY
|
||||
start_dds => start_wi_dw(0 to NUM_WRITERS-2),
|
||||
ack_dds => ack_dw_wi(0 to NUM_WRITERS-2),
|
||||
opcode_dds => opcode_wi_dw(0 to NUM_WRITERS-2),
|
||||
instance_handle_in_dds => instance_handle_wi_dw(0 to NUM_WRITERS-2),
|
||||
source_ts_dds => source_ts_wi_dw(0 to NUM_WRITERS-2),
|
||||
max_wait_dds => max_wait_wi_dw(0 to NUM_WRITERS-2),
|
||||
done_dds => done_dw_wi(0 to NUM_WRITERS-2),
|
||||
return_code_dds => return_code_dw_wi(0 to NUM_WRITERS-2),
|
||||
instance_handle_out_dds => instance_handle_dw_wi(0 to NUM_WRITERS-2),
|
||||
valid_in_dds => valid_wi_dw(0 to NUM_WRITERS-2),
|
||||
ready_in_dds => ready_dw_wi(0 to NUM_WRITERS-2),
|
||||
data_in_dds => data_wi_dw(0 to NUM_WRITERS-2),
|
||||
last_word_in_dds => last_word_wi_dw(0 to NUM_WRITERS-2),
|
||||
valid_out_dds => valid_dw_wi(0 to NUM_WRITERS-2),
|
||||
ready_out_dds => ready_wi_dw(0 to NUM_WRITERS-2),
|
||||
data_out_dds => data_dw_wi(0 to NUM_WRITERS-2),
|
||||
last_word_out_dds => last_word_dw_wi(0 to NUM_WRITERS-2),
|
||||
-- Communication Status
|
||||
status => status_dw_wi(0 to NUM_WRITERS-2)
|
||||
);
|
||||
end generate;
|
||||
dds_endpoint_gen : for i in 0 to NUM_READERS-1 generate
|
||||
dds_reader_inst : entity work.dds_reader(arch)
|
||||
generic map (
|
||||
TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS,
|
||||
DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS,
|
||||
MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES,
|
||||
MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE,
|
||||
MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES,
|
||||
HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS,
|
||||
RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS,
|
||||
PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS,
|
||||
DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS,
|
||||
COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS,
|
||||
ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS,
|
||||
WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY,
|
||||
PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE,
|
||||
MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS
|
||||
)
|
||||
port map (
|
||||
-- SYSTEM
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
time => time,
|
||||
-- FROM RTPS ENDPOINT
|
||||
start_rtps => start_rr_dr(i),
|
||||
opcode_rtps => opcode_rr_dr(i),
|
||||
ack_rtps => ack_dr_rr(i),
|
||||
done_rtps => done_dr_rr(i),
|
||||
ret_rtps => ret_dr_rr(i),
|
||||
valid_in_rtps => valid_rr_dr(i),
|
||||
ready_in_rtps => ready_dr_rr(i),
|
||||
data_in_rtps => data_rr_dr(i),
|
||||
last_word_in_rtps => last_word_rr_dr(i),
|
||||
-- TO USER ENTITY
|
||||
start_dds => start_ri_dr(i),
|
||||
ack_dds => ack_dr_ri(i),
|
||||
opcode_dds => opcode_ri_dr(i),
|
||||
instance_state_dds => instance_state_ri_dr(i),
|
||||
view_state_dds => view_state_ri_dr(i),
|
||||
sample_state_dds => sample_state_ri_dr(i),
|
||||
instance_handle_dds => instance_handle_ri_dr(i),
|
||||
max_samples_dds => max_samples_ri_dr(i),
|
||||
get_data_dds => get_data_ri_dr(i),
|
||||
done_dds => done_dr_ri(i),
|
||||
return_code_dds => return_code_dr_ri(i),
|
||||
valid_out_dds => valid_dr_ri(i),
|
||||
ready_out_dds => ready_ri_dr(i),
|
||||
data_out_dds => data_dr_ri(i),
|
||||
last_word_out_dds => last_word_dr_ri(i),
|
||||
sample_info => sample_info_dr_ri(i),
|
||||
sample_info_valid => sample_info_valid_dr_ri(i),
|
||||
sample_info_ack => sample_info_ack_ri_dr(i),
|
||||
eoc => eoc_dr_ri(i),
|
||||
-- Communication Status
|
||||
status => status_dr_ri(i)
|
||||
);
|
||||
end generate;
|
||||
|
||||
|
||||
|
||||
@ -369,122 +369,114 @@ begin
|
||||
);
|
||||
end generate;
|
||||
|
||||
dds_endpoint_gen : for i in 0 to NUM_ENDPOINTS-2 generate
|
||||
dds_endpoint_if : if (i < NUM_READERS) generate
|
||||
dds_reader_inst : entity work.dds_reader(arch)
|
||||
generic map (
|
||||
TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS,
|
||||
DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS,
|
||||
MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES,
|
||||
MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE,
|
||||
MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES,
|
||||
HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS,
|
||||
RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS,
|
||||
PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS,
|
||||
DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS,
|
||||
COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS,
|
||||
ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS,
|
||||
WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY,
|
||||
PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE,
|
||||
MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS
|
||||
)
|
||||
port map (
|
||||
-- SYSTEM
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
time => time,
|
||||
-- FROM RTPS ENDPOINT
|
||||
start_rtps => start_rr_dr(i),
|
||||
opcode_rtps => opcode_rr_dr(i),
|
||||
ack_rtps => ack_dr_rr(i),
|
||||
done_rtps => done_dr_rr(i),
|
||||
ret_rtps => ret_dr_rr(i),
|
||||
valid_in_rtps => valid_rr_dr(i),
|
||||
ready_in_rtps => ready_dr_rr(i),
|
||||
data_in_rtps => data_rr_dr(i),
|
||||
last_word_in_rtps => last_word_rr_dr(i),
|
||||
-- TO USER ENTITY
|
||||
start_dds => start_ri_dr(i),
|
||||
ack_dds => ack_dr_ri(i),
|
||||
opcode_dds => opcode_ri_dr(i),
|
||||
instance_state_dds => instance_state_ri_dr(i),
|
||||
view_state_dds => view_state_ri_dr(i),
|
||||
sample_state_dds => sample_state_ri_dr(i),
|
||||
instance_handle_dds => instance_handle_ri_dr(i),
|
||||
max_samples_dds => max_samples_ri_dr(i),
|
||||
get_data_dds => get_data_ri_dr(i),
|
||||
done_dds => done_dr_ri(i),
|
||||
return_code_dds => return_code_dr_ri(i),
|
||||
valid_out_dds => valid_dr_ri(i),
|
||||
ready_out_dds => ready_ri_dr(i),
|
||||
data_out_dds => data_dr_ri(i),
|
||||
last_word_out_dds => last_word_dr_ri(i),
|
||||
sample_info => sample_info_dr_ri(i),
|
||||
sample_info_valid => sample_info_valid_dr_ri(i),
|
||||
sample_info_ack => sample_info_ack_ri_dr(i),
|
||||
eoc => eoc_dr_ri(i),
|
||||
-- Communication Status
|
||||
status => status_dr_ri(i)
|
||||
);
|
||||
else generate
|
||||
dds_writer_inst : entity work.dds_writer(arch)
|
||||
generic map (
|
||||
HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS,
|
||||
DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS,
|
||||
LIFESPAN_QOS => ENDPOINT_CONFIG(i).LIFESPAN_QOS,
|
||||
LEASE_DURATION => ENDPOINT_CONFIG(i).LEASE_DURATION,
|
||||
WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY,
|
||||
MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES,
|
||||
MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES,
|
||||
MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE,
|
||||
PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE
|
||||
)
|
||||
port map (
|
||||
-- SYSTEM
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
time => time,
|
||||
-- TO/FROM RTPS ENDPOINT
|
||||
start_rtps => start_rw_dw(i-NUM_READERS),
|
||||
opcode_rtps => opcode_rw_dw(i-NUM_READERS),
|
||||
ack_rtps => ack_dw_rw(i-NUM_READERS),
|
||||
done_rtps => done_rw_dw(i-NUM_READERS),
|
||||
ret_rtps => ret_dw_rw(i-NUM_READERS),
|
||||
seq_nr_rtps => seq_nr_rw_dw(i-NUM_READERS),
|
||||
get_data_rtps => get_data_rw_dw(i-NUM_READERS),
|
||||
valid_out_rtps => valid_dw_rw(i-NUM_READERS),
|
||||
ready_out_rtps => ready_rw_dw(i-NUM_READERS),
|
||||
data_out_rtps => data_dw_rw(i-NUM_READERS),
|
||||
last_word_out_rtps => last_word_dw_rw(i-NUM_READERS),
|
||||
liveliness_assertion => liveliness_assertion_dw_rw(i-NUM_READERS),
|
||||
data_available => data_available_dw_rw(i-NUM_READERS),
|
||||
-- Cache Change
|
||||
cc_instance_handle => cc_instance_handle_dw_rw(i-NUM_READERS),
|
||||
cc_kind => cc_kind_dw_rw(i-NUM_READERS),
|
||||
cc_source_timestamp => cc_source_timestamp_dw_rw(i-NUM_READERS),
|
||||
cc_seq_nr => cc_seq_nr_dw_rw(i-NUM_READERS),
|
||||
-- TO/FROM USER ENTITY
|
||||
start_dds => start_wi_dw(i-NUM_READERS),
|
||||
ack_dds => ack_dw_wi(i-NUM_READERS),
|
||||
opcode_dds => opcode_wi_dw(i-NUM_READERS),
|
||||
instance_handle_in_dds => instance_handle_wi_dw(i-NUM_READERS),
|
||||
source_ts_dds => source_ts_wi_dw(i-NUM_READERS),
|
||||
max_wait_dds => max_wait_wi_dw(i-NUM_READERS),
|
||||
done_dds => done_dw_wi(i-NUM_READERS),
|
||||
return_code_dds => return_code_dw_wi(i-NUM_READERS),
|
||||
instance_handle_out_dds => instance_handle_dw_wi(i-NUM_READERS),
|
||||
valid_in_dds => valid_wi_dw(i-NUM_READERS),
|
||||
ready_in_dds => ready_dw_wi(i-NUM_READERS),
|
||||
data_in_dds => data_wi_dw(i-NUM_READERS),
|
||||
last_word_in_dds => last_word_wi_dw(i-NUM_READERS),
|
||||
valid_out_dds => valid_dw_wi(i-NUM_READERS),
|
||||
ready_out_dds => ready_wi_dw(i-NUM_READERS),
|
||||
data_out_dds => data_dw_wi(i-NUM_READERS),
|
||||
last_word_out_dds => last_word_dw_wi(i-NUM_READERS),
|
||||
-- Communication Status
|
||||
status => status_dw_wi(i-NUM_READERS)
|
||||
);
|
||||
end generate;
|
||||
dds_endpoint_w_if : if (NUM_WRITERS > 1) generate
|
||||
dds_writer_inst : entity work.dds_writer(arch)
|
||||
generic map (
|
||||
NUM_WRITERS => NUM_WRITERS-1,
|
||||
CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(ENDPOINT_CONFIG(NUM_READERS to NUM_ENDPOINTS-2))
|
||||
)
|
||||
port map (
|
||||
-- SYSTEM
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
time => time,
|
||||
-- TO/FROM RTPS ENDPOINT
|
||||
start_rtps => start_rw_dw(0 to NUM_WRITERS-2),
|
||||
opcode_rtps => opcode_rw_dw(0 to NUM_WRITERS-2),
|
||||
ack_rtps => ack_dw_rw(0 to NUM_WRITERS-2),
|
||||
done_rtps => done_rw_dw(0 to NUM_WRITERS-2),
|
||||
ret_rtps => ret_dw_rw(0 to NUM_WRITERS-2),
|
||||
seq_nr_rtps => seq_nr_rw_dw(0 to NUM_WRITERS-2),
|
||||
get_data_rtps => get_data_rw_dw(0 to NUM_WRITERS-2),
|
||||
valid_out_rtps => valid_dw_rw(0 to NUM_WRITERS-2),
|
||||
ready_out_rtps => ready_rw_dw(0 to NUM_WRITERS-2),
|
||||
data_out_rtps => data_dw_rw(0 to NUM_WRITERS-2),
|
||||
last_word_out_rtps => last_word_dw_rw(0 to NUM_WRITERS-2),
|
||||
liveliness_assertion => liveliness_assertion_dw_rw(0 to NUM_WRITERS-2),
|
||||
data_available => data_available_dw_rw(0 to NUM_WRITERS-2),
|
||||
-- Cache Change
|
||||
cc_instance_handle => cc_instance_handle_dw_rw(0 to NUM_WRITERS-2),
|
||||
cc_kind => cc_kind_dw_rw(0 to NUM_WRITERS-2),
|
||||
cc_source_timestamp => cc_source_timestamp_dw_rw(0 to NUM_WRITERS-2),
|
||||
cc_seq_nr => cc_seq_nr_dw_rw(0 to NUM_WRITERS-2),
|
||||
-- TO/FROM USER ENTITY
|
||||
start_dds => start_wi_dw(0 to NUM_WRITERS-2),
|
||||
ack_dds => ack_dw_wi(0 to NUM_WRITERS-2),
|
||||
opcode_dds => opcode_wi_dw(0 to NUM_WRITERS-2),
|
||||
instance_handle_in_dds => instance_handle_wi_dw(0 to NUM_WRITERS-2),
|
||||
source_ts_dds => source_ts_wi_dw(0 to NUM_WRITERS-2),
|
||||
max_wait_dds => max_wait_wi_dw(0 to NUM_WRITERS-2),
|
||||
done_dds => done_dw_wi(0 to NUM_WRITERS-2),
|
||||
return_code_dds => return_code_dw_wi(0 to NUM_WRITERS-2),
|
||||
instance_handle_out_dds => instance_handle_dw_wi(0 to NUM_WRITERS-2),
|
||||
valid_in_dds => valid_wi_dw(0 to NUM_WRITERS-2),
|
||||
ready_in_dds => ready_dw_wi(0 to NUM_WRITERS-2),
|
||||
data_in_dds => data_wi_dw(0 to NUM_WRITERS-2),
|
||||
last_word_in_dds => last_word_wi_dw(0 to NUM_WRITERS-2),
|
||||
valid_out_dds => valid_dw_wi(0 to NUM_WRITERS-2),
|
||||
ready_out_dds => ready_wi_dw(0 to NUM_WRITERS-2),
|
||||
data_out_dds => data_dw_wi(0 to NUM_WRITERS-2),
|
||||
last_word_out_dds => last_word_dw_wi(0 to NUM_WRITERS-2),
|
||||
-- Communication Status
|
||||
status => status_dw_wi(0 to NUM_WRITERS-2)
|
||||
);
|
||||
end generate;
|
||||
dds_endpoint_gen : for i in 0 to NUM_READERS-1 generate
|
||||
dds_reader_inst : entity work.dds_reader(arch)
|
||||
generic map (
|
||||
TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS,
|
||||
DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS,
|
||||
MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES,
|
||||
MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE,
|
||||
MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES,
|
||||
HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS,
|
||||
RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS,
|
||||
PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS,
|
||||
DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS,
|
||||
COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS,
|
||||
ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS,
|
||||
WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY,
|
||||
PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE,
|
||||
MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS
|
||||
)
|
||||
port map (
|
||||
-- SYSTEM
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
time => time,
|
||||
-- FROM RTPS ENDPOINT
|
||||
start_rtps => start_rr_dr(i),
|
||||
opcode_rtps => opcode_rr_dr(i),
|
||||
ack_rtps => ack_dr_rr(i),
|
||||
done_rtps => done_dr_rr(i),
|
||||
ret_rtps => ret_dr_rr(i),
|
||||
valid_in_rtps => valid_rr_dr(i),
|
||||
ready_in_rtps => ready_dr_rr(i),
|
||||
data_in_rtps => data_rr_dr(i),
|
||||
last_word_in_rtps => last_word_rr_dr(i),
|
||||
-- TO USER ENTITY
|
||||
start_dds => start_ri_dr(i),
|
||||
ack_dds => ack_dr_ri(i),
|
||||
opcode_dds => opcode_ri_dr(i),
|
||||
instance_state_dds => instance_state_ri_dr(i),
|
||||
view_state_dds => view_state_ri_dr(i),
|
||||
sample_state_dds => sample_state_ri_dr(i),
|
||||
instance_handle_dds => instance_handle_ri_dr(i),
|
||||
max_samples_dds => max_samples_ri_dr(i),
|
||||
get_data_dds => get_data_ri_dr(i),
|
||||
done_dds => done_dr_ri(i),
|
||||
return_code_dds => return_code_dr_ri(i),
|
||||
valid_out_dds => valid_dr_ri(i),
|
||||
ready_out_dds => ready_ri_dr(i),
|
||||
data_out_dds => data_dr_ri(i),
|
||||
last_word_out_dds => last_word_dr_ri(i),
|
||||
sample_info => sample_info_dr_ri(i),
|
||||
sample_info_valid => sample_info_valid_dr_ri(i),
|
||||
sample_info_ack => sample_info_ack_ri_dr(i),
|
||||
eoc => eoc_dr_ri(i),
|
||||
-- Communication Status
|
||||
status => status_dr_ri(i)
|
||||
);
|
||||
end generate;
|
||||
|
||||
|
||||
|
||||
@ -399,122 +399,114 @@ begin
|
||||
);
|
||||
end generate;
|
||||
|
||||
dds_endpoint_gen : for i in 0 to NUM_ENDPOINTS-2 generate
|
||||
dds_endpoint_if : if (i < NUM_READERS) generate
|
||||
dds_reader_inst : entity work.dds_reader(arch)
|
||||
generic map (
|
||||
TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS,
|
||||
DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS,
|
||||
MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES,
|
||||
MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE,
|
||||
MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES,
|
||||
HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS,
|
||||
RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS,
|
||||
PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS,
|
||||
DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS,
|
||||
COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS,
|
||||
ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS,
|
||||
WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY,
|
||||
PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE,
|
||||
MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS
|
||||
)
|
||||
port map (
|
||||
-- SYSTEM
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
time => time,
|
||||
-- FROM RTPS ENDPOINT
|
||||
start_rtps => start_rr_dr(i),
|
||||
opcode_rtps => opcode_rr_dr(i),
|
||||
ack_rtps => ack_dr_rr(i),
|
||||
done_rtps => done_dr_rr(i),
|
||||
ret_rtps => ret_dr_rr(i),
|
||||
valid_in_rtps => valid_rr_dr(i),
|
||||
ready_in_rtps => ready_dr_rr(i),
|
||||
data_in_rtps => data_rr_dr(i),
|
||||
last_word_in_rtps => last_word_rr_dr(i),
|
||||
-- TO USER ENTITY
|
||||
start_dds => start_ri_dr(i),
|
||||
ack_dds => ack_dr_ri(i),
|
||||
opcode_dds => opcode_ri_dr(i),
|
||||
instance_state_dds => instance_state_ri_dr(i),
|
||||
view_state_dds => view_state_ri_dr(i),
|
||||
sample_state_dds => sample_state_ri_dr(i),
|
||||
instance_handle_dds => instance_handle_ri_dr(i),
|
||||
max_samples_dds => max_samples_ri_dr(i),
|
||||
get_data_dds => get_data_ri_dr(i),
|
||||
done_dds => done_dr_ri(i),
|
||||
return_code_dds => return_code_dr_ri(i),
|
||||
valid_out_dds => valid_dr_ri(i),
|
||||
ready_out_dds => ready_ri_dr(i),
|
||||
data_out_dds => data_dr_ri(i),
|
||||
last_word_out_dds => last_word_dr_ri(i),
|
||||
sample_info => sample_info_dr_ri(i),
|
||||
sample_info_valid => sample_info_valid_dr_ri(i),
|
||||
sample_info_ack => sample_info_ack_ri_dr(i),
|
||||
eoc => eoc_dr_ri(i),
|
||||
-- Communication Status
|
||||
status => status_dr_ri(i)
|
||||
);
|
||||
else generate
|
||||
dds_writer_inst : entity work.dds_writer(arch)
|
||||
generic map (
|
||||
HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS,
|
||||
DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS,
|
||||
LIFESPAN_QOS => ENDPOINT_CONFIG(i).LIFESPAN_QOS,
|
||||
LEASE_DURATION => ENDPOINT_CONFIG(i).LEASE_DURATION,
|
||||
WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY,
|
||||
MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES,
|
||||
MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES,
|
||||
MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE,
|
||||
PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE
|
||||
)
|
||||
port map (
|
||||
-- SYSTEM
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
time => time,
|
||||
-- TO/FROM RTPS ENDPOINT
|
||||
start_rtps => start_rw_dw(i-NUM_READERS),
|
||||
opcode_rtps => opcode_rw_dw(i-NUM_READERS),
|
||||
ack_rtps => ack_dw_rw(i-NUM_READERS),
|
||||
done_rtps => done_rw_dw(i-NUM_READERS),
|
||||
ret_rtps => ret_dw_rw(i-NUM_READERS),
|
||||
seq_nr_rtps => seq_nr_rw_dw(i-NUM_READERS),
|
||||
get_data_rtps => get_data_rw_dw(i-NUM_READERS),
|
||||
valid_out_rtps => valid_dw_rw(i-NUM_READERS),
|
||||
ready_out_rtps => ready_rw_dw(i-NUM_READERS),
|
||||
data_out_rtps => data_dw_rw(i-NUM_READERS),
|
||||
last_word_out_rtps => last_word_dw_rw(i-NUM_READERS),
|
||||
liveliness_assertion => liveliness_assertion_dw_rw(i-NUM_READERS),
|
||||
data_available => data_available_dw_rw(i-NUM_READERS),
|
||||
-- Cache Change
|
||||
cc_instance_handle => cc_instance_handle_dw_rw(i-NUM_READERS),
|
||||
cc_kind => cc_kind_dw_rw(i-NUM_READERS),
|
||||
cc_source_timestamp => cc_source_timestamp_dw_rw(i-NUM_READERS),
|
||||
cc_seq_nr => cc_seq_nr_dw_rw(i-NUM_READERS),
|
||||
-- TO/FROM USER ENTITY
|
||||
start_dds => start_wi_dw(i-NUM_READERS),
|
||||
ack_dds => ack_dw_wi(i-NUM_READERS),
|
||||
opcode_dds => opcode_wi_dw(i-NUM_READERS),
|
||||
instance_handle_in_dds => instance_handle_wi_dw(i-NUM_READERS),
|
||||
source_ts_dds => source_ts_wi_dw(i-NUM_READERS),
|
||||
max_wait_dds => max_wait_wi_dw(i-NUM_READERS),
|
||||
done_dds => done_dw_wi(i-NUM_READERS),
|
||||
return_code_dds => return_code_dw_wi(i-NUM_READERS),
|
||||
instance_handle_out_dds => instance_handle_dw_wi(i-NUM_READERS),
|
||||
valid_in_dds => valid_wi_dw(i-NUM_READERS),
|
||||
ready_in_dds => ready_dw_wi(i-NUM_READERS),
|
||||
data_in_dds => data_wi_dw(i-NUM_READERS),
|
||||
last_word_in_dds => last_word_wi_dw(i-NUM_READERS),
|
||||
valid_out_dds => valid_dw_wi(i-NUM_READERS),
|
||||
ready_out_dds => ready_wi_dw(i-NUM_READERS),
|
||||
data_out_dds => data_dw_wi(i-NUM_READERS),
|
||||
last_word_out_dds => last_word_dw_wi(i-NUM_READERS),
|
||||
-- Communication Status
|
||||
status => status_dw_wi(i-NUM_READERS)
|
||||
);
|
||||
end generate;
|
||||
dds_endpoint_w_if : if (NUM_WRITERS > 1) generate
|
||||
dds_writer_inst : entity work.dds_writer(arch)
|
||||
generic map (
|
||||
NUM_WRITERS => NUM_WRITERS-1,
|
||||
CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(ENDPOINT_CONFIG(NUM_READERS to NUM_ENDPOINTS-2))
|
||||
)
|
||||
port map (
|
||||
-- SYSTEM
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
time => time,
|
||||
-- TO/FROM RTPS ENDPOINT
|
||||
start_rtps => start_rw_dw(0 to NUM_WRITERS-2),
|
||||
opcode_rtps => opcode_rw_dw(0 to NUM_WRITERS-2),
|
||||
ack_rtps => ack_dw_rw(0 to NUM_WRITERS-2),
|
||||
done_rtps => done_rw_dw(0 to NUM_WRITERS-2),
|
||||
ret_rtps => ret_dw_rw(0 to NUM_WRITERS-2),
|
||||
seq_nr_rtps => seq_nr_rw_dw(0 to NUM_WRITERS-2),
|
||||
get_data_rtps => get_data_rw_dw(0 to NUM_WRITERS-2),
|
||||
valid_out_rtps => valid_dw_rw(0 to NUM_WRITERS-2),
|
||||
ready_out_rtps => ready_rw_dw(0 to NUM_WRITERS-2),
|
||||
data_out_rtps => data_dw_rw(0 to NUM_WRITERS-2),
|
||||
last_word_out_rtps => last_word_dw_rw(0 to NUM_WRITERS-2),
|
||||
liveliness_assertion => liveliness_assertion_dw_rw(0 to NUM_WRITERS-2),
|
||||
data_available => data_available_dw_rw(0 to NUM_WRITERS-2),
|
||||
-- Cache Change
|
||||
cc_instance_handle => cc_instance_handle_dw_rw(0 to NUM_WRITERS-2),
|
||||
cc_kind => cc_kind_dw_rw(0 to NUM_WRITERS-2),
|
||||
cc_source_timestamp => cc_source_timestamp_dw_rw(0 to NUM_WRITERS-2),
|
||||
cc_seq_nr => cc_seq_nr_dw_rw(0 to NUM_WRITERS-2),
|
||||
-- TO/FROM USER ENTITY
|
||||
start_dds => start_wi_dw(0 to NUM_WRITERS-2),
|
||||
ack_dds => ack_dw_wi(0 to NUM_WRITERS-2),
|
||||
opcode_dds => opcode_wi_dw(0 to NUM_WRITERS-2),
|
||||
instance_handle_in_dds => instance_handle_wi_dw(0 to NUM_WRITERS-2),
|
||||
source_ts_dds => source_ts_wi_dw(0 to NUM_WRITERS-2),
|
||||
max_wait_dds => max_wait_wi_dw(0 to NUM_WRITERS-2),
|
||||
done_dds => done_dw_wi(0 to NUM_WRITERS-2),
|
||||
return_code_dds => return_code_dw_wi(0 to NUM_WRITERS-2),
|
||||
instance_handle_out_dds => instance_handle_dw_wi(0 to NUM_WRITERS-2),
|
||||
valid_in_dds => valid_wi_dw(0 to NUM_WRITERS-2),
|
||||
ready_in_dds => ready_dw_wi(0 to NUM_WRITERS-2),
|
||||
data_in_dds => data_wi_dw(0 to NUM_WRITERS-2),
|
||||
last_word_in_dds => last_word_wi_dw(0 to NUM_WRITERS-2),
|
||||
valid_out_dds => valid_dw_wi(0 to NUM_WRITERS-2),
|
||||
ready_out_dds => ready_wi_dw(0 to NUM_WRITERS-2),
|
||||
data_out_dds => data_dw_wi(0 to NUM_WRITERS-2),
|
||||
last_word_out_dds => last_word_dw_wi(0 to NUM_WRITERS-2),
|
||||
-- Communication Status
|
||||
status => status_dw_wi(0 to NUM_WRITERS-2)
|
||||
);
|
||||
end generate;
|
||||
dds_endpoint_gen : for i in 0 to NUM_READERS-1 generate
|
||||
dds_reader_inst : entity work.dds_reader(arch)
|
||||
generic map (
|
||||
TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(i).TIME_BASED_FILTER_QOS,
|
||||
DEADLINE_QOS => ENDPOINT_CONFIG(i).DEADLINE_QOS,
|
||||
MAX_INSTANCES => ENDPOINT_CONFIG(i).MAX_INSTANCES,
|
||||
MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(i).MAX_SAMPLES_PER_INSTANCE,
|
||||
MAX_SAMPLES => ENDPOINT_CONFIG(i).MAX_SAMPLES,
|
||||
HISTORY_QOS => ENDPOINT_CONFIG(i).HISTORY_QOS,
|
||||
RELIABILITY_QOS => ENDPOINT_CONFIG(i).RELIABILITY_QOS,
|
||||
PRESENTATION_QOS => ENDPOINT_CONFIG(i).PRESENTATION_QOS,
|
||||
DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(i).DESTINATION_ORDER_QOS,
|
||||
COHERENT_ACCESS => ENDPOINT_CONFIG(i).COHERENT_ACCESS,
|
||||
ORDERED_ACCESS => ENDPOINT_CONFIG(i).ORDERED_ACCESS,
|
||||
WITH_KEY => ENDPOINT_CONFIG(i).WITH_KEY,
|
||||
PAYLOAD_FRAME_SIZE => ENDPOINT_CONFIG(i).MAX_PAYLOAD_SIZE,
|
||||
MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS
|
||||
)
|
||||
port map (
|
||||
-- SYSTEM
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
time => time,
|
||||
-- FROM RTPS ENDPOINT
|
||||
start_rtps => start_rr_dr(i),
|
||||
opcode_rtps => opcode_rr_dr(i),
|
||||
ack_rtps => ack_dr_rr(i),
|
||||
done_rtps => done_dr_rr(i),
|
||||
ret_rtps => ret_dr_rr(i),
|
||||
valid_in_rtps => valid_rr_dr(i),
|
||||
ready_in_rtps => ready_dr_rr(i),
|
||||
data_in_rtps => data_rr_dr(i),
|
||||
last_word_in_rtps => last_word_rr_dr(i),
|
||||
-- TO USER ENTITY
|
||||
start_dds => start_ri_dr(i),
|
||||
ack_dds => ack_dr_ri(i),
|
||||
opcode_dds => opcode_ri_dr(i),
|
||||
instance_state_dds => instance_state_ri_dr(i),
|
||||
view_state_dds => view_state_ri_dr(i),
|
||||
sample_state_dds => sample_state_ri_dr(i),
|
||||
instance_handle_dds => instance_handle_ri_dr(i),
|
||||
max_samples_dds => max_samples_ri_dr(i),
|
||||
get_data_dds => get_data_ri_dr(i),
|
||||
done_dds => done_dr_ri(i),
|
||||
return_code_dds => return_code_dr_ri(i),
|
||||
valid_out_dds => valid_dr_ri(i),
|
||||
ready_out_dds => ready_ri_dr(i),
|
||||
data_out_dds => data_dr_ri(i),
|
||||
last_word_out_dds => last_word_dr_ri(i),
|
||||
sample_info => sample_info_dr_ri(i),
|
||||
sample_info_valid => sample_info_valid_dr_ri(i),
|
||||
sample_info_ack => sample_info_ack_ri_dr(i),
|
||||
eoc => eoc_dr_ri(i),
|
||||
-- Communication Status
|
||||
status => status_dr_ri(i)
|
||||
);
|
||||
end generate;
|
||||
|
||||
|
||||
|
||||
@ -79,9 +79,12 @@ package rtps_package is
|
||||
constant SAMPLE_LOST_STATUS_COUNT_WIDTH : natural := CDR_LONG_WIDTH;
|
||||
constant SAMPLE_REJECTED_STATUS_COUNT_WIDTH : natural := CDR_LONG_WIDTH;
|
||||
constant LIVELINESS_LOST_STATUS_COUNT_WIDTH : natural := CDR_LONG_WIDTH;
|
||||
type LIVELINESS_LOST_STATUS_COUNT_ARRAY_TYPE is array (natural range <>) of std_logic_vector(LIVELINESS_LOST_STATUS_COUNT_WIDTH-1 downto 0);
|
||||
constant LIVELINESS_CHANGED_STATUS_COUNT_WIDTH : natural := CDR_LONG_WIDTH;
|
||||
constant OFFERED_DEADLINE_MISSED_STATUS_COUNT_WIDTH : natural := CDR_LONG_WIDTH;
|
||||
type OFFERED_DEADLINE_MISSED_STATUS_COUNT_ARRAY_TYPE is array (natural range <>) of std_logic_vector(OFFERED_DEADLINE_MISSED_STATUS_COUNT_WIDTH-1 downto 0);
|
||||
constant REQUESTED_DEADLINE_MISSED_STATUS_COUNT_WIDTH : natural := CDR_LONG_WIDTH;
|
||||
type REQUESTED_DEADLINE_MISSED_STATUS_COUNT_ARRAY_TYPE is array (natural range <>) of std_logic_vector(REQUESTED_DEADLINE_MISSED_STATUS_COUNT_WIDTH-1 downto 0);
|
||||
constant OFFERED_INCOMPATIBLE_QOS_STATUS_COUNT_WIDTH : natural := CDR_LONG_WIDTH;
|
||||
constant REQUESTED_INCOMPATIBLE_QOS_STATUS_COUNT_WIDTH : natural := CDR_LONG_WIDTH;
|
||||
constant PUBLICATION_MATCHED_STATUS_COUNT_WIDTH : natural := CDR_LONG_WIDTH;
|
||||
@ -492,6 +495,7 @@ package rtps_package is
|
||||
type HISTORY_CACHE_OPCODE_TYPE is (NOP, ADD_CACHE_CHANGE, GET_CACHE_CHANGE, ACK_CACHE_CHANGE, NACK_CACHE_CHANGE, REMOVE_CACHE_CHANGE, REMOVE_WRITER, GET_MIN_SN, GET_MAX_SN);
|
||||
type HISTORY_CACHE_OPCODE_ARRAY_TYPE is array (natural range <>) of HISTORY_CACHE_OPCODE_TYPE;
|
||||
type KEY_HOLDER_OPCODE_TYPE is (NOP, PUSH_DATA, PUSH_SERIALIZED_KEY, READ_KEY_HASH, READ_SERIALIZED_KEY);
|
||||
type KEY_HOLDER_OPCODE_ARRAY_TYPE is array (natural range <>) of KEY_HOLDER_OPCODE_TYPE;
|
||||
type HISTORY_CACHE_RESPONSE_TYPE is (OK, REJECTED, INVALID, ERROR);
|
||||
type HISTORY_CACHE_RESPONSE_ARRAY_TYPE is array (natural range <>) of HISTORY_CACHE_RESPONSE_TYPE;
|
||||
type DDS_WRITER_OPCODE_TYPE is (NOP, REGISTER_INSTANCE, WRITE, DISPOSE, UNREGISTER_INSTANCE, LOOKUP_INSTANCE, WAIT_FOR_ACKNOWLEDGEMENTS, GET_OFFERED_DEADLINE_MISSED_STATUS, ASSERT_LIVELINESS, GET_LIVELINESS_LOST_STATUS);
|
||||
|
||||
@ -39,7 +39,7 @@
|
||||
|
||||
set_global_assignment -name FAMILY "Cyclone V"
|
||||
set_global_assignment -name DEVICE 5CSEBA6U23I7
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY test_top
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY dds_writer_syn
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:33:09 NOVEMBER 02, 2020"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
|
||||
@ -49,9 +49,6 @@ set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
|
||||
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_global_assignment -name SDC_FILE ../top.sdc
|
||||
set_global_assignment -name VHDL_FILE ../test_top.vhd -hdl_version VHDL_2008
|
||||
set_global_assignment -name VHDL_FILE ../../src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib4.vhd -hdl_version VHDL_2008
|
||||
@ -134,4 +131,7 @@ set_global_assignment -name VHDL_FILE ../../src/ros2/rcl_interfaces/action_msgs/
|
||||
set_global_assignment -name VHDL_FILE ../../src/ros2/ros_package.vhd -hdl_version VHDL_2008
|
||||
set_global_assignment -name VHDL_FILE ../../src/rtps_package.vhd -hdl_version VHDL_2008
|
||||
set_global_assignment -name VHDL_FILE ../../src/math_pkg.vhd -hdl_version VHDL_2008
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
@ -18,44 +18,44 @@ entity dds_writer_syn is
|
||||
reset : in std_logic;
|
||||
time : in TIME_TYPE;
|
||||
-- TO/FROM RTPS ENDPOINT
|
||||
start_rtps : in std_logic;
|
||||
opcode_rtps : in HISTORY_CACHE_OPCODE_TYPE;
|
||||
ack_rtps : out std_logic;
|
||||
done_rtps : out std_logic;
|
||||
ret_rtps : out HISTORY_CACHE_RESPONSE_TYPE;
|
||||
seq_nr_rtps : in SEQUENCENUMBER_TYPE;
|
||||
get_data_rtps : in std_logic;
|
||||
data_out_rtps : out std_logic_vector(WORD_WIDTH-1 downto 0);
|
||||
valid_out_rtps : out std_logic;
|
||||
ready_out_rtps : in std_logic;
|
||||
last_word_out_rtps : out std_logic;
|
||||
liveliness_assertion : out std_logic;
|
||||
data_available : out std_logic;
|
||||
start_rtps : in std_logic_vector(0 to 0);
|
||||
opcode_rtps : in HISTORY_CACHE_OPCODE_ARRAY_TYPE(0 to 0);
|
||||
ack_rtps : out std_logic_vector(0 to 0);
|
||||
done_rtps : out std_logic_vector(0 to 0);
|
||||
ret_rtps : out HISTORY_CACHE_RESPONSE_ARRAY_TYPE(0 to 0);
|
||||
seq_nr_rtps : in SEQUENCENUMBER_ARRAY_TYPE(0 to 0);
|
||||
get_data_rtps : in std_logic_vector(0 to 0);
|
||||
data_out_rtps : out WORD_ARRAY_TYPE(0 to 0);
|
||||
valid_out_rtps : out std_logic_vector(0 to 0);
|
||||
ready_out_rtps : in std_logic_vector(0 to 0);
|
||||
last_word_out_rtps : out std_logic_vector(0 to 0);
|
||||
liveliness_assertion : out std_logic_vector(0 to 0);
|
||||
data_available : out std_logic_vector(0 to 0);
|
||||
-- Cache Change
|
||||
cc_instance_handle : out INSTANCE_HANDLE_TYPE;
|
||||
cc_kind : out CACHE_CHANGE_KIND_TYPE;
|
||||
cc_source_timestamp : out TIME_TYPE;
|
||||
cc_seq_nr : out SEQUENCENUMBER_TYPE;
|
||||
cc_instance_handle : out INSTANCE_HANDLE_ARRAY_TYPE(0 to 0);
|
||||
cc_kind : out CACHE_CHANGE_KIND_ARRAY_TYPE(0 to 0);
|
||||
cc_source_timestamp : out TIME_ARRAY_TYPE(0 to 0);
|
||||
cc_seq_nr : out SEQUENCENUMBER_ARRAY_TYPE(0 to 0);
|
||||
-- TO/FROM USER ENTITY
|
||||
start_dds : in std_logic;
|
||||
ack_dds : out std_logic;
|
||||
opcode_dds : in DDS_WRITER_OPCODE_TYPE;
|
||||
instance_handle_in_dds : in INSTANCE_HANDLE_TYPE;
|
||||
source_ts_dds : in TIME_TYPE;
|
||||
max_wait_dds : in DURATION_TYPE;
|
||||
done_dds : out std_logic;
|
||||
return_code_dds : out std_logic_vector(RETURN_CODE_WIDTH-1 downto 0);
|
||||
instance_handle_out_dds : out INSTANCE_HANDLE_TYPE;
|
||||
ready_in_dds : out std_logic;
|
||||
valid_in_dds : in std_logic;
|
||||
data_in_dds : in std_logic_vector(WORD_WIDTH-1 downto 0);
|
||||
last_word_in_dds : in std_logic;
|
||||
ready_out_dds : in std_logic;
|
||||
valid_out_dds : out std_logic;
|
||||
data_out_dds : out std_logic_vector(WORD_WIDTH-1 downto 0);
|
||||
last_word_out_dds : out std_logic;
|
||||
start_dds : in std_logic_vector(0 to 0);
|
||||
ack_dds : out std_logic_vector(0 to 0);
|
||||
opcode_dds : in DDS_WRITER_OPCODE_ARRAY_TYPE(0 to 0);
|
||||
instance_handle_in_dds : in INSTANCE_HANDLE_ARRAY_TYPE(0 to 0);
|
||||
source_ts_dds : in TIME_ARRAY_TYPE(0 to 0);
|
||||
max_wait_dds : in DURATION_ARRAY_TYPE(0 to 0);
|
||||
done_dds : out std_logic_vector(0 to 0);
|
||||
return_code_dds : out RETURN_CODE_ARRAY_TYPE(0 to 0);
|
||||
instance_handle_out_dds : out INSTANCE_HANDLE_ARRAY_TYPE(0 to 0);
|
||||
valid_in_dds : in std_logic_vector(0 to 0);
|
||||
ready_in_dds : out std_logic_vector(0 to 0);
|
||||
data_in_dds : in WORD_ARRAY_TYPE(0 to 0);
|
||||
last_word_in_dds : in std_logic_vector(0 to 0);
|
||||
valid_out_dds : out std_logic_vector(0 to 0);
|
||||
ready_out_dds : in std_logic_vector(0 to 0);
|
||||
data_out_dds : out WORD_ARRAY_TYPE(0 to 0);
|
||||
last_word_out_dds : out std_logic_vector(0 to 0);
|
||||
-- Communication Status
|
||||
status : out std_logic_vector(STATUS_KIND_WIDTH-1 downto 0)
|
||||
status : out STATUS_KIND_ARRAY_TYPE(0 to 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
@ -65,15 +65,8 @@ begin
|
||||
if_gen : if (NUM_WRITERS > 0) generate
|
||||
syn_inst : entity work.dds_writer(arch)
|
||||
generic map (
|
||||
HISTORY_QOS => ENDPOINT_CONFIG(NUM_READERS).HISTORY_QOS,
|
||||
DEADLINE_QOS => ENDPOINT_CONFIG(NUM_READERS).DEADLINE_QOS,
|
||||
LIFESPAN_QOS => ENDPOINT_CONFIG(NUM_READERS).LIFESPAN_QOS,
|
||||
LEASE_DURATION => ENDPOINT_CONFIG(NUM_READERS).LEASE_DURATION,
|
||||
WITH_KEY => ENDPOINT_CONFIG(NUM_READERS).WITH_KEY,
|
||||
MAX_SAMPLES => ENDPOINT_CONFIG(NUM_READERS).MAX_SAMPLES,
|
||||
MAX_INSTANCES => ENDPOINT_CONFIG(NUM_READERS).MAX_INSTANCES,
|
||||
MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(NUM_READERS).MAX_SAMPLES_PER_INSTANCE,
|
||||
PAYLOAD_FRAME_SIZE => MAX_TYPE1_SIZE
|
||||
NUM_WRITERS => 1,
|
||||
CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(ENDPOINT_CONFIG(NUM_READERS to NUM_READERS))
|
||||
)
|
||||
port map (
|
||||
clk => clk,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user