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Fix testbench for Linux OS (Linux is case Sensitive)

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John Ring 2023-06-16 14:02:44 +02:00
parent 6e93248b52
commit 5f58b0bca4
5 changed files with 12 additions and 12 deletions
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24
sim/modelsim.ini
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@ -16,18 +16,18 @@ others = $MODEL_TECH/../modelsim.ini
; ;
; Verilog Section ; Verilog Section
; ;
default = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/default.lib default = /tmp/sim_temp/VHDL_LIBS/ModelSim-2020.02/default.lib
osvvm = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/osvvm.lib osvvm = /tmp/sim_temp/VHDL_LIBS/ModelSim-2020.02/osvvm.lib
Testbench_Lib2 = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/Testbench_Lib2.lib Testbench_Lib2 = /tmp/sim_temp/VHDL_LIBS/ModelSim-2020.02/Testbench_Lib2.lib
Testbench_Lib3 = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/Testbench_Lib3.lib Testbench_Lib3 = /tmp/sim_temp/VHDL_LIBS/ModelSim-2020.02/Testbench_Lib3.lib
Testbench_Lib4 = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/Testbench_Lib4.lib Testbench_Lib4 = /tmp/sim_temp/VHDL_LIBS/ModelSim-2020.02/Testbench_Lib4.lib
Testbench_Lib5 = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/Testbench_Lib5.lib Testbench_Lib5 = /tmp/sim_temp/VHDL_LIBS/ModelSim-2020.02/Testbench_Lib5.lib
Testbench_Lib1 = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/Testbench_Lib1.lib Testbench_Lib1 = /tmp/sim_temp/VHDL_LIBS/ModelSim-2020.02/Testbench_Lib1.lib
Testbench_ROS_Lib1 = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/Testbench_ROS_Lib1.lib Testbench_ROS_Lib1 = /tmp/sim_temp/VHDL_LIBS/ModelSim-2020.02/Testbench_ROS_Lib1.lib
Testbench_ROS_Lib2 = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/Testbench_ROS_Lib2.lib Testbench_ROS_Lib2 = /tmp/sim_temp/VHDL_LIBS/ModelSim-2020.02/Testbench_ROS_Lib2.lib
Testbench_ROS_Lib3 = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/Testbench_ROS_Lib3.lib Testbench_ROS_Lib3 = /tmp/sim_temp/VHDL_LIBS/ModelSim-2020.02/Testbench_ROS_Lib3.lib
Testbench_ROS_Lib4 = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/Testbench_ROS_Lib4.lib Testbench_ROS_Lib4 = /tmp/sim_temp/VHDL_LIBS/ModelSim-2020.02/Testbench_ROS_Lib4.lib
Testbench_ROS_Lib5 = W:/HDL-SIM/OSVVM-Scripts/../sim/VHDL_LIBS/ModelSim-2020.02/Testbench_ROS_Lib5.lib Testbench_ROS_Lib5 = /tmp/sim_temp/VHDL_LIBS/ModelSim-2020.02/Testbench_ROS_Lib5.lib
[vcom] [vcom]
; VHDL93 variable selects language version as the default. ; VHDL93 variable selects language version as the default.
; Default is VHDL-2002. ; Default is VHDL-2002.

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src/Tests/Level_2/L2_testbench_Lib4.vhd → src/Tests/Level_2/L2_Testbench_Lib4.vhd
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src/Tests/Level_2/L2_testbench_Lib4_config.vhd → src/Tests/Level_2/L2_Testbench_Lib4_config.vhd
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src/Tests/Level_2/L2_testbench_Lib5.vhd → src/Tests/Level_2/L2_Testbench_Lib5.vhd
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src/Tests/Level_2/L2_testbench_Lib5_config.vhd → src/Tests/Level_2/L2_Testbench_Lib5_config.vhd
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