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Fix Avalon_MM_wrapper Byte Ordering

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According to Avalon MM Interface Specification, the Bus is in Little
Endian.
This commit is contained in:
Greek 2021-11-30 12:54:18 +01:00
parent 0ede0537b7
commit 746b273cff
1 changed files with 6 additions and 2 deletions
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8
src/Avalon_MM_wrapper.vhd
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@ -2,6 +2,8 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.rtps_config_package.all;
entity Avalon_MM_wrapper is
generic (
DATA_WIDTH : integer := 32
@ -51,7 +53,8 @@ begin
if (write = '1') then
case (to_integer(unsigned(address))) is
when 2 =>
data_ri <= writedata;
-- NOTE: Avalon-MM interface specification requires little endian ordering. [Embedded Design Handbook, Chapter 11, ED51012-1.1]
data_ri <= endian_swap('1', writedata);
if (full_ri = '1') then
-- Stall Avalon MM
waitrequest <= '1';
@ -66,7 +69,8 @@ begin
when 0 =>
readdata(0) <= not empty_ro;
when 1 =>
readdata <= data_ro;
-- NOTE: Avalon-MM interface specification requires little endian ordering. [Embedded Design Handbook, Chapter 11, ED51012-1.1]
readdata <= endian_swap('1',data_ro);
if (empty_ro = '1') then
-- Stall Avalon MM
waitrequest <= '1';