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Add moving_average VHDL Implementation

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Add a configurable moving_average implementaion, that has a configurable
window size and is enable triggered.
Also add a moving_average_wrapper that instantiates 2 moving_average instances
(an inner and an outer) to lower the memory resource requirement for large
window sizes. Effective window size is OUTER*INNER, whereas the resources are
only OUTER+INNER. A trigger signal signals when the average is "valid".

Accompanying testebench was also implemented.
This commit is contained in:
John Ring 2023-06-23 23:55:49 +02:00
parent c318b3c560
commit 8004f21a7c
5 changed files with 412 additions and 1 deletions
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45
sim/L0_moving_average_wrapper_test1.do Normal file
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onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider SYSTEM
add wave -noupdate /l0_moving_average_wrapper_test1/uut/clk
add wave -noupdate /l0_moving_average_wrapper_test1/uut/reset
add wave -noupdate -divider WRAPPER
add wave -noupdate -radix unsigned /l0_moving_average_wrapper_test1/uut/data_in
add wave -noupdate -radix unsigned /l0_moving_average_wrapper_test1/uut/average
add wave -noupdate /l0_moving_average_wrapper_test1/uut/trigger
add wave -noupdate /l0_moving_average_wrapper_test1/uut/overflow
add wave -noupdate -divider INNER
add wave -noupdate /l0_moving_average_wrapper_test1/uut/inner_average_inst/enable
add wave -noupdate -radix unsigned /l0_moving_average_wrapper_test1/uut/inner_average_inst/data_in
add wave -noupdate -radix unsigned /l0_moving_average_wrapper_test1/uut/inner_average_inst/average
add wave -noupdate /l0_moving_average_wrapper_test1/uut/inner_average_inst/overflow
add wave -noupdate /l0_moving_average_wrapper_test1/uut/inner_average_inst/fifo_full
add wave -noupdate -divider OUTER
add wave -noupdate /l0_moving_average_wrapper_test1/uut/outer_average_inst/enable
add wave -noupdate -radix unsigned /l0_moving_average_wrapper_test1/uut/outer_average_inst/data_in
add wave -noupdate -radix unsigned /l0_moving_average_wrapper_test1/uut/outer_average_inst/average
add wave -noupdate /l0_moving_average_wrapper_test1/uut/outer_average_inst/overflow
add wave -noupdate /l0_moving_average_wrapper_test1/uut/outer_average_inst/fifo_full
add wave -noupdate -divider MISC
add wave -noupdate /l0_moving_average_wrapper_test1/uut/inner_cnt
add wave -noupdate /l0_moving_average_wrapper_test1/uut/outer_cnt
add wave -noupdate /l0_moving_average_wrapper_test1/uut/inner_trigger
add wave -noupdate /l0_moving_average_wrapper_test1/uut/outer_trigger
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {400000 ps} 0}
quietly wave cursor active 1
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {0 ps} {1007104 ps}

181
src/Tests/Level_0/L0_moving_average_wrapper_test1.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library osvvm; -- Utility Library
context osvvm.OsvvmContext;
use work.rtps_test_package.all;
-- TODO
entity L0_moving_average_wrapper_test1 is
end entity;
architecture testbench of L0_moving_average_wrapper_test1 is
-- *SIGNAL DECLARATION*
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal data_in, average : std_logic_vector(31 downto 0);
signal trigger, overflow : std_logic;
shared variable SB : osvvm.ScoreBoardPkg_slv.ScoreBoardPType;
signal stim_done, check_done : std_logic := '0';
begin
-- Unit Under Test
uut : entity work.moving_average_wrapper(arch)
generic map(
INNER_WINDOW_SIZE => 2,
OUTER_WINDOW_SIZE => 2,
DATA_WIDTH => 32,
ENABLE_ROUNDING => TRUE
)
port map(
clk => clk,
reset => reset,
data_in => data_in,
average => average,
trigger => trigger,
overflow => overflow
);
stimulus_prc : process
variable RV : RandomPType;
procedure wait_clock(num : in natural := 1) is
begin
assert (num > 0) report "Num has to be > 0" severity FAILURE;
for i in 0 to num-1 loop
wait until rising_edge(clk);
end loop;
end procedure;
procedure wait_on_sig(signal sig : std_logic) is
begin
if (sig /= '1') then
wait on sig until sig = '1';
end if;
end procedure;
begin
SetAlertLogName("L0_moving_average_wrapper_test1 - General");
SetAlertEnable(FAILURE, TRUE);
SetAlertEnable(ERROR, TRUE);
SetAlertEnable(WARNING, TRUE);
SetLogEnable(DEBUG, FALSE);
SetLogEnable(PASSED, FALSE);
SetLogEnable(INFO, TRUE);
RV.InitSeed(RV'instance_name);
--
Log("Initiating Test", INFO);
stim_done <= '0';
reset <= '1';
data_in <= (others => '0');
wait until rising_edge(clk);
wait until rising_edge(clk);
reset <= '0';
Log("TEST 1: {100, 100, 100, 100}}", INFO);
SB.Push(int(100,32));
data_in <= int(100, 32);
wait_clock(4);
Log("TEST 2: {0, 0, 0, 0}}", INFO);
SB.Push(int(0,32));
data_in <= int(0, 32);
wait_clock(4);
Log("TEST 3: {100,0,100,0}", INFO);
SB.Push(int(50,32));
data_in <= int(100, 32);
wait_clock;
data_in <= int(0, 32);
wait_clock;
data_in <= int(100, 32);
wait_clock;
data_in <= int(0, 32);
wait_clock;
Log("TEST 4: {0,0,100,100}", INFO);
SB.Push(int(50,32));
data_in <= int(0, 32);
wait_clock;
data_in <= int(0, 32);
wait_clock;
data_in <= int(100, 32);
wait_clock;
data_in <= int(100, 32);
wait_clock;
Log("TEST 5: {0,25,50,75}", INFO);
SB.Push(int(38,32)); -- ROUND!
data_in <= int(0, 32);
wait_clock;
data_in <= int(25, 32);
wait_clock;
data_in <= int(50, 32);
wait_clock;
data_in <= int(75, 32);
wait_clock;
Log("TEST 6: {10,50,100,50}", INFO);
SB.Push(int(53,32)); -- ROUND!
data_in <= int(10, 32);
wait_clock;
data_in <= int(50, 32);
wait_clock;
data_in <= int(100, 32);
wait_clock;
data_in <= int(50, 32);
wait_clock;
TranscriptOpen(RESULTS_FILE, APPEND_MODE);
SetTranscriptMirror;
stim_done <= '1';
wait until check_done = '1';
AlertIf(not SB.empty, "Incomplete test run");
ReportAlerts;
TranscriptClose;
std.env.stop;
wait;
end process;
output_check_prc : process(all)
begin
check_done <= '0';
if rising_edge(clk) then
if (trigger = '1') then
SB.Check(average);
end if;
if (stim_done = '1' and SB.empty) then
check_done <= '1';
end if;
end if;
end process;
clock_prc : process
begin
clk <= '1';
wait for 10 ns;
clk <= '0';
wait for 10 ns;
end process;
alert_prc : process(all)
begin
if rising_edge(clk) then
alertif(overflow = '1', "Overflow signal asserted", ERROR);
end if;
end process;
watchdog : process
begin
wait for 5 ms;
Alert("Test timeout", FAILURE);
std.env.stop;
end process;
end architecture;

5
src/Tests/testbench.pro
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@ -162,6 +162,8 @@ analyze FWFT_FIFO_cfg.vhd
analyze ../vector_FIFO.vhd
analyze ../mem_ctrl.vhd
analyze ../dp_mem_ctrl.vhd
analyze ../moving_average.vhd
analyze ../moving_average_wrapper.vhd
analyze ../rtps_handler.vhd
analyze ../rtps_discovery_module.vhd
analyze ../rtps_out.vhd
@ -183,6 +185,7 @@ analyze Type2_key_holder.vhd
analyze test_key_holder.vhd
analyze ScoreBoard_test_memory.vhd
analyze ScoreBoard_discovery_module.vhd
analyze Level_0/L0_moving_average_wrapper_test1.vhd
analyze Level_0/L0_rtps_handler_test1.vhd
analyze Level_0/L0_rtps_handler_test2.vhd
analyze Level_0/L0_rtps_discovery_module_test1_uc.vhd
@ -228,7 +231,7 @@ analyze Level_2/L2_Type1_test1.vhd
analyze Level_2/L2_Type1_test2.vhd
analyze test_cfg.vhd
simulate L0_moving_average_wrapper_test1
simulate L0_rtps_handler_test1
simulate L0_rtps_handler_test2
simulate L0_rtps_out_test1

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src/moving_average.vhd Normal file
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-- altera vhdl_input_version vhdl_2008
-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.math_pkg.all;
entity moving_average is
generic(
WINDOW_SIZE : natural := 2; -- Must be Power of Two
DATA_WIDTH : natural := 32;
ENABLE_ROUNDING : boolean := true
);
port(
-- SYSTEM
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
average : out std_logic_vector(DATA_WIDTH-1 downto 0);
overflow : out std_logic
);
end entity;
architecture arch of moving_average is
signal read_sig : std_logic;
signal fifo_out : std_logic_vector(DATA_WIDTH-1 downto 0);
signal accumulator : unsigned(DATA_WIDTH downto 0);
signal fifo_full : std_logic;
begin
fifo_inst : configuration work.FWFT_FIFO_cfg
generic map (
FIFO_DEPTH => WINDOW_SIZE,
DATA_WIDTH => DATA_WIDTH
)
port map (
clk => clk,
reset => reset,
data_in => data_in,
write => enable,
read => read_sig,
data_out => fifo_out,
empty => open,
full => fifo_full,
free => open
);
-- Keep FIFO in a full state
read_sig <= '1' when (enable = '1' and fifo_full = '1') else '0';
main_prc : process(clk)
begin
if rising_edge(clk) then
if (reset = '1') then
accumulator <= (others => '0');
overflow <= '0';
else
-- Overflow Latch
if (accumulator(DATA_WIDTH) = '1') then
overflow <= '1';
end if;
if (enable = '1') then
accumulator <= accumulator + unsigned("0" & data_in) - unsigned("0" & fifo_out) when (fifo_full = '1') else accumulator + unsigned("0" & data_in);
end if;
end if;
end if;
end process;
average <= std_logic_vector(((log2c(WINDOW_SIZE)-1 downto 0 => '0') & accumulator(DATA_WIDTH-1 downto log2c(WINDOW_SIZE))) + 1)
when (ENABLE_ROUNDING and accumulator(log2c(WINDOW_SIZE)-1) = '1')
else std_logic_vector(((log2c(WINDOW_SIZE)-1 downto 0 => '0') & accumulator(DATA_WIDTH-1 downto log2c(WINDOW_SIZE))));
end architecture;

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src/moving_average_wrapper.vhd Normal file
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-- altera vhdl_input_version vhdl_2008
-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity moving_average_wrapper is
generic(
INNER_WINDOW_SIZE : natural := 8192; -- Must be Power of Two
OUTER_WINDOW_SIZE : natural := 8192;
DATA_WIDTH : natural := 32;
ENABLE_ROUNDING : boolean := true
);
port(
-- SYSTEM
clk : in std_logic;
reset : in std_logic;
data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
average : out std_logic_vector(DATA_WIDTH-1 downto 0);
trigger : out std_logic;
overflow : out std_logic
);
end entity;
architecture arch of moving_average_wrapper is
signal inner_cnt : natural range 0 to INNER_WINDOW_SIZE;
signal outer_cnt : natural range 0 to OUTER_WINDOW_SIZE;
signal inner_out : std_logic_vector(DATA_WIDTH-1 downto 0);
signal inner_overflow : std_logic;
signal outer_overflow : std_logic;
signal inner_trigger : std_logic;
signal outer_trigger : std_logic;
begin
overflow <= inner_overflow or outer_overflow;
inner_average_inst : entity work.moving_average
generic map(
WINDOW_SIZE => INNER_WINDOW_SIZE,
DATA_WIDTH => DATA_WIDTH,
ENABLE_ROUNDING => ENABLE_ROUNDING
)
port map
(
clk => clk,
reset => reset,
enable => '1',
data_in => data_in,
average => inner_out,
overflow => inner_overflow
);
outer_average_inst : entity work.moving_average
generic map(
WINDOW_SIZE => OUTER_WINDOW_SIZE,
DATA_WIDTH => DATA_WIDTH,
ENABLE_ROUNDING => ENABLE_ROUNDING
)
port map
(
clk => clk,
reset => reset,
enable => inner_trigger,
data_in => inner_out,
average => average,
overflow => outer_overflow
);
main_prc : process(clk)
begin
if rising_edge(clk) then
if (reset = '1') then
inner_cnt <= 0;
outer_cnt <= 0;
inner_trigger <= '0';
outer_trigger <= '0';
else
-- DEFAULT
inner_trigger <= '0';
outer_trigger <= '0';
trigger <= outer_trigger;
if (inner_cnt = INNER_WINDOW_SIZE-1) then
inner_cnt <= 0;
inner_trigger <= '1';
if (outer_cnt = OUTER_WINDOW_SIZE-1) then
outer_cnt <= 0;
outer_trigger <= '1';
else
outer_cnt <= outer_cnt + 1;
end if;
else
inner_cnt <= inner_cnt + 1;
end if;
end if;
end if;
end process;
end architecture;