greek64/rtps-fpga
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8004f21a7c
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John Daktylidis 8004f21a7c Add moving_average VHDL Implementation 
Add a configurable moving_average implementaion, that has a configurable
window size and is enable triggered.
Also add a moving_average_wrapper that instantiates 2 moving_average instances
(an inner and an outer) to lower the memory resource requirement for large
window sizes. Effective window size is OUTER*INNER, whereas the resources are
only OUTER+INNER. A trigger signal signals when the average is "valid".

Accompanying testebench was also implemented.
2023-06-24 00:02:02 +02:00
doc Documentation & Code Refactoring 2023-06-17 10:48:11 +02:00
sim Add moving_average VHDL Implementation 2023-06-24 00:02:02 +02:00
src Add moving_average VHDL Implementation 2023-06-24 00:02:02 +02:00
syn TIMING CLOSURE: Split main FSM in dds_reader 2022-04-14 14:27:09 +02:00
.gitattributes * Added DDS/RTPS Documentation 2020-05-10 19:31:49 +02:00
.gitignore code refactoring 2021-12-09 19:44:39 +01:00
.gitmodules * Added OSVVM Library as Submodule 2020-11-15 20:34:39 +01:00
READ.txt Documentation & Code Refactoring 2023-06-17 10:48:11 +02:00
ros_action_Fibonacci_with_feedback2.rpt Convert rtps_writer to Vector Endpoint 2022-04-05 17:18:07 +02:00
ros_action_Fibonacci_with_feedback3.rpt Convert rtps_writer to Vector Endpoint 2022-04-05 17:18:07 +02:00
ros_action_Fibonacci_with_feedback4.rpt Convert rtps_reader to Vector Endpoint 2022-04-05 17:20:22 +02:00
ros_action_Fibonacci_with_feedback5.rpt Convert dds_writer to Vector Endpoint 2022-04-10 11:04:02 +02:00
ros_action_Fibonacci_with_feedback6.rpt TIMING CLOSURE: Split main FSM in dds_reader 2022-04-14 14:27:09 +02:00
ros_action_Fibonacci_with_feedback.rpt Add/Modify synthesis entities to synthesize Fibonacci_ros_action_server 2022-03-13 12:43:12 +01:00
ros_action_Fibonacci_with_feedback.txt TIMING CLOSURE: Split main FSM in dds_reader 2022-04-14 14:27:09 +02:00
ros_action_Fibonacci_without_feedback.rpt Add/Modify synthesis entities to synthesize Fibonacci_ros_action_server 2022-03-13 12:43:12 +01:00
VHDL-2008.txt Code Refactor 2021-05-15 20:39:56 +02:00