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Move functions between rtps_package and rtps_config_package

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This commit is contained in:
John Ring 2022-02-03 14:35:54 +01:00
parent dc47f72942
commit a26faff89a
2 changed files with 68 additions and 70 deletions
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70
src/rtps_config_package.vhd
View File

@ -143,19 +143,6 @@ package rtps_config_package is
function gen_inline_qos (id : natural) return OUTPUT_DATA_TYPE; function gen_inline_qos (id : natural) return OUTPUT_DATA_TYPE;
-- Indexing Function to extract sub-vectors from std_logic_vector signals
-- input SLV from which to extract a sub-vector
-- index The SLV is divided in width-sized sub-vectors. index states which sub-vector to extract (depending on invert)
-- width width of sub-vector (NOTE: SLV must have a length multiple to width)
-- invert If invert=TRUE, index 0 is the leftmost sub-vector, else the rightmost
function get_sub_vector (input : std_logic_vector; index : natural; width : natural; invert : boolean) return std_logic_vector;
-- Indexing Function to write sub-vectors to std_logic_vector signals
-- input SLV from to which to write a sub-vector
-- sub Sub-vector to write into the SLV
-- index The SLV is divided in sub-sized 'sub'-vectors. index states which sub-vector to write (depending on invert)
-- invert If invert=TRUE, index 0 is the leftmost sub-vector, else the rightmost
function write_sub_vector(input : std_logic_vector; sub : std_logic_vector; index : natural; invert : boolean) return std_logic_vector;
end package; end package;
package body rtps_config_package is package body rtps_config_package is
@ -1198,61 +1185,4 @@ package body rtps_config_package is
return FALSE; return FALSE;
end if; end if;
end function; end function;
function get_sub_vector (input : std_logic_vector; index : natural; width : natural; invert : boolean) return std_logic_vector is
variable ret : std_logic_vector(width-1 downto 0) := (others => '0');
begin
assert(input'length mod width = 0) report "Input Length has to be multiple of width" severity FAILURE;
assert(input'length / width > index) report "Index out of bounds" severity FAILURE;
if (invert = TRUE) then
-- XXX: Synthesis Hack
--ret := input(input'length-(index*width)-1 downto input'length-((index+1)*width));
for i in 0 to (input'length/width)-1 loop
if (index = i) then
ret := input(input'length-(i*width)-1 downto input'length-((i+1)*width));
end if;
end loop;
else
-- XXX: Synthesis Hack
--ret := input(((index+1)*width)-1 downto index*width);
for i in 0 to (input'length/width)-1 loop
if (index = i) then
ret := input(((i+1)*width)-1 downto i*width);
end if;
end loop;
end if;
return ret;
end function;
function write_sub_vector(input : std_logic_vector; sub : std_logic_vector; index : natural; invert : boolean) return std_logic_vector is
variable ret : std_logic_vector(input'length-1 downto 0) := (others => '0');
begin
assert(input'length mod sub'length = 0) report "Input Length has to be multiple of sub width" severity FAILURE;
assert(input'length / sub'length > index) report "Index out of bounds" severity FAILURE;
ret := input;
if (invert = TRUE) then
-- XXX: Synthesis Hack
--ret(input'length-(index*sub'length)-1 downto input'length-((index+1)*sub'length)) := sub;
for i in 0 to (input'length/sub'length)-1 loop
if (index = i) then
ret(input'length-(i*sub'length)-1 downto input'length-((i+1)*sub'length)) := sub;
end if;
end loop;
else
-- XXX: Synthesis Hack
--ret(((index+1)*sub'length)-1 downto index*sub'length) := sub;
for i in 0 to (input'length/sub'length)-1 loop
if (index = i) then
ret(((i+1)*sub'length)-1 downto i*sub'length) := sub;
end if;
end loop;
end if;
return ret;
end function;
end package body; end package body;

68
src/rtps_package.vhd
View File

@ -594,6 +594,19 @@ package rtps_package is
function to_integer(dw : DOUBLE_WORD_ARRAY) return integer; function to_integer(dw : DOUBLE_WORD_ARRAY) return integer;
function to_unsigned(input : KEY_HASH_TYPE) return unsigned; function to_unsigned(input : KEY_HASH_TYPE) return unsigned;
function to_unsigned(input : GUID_TYPE) return unsigned; function to_unsigned(input : GUID_TYPE) return unsigned;
-- Indexing Function to extract sub-vectors from std_logic_vector signals
-- input SLV from which to extract a sub-vector
-- index The SLV is divided in width-sized sub-vectors. index states which sub-vector to extract (depending on invert)
-- width width of sub-vector (NOTE: SLV must have a length multiple to width)
-- invert If invert=TRUE, index 0 is the leftmost sub-vector, else the rightmost
function get_sub_vector (input : std_logic_vector; index : natural; width : natural; invert : boolean) return std_logic_vector;
-- Indexing Function to write sub-vectors to std_logic_vector signals
-- input SLV from to which to write a sub-vector
-- sub Sub-vector to write into the SLV
-- index The SLV is divided in sub-sized 'sub'-vectors. index states which sub-vector to write (depending on invert)
-- invert If invert=TRUE, index 0 is the leftmost sub-vector, else the rightmost
function write_sub_vector(input : std_logic_vector; sub : std_logic_vector; index : natural; invert : boolean) return std_logic_vector;
end package; end package;
package body rtps_package is package body rtps_package is
@ -1014,4 +1027,59 @@ package body rtps_package is
return ret; return ret;
end function; end function;
function get_sub_vector (input : std_logic_vector; index : natural; width : natural; invert : boolean) return std_logic_vector is
variable ret : std_logic_vector(width-1 downto 0) := (others => '0');
begin
assert(input'length mod width = 0) report "Input Length has to be multiple of width" severity FAILURE;
assert(input'length / width > index) report "Index out of bounds" severity FAILURE;
if (invert = TRUE) then
-- XXX: Synthesis Hack
--ret := input(input'length-(index*width)-1 downto input'length-((index+1)*width));
for i in 0 to (input'length/width)-1 loop
if (index = i) then
ret := input(input'length-(i*width)-1 downto input'length-((i+1)*width));
end if;
end loop;
else
-- XXX: Synthesis Hack
--ret := input(((index+1)*width)-1 downto index*width);
for i in 0 to (input'length/width)-1 loop
if (index = i) then
ret := input(((i+1)*width)-1 downto i*width);
end if;
end loop;
end if;
return ret;
end function;
function write_sub_vector(input : std_logic_vector; sub : std_logic_vector; index : natural; invert : boolean) return std_logic_vector is
variable ret : std_logic_vector(input'length-1 downto 0) := (others => '0');
begin
assert(input'length mod sub'length = 0) report "Input Length has to be multiple of sub width" severity FAILURE;
assert(input'length / sub'length > index) report "Index out of bounds" severity FAILURE;
ret := input;
if (invert = TRUE) then
-- XXX: Synthesis Hack
--ret(input'length-(index*sub'length)-1 downto input'length-((index+1)*sub'length)) := sub;
for i in 0 to (input'length/sub'length)-1 loop
if (index = i) then
ret(input'length-(i*sub'length)-1 downto input'length-((i+1)*sub'length)) := sub;
end if;
end loop;
else
-- XXX: Synthesis Hack
--ret(((index+1)*sub'length)-1 downto index*sub'length) := sub;
for i in 0 to (input'length/sub'length)-1 loop
if (index = i) then
ret(((i+1)*sub'length)-1 downto i*sub'length) := sub;
end if;
end loop;
end if;
return ret;
end function;
end package body; end package body;