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Add Test1 of DDS Writer

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Test RTPS GET_MIN_SN, GET_MAX_SN, GET_CACHE_CHANGE, REMOVE_CACHE_CHANGE,
ACK_CACHE_CHANGE, and NACK_CACHE_CHANGE Operations.
Test DDS Register, Unregister, Write, Dispose, and Lookup Instance
Operations.
This commit is contained in:
Greek 2021-03-21 18:49:59 +01:00
parent 981ca09149
commit a6802cc538
17 changed files with 9659 additions and 892 deletions
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src/REF.txt
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@ -468,7 +468,7 @@ WRITER
+-------------------------------------------------------------+
07| PAYLOAD_ADDRESS |
+-------------------------------------------------------------+
08| INSTANCE_ADDRESS |
08| INSTANCE_ADDRESS | [only if WITH_KEY]
+-------------------------------------------------------------+
09| PREV_ADDRESS |
+-------------------------------------------------------------+
@ -783,6 +783,16 @@ NOTE: Writing data via the write operation on a DataWriter asserts liveliness on
and its DomainParticipant. Consequently the use of assert_liveliness is only needed if the application
is not writing data regularly.
2.2.2.4.2.11 write (DDS)
If (RESOURCE_LIMITS max_samples < RESOURCE_LIMITS max_instances * HISTORY depth), then in the situation
where the max_samples resource limit is exhausted the Service is allowed to discard samples of some other
instance as long as at least one sample remains for such an instance. If it is still not possible to make
space available to store the modification, the writer is allowed to block.
2.2.2.4.2.7 unregister_instance (DDS)
If after that, the application wants to modify (write or dispose) the instance, it has to register it again,
or else use the special handle value HANDLE_NIL.
INVALIDATION
============

58
src/TODO.txt
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@ -66,8 +66,7 @@
- opendds sends Payload Encapsulation with a Key Holder Object (As defined in XType 7.6.8)
- opensplice seems todo the same as opendds
* Currently the builtin-endpoint does only acknowledge SN, but does not negatively acknowledge any SN (Bitamp is always empty).
A writer usually responds with repqirs only to negative acknowledgements.
* Currently a RTPS Writer with DURABILITY TARNSIENT_LOCAL does send historical data to all matched readers, not depending if they are VOLATILE or TRANSIENT_LOCAL.
A writer usually responds with repairs only to negative acknowledgements.
* Assert Heartbeat period > Heartbeat Suppression Period
* Can I request (NACK) SNs that were NOT announced by the writer (> last_sn in Heartbeat)?
* Does AUTOMATIC Liveliness QoS also update the lease on write/assert_liveliness operations?
@ -153,7 +152,14 @@
- 2.2.3 Supported QoS
Partition is marked as RxO=No, but should be RxO=Yes? Or not?
- Existing Issue: https://issues.omg.org/issues/DDS15-245
- How is History QoS affecting MAX_INSTANCES handling (if at all). When is an instance eligibale for
replacement.
- 2.2.2.4.2.5 register_instance
This operation may block and return TIMEOUT under the same circumstances described for the write operation
This operation may return OUT_OF_RESOURCES under the same circumstances described for the write operation
But the opration only returns InstanceHandle_t. Other vendors return HANDLE_NIL also on error and not only
"if the Service does not want to allocate any handle for that instance".
It should propably behave like the Lookup_Instance operation.
* Source Port of SPDP is irrelevant, since it is BEST EFFORT and we do not reply (only Destination Port is of significance)
@ -254,6 +260,23 @@ DESIGN DECISIONS
The RTPS Endpoint will have to output multiple versions of Changes, depending on the connected
Entity, in order to facilitate this design decision.
* Because the Key Hash has to be known in order to make an ACCEPT/REJECT decision for the new
Sample, and the fact that the Key Hash is not always given and has to be manually calculated from
the payload, we need "buffer" slots to store the Sample and Payload until the decision can be
made. This temporal "buffer" is not implemented explicitly, but implicitly by having an extra
slot in the empty list of the memory. The Sample is added to the Empty List Head, and only added
to the occupied list tail if the Sample is accepted. In case an Older Sample needs to be removed
due to the QoS policy, this is done after the Sample Addition has been finalized (has been added
to the Occupied List), because the Sample Removal will modify the Empty List and the new Sample
would be lost if done prior to the finalization.
I.e. a single slot has to be available in the Sample/Payload Memory at all times. This is easy
for the Sample Memory, but more complicated for the Payload memory due to the dynamic slot nature
that it can have. It may happen that after an addition we have a "buffer" Sample Memory Slot, but
no Payload slot. In order to mitigate this we have to actively check the payload memory prior to
the addition and either delete the oldest sample or immediately reject the operation. This may lead
to multiple Sample removals (One prior the addition in order to free up a Payload "buffer", and
one after addition as a result of QoS policies).
* Since the "reading" side needs to have consistent state during it's processing, it does not make
sense to implement dual port RAMs for the History Cache.
@ -282,6 +305,35 @@ DESIGN DECISIONS
Due to the type-specific nature of the entities, those are not instantiated inside the DDS Endpoints,
but will be instantiated in a wrapper and linked through port mapping with the DDS Enspoints.
* Due to the requirements of read_next_instance/take_next_instance of the DDS Reader, the Instances are
inserted in numerical Key Hash order into the Instance Memory. This extra sorting logic is not needed
in the DDS Writer, where Instances are inserted normally to the end of the List.
* The Specification does not really specify how handling of MAX_INSTANCES is affected by the HISTORY QoS
Policy (if at all). The current implementation ignores the HISTORY QoS and only removes stale instances
(Instances that are Unregistered and have all Samples acknowledged).
* According to the DDS Specification the resources taken from an instance can be freed locally if the
instance is Unregistered, and globally if the Instance is Disposed (And all Instance Samples have been
ACKed/READ/Taken). There are scenarios where removing a Disposed, but still registered Instance may
lead to inconsistent behavior (see REF.txt). RTI has thus decided to only delete unregistered
instances. I will copy this behavior.
* DATA WRITER: Once an instance is unregistered, it is eligible for deletion except if it is
Re-registered, or a write operation occurs on that instance. Disposal of an unregistered Instance
does not re-register the instance (State remains NOT_ALIVE) and is still eligible for deletion.
* The DDS Specification does not explicitly state that the behaviour of the Register/Unregister/Dispose
Operations have on non-keyed Topics. RTI basically does a NOP and does not modify the instance in
any way. I basically do a NOP for the Register Operation (in the sense that it does not modify the
instance in any kind of way), but still implemented the Unregister and Dispose Operations, meaning
that the Data Readers will receive a state change.
* The DDS Specification states that if after an Unregister Operation "the application wants to modify
(write or dispose) the instance, it has to register it again, or else use the special handle value
HANDLE_NIL". I do not have this prerequirement. it will return BAD_PARAMETER only if the Instance
is not in the memory anymore.
PROTOCOL UNCOMPLIANCE
=====================
* Partition QoS

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@ -0,0 +1,270 @@
SAMPLE MEMORY: -/0,9,18,27,36
PAYLOAD MEMORY: -/0,11,22,33,44
INSTANCE MEMORY: -/0,8,16
RTPS Operation GET_MIN_SN (Expected SEQUENCENUMBER_UNKNOWN)
RTPS Operation GET_MAX_SN (Expected SEQUENCENUMBER_UNKNOWN)
DDS Operation WRITE [TS 1s, Instance 1] (REJECTED: Instance not Registered)
DDS Operation WRITE [TS 1s, Instance 1, HANDLE_NIL] (ACCEPTED)
SAMPLE MEMORY: 0(I1S1)/9,18,27,36
PAYLOAD MEMORY: 0(I1S1)/11,22,33,44
INSTANCE MEMORY: 0(I1)/8,16
RTPS Operation GET_MIN_SN (Expected SN 1)
RTPS Operation GET_MAX_SN (Expected SN 1)
DDS Operation WRITE [TS 2s, Instance 2, Unaligned Payload (2 Slots)] (REJECTED: Instance not Registered)
DDS Operation REGISTER_INSTANCE 2 (ACCEPTED)
SAMPLE MEMORY: 0(I1S1)/9,18,27,36
PAYLOAD MEMORY: 0(I1S1)/11,22,33,44
INSTANCE MEMORY: 8(I2),0(I1)/16
DDS Operation WRITE [TS 2s, Instance 2, Unaligned Payload (2 Slots)] (ACCEPTED)
SAMPLE MEMORY: 0(I1S1),9(I2S2)/18,27,36
PAYLOAD MEMORY: 0(I1S1),11(I2S2),22(I2S2)/33,44
INSTANCE MEMORY: 8(I2),0(I1)/16
DDS Operation WRITE [TS 3s, Instance 1, Unaligned Payload (2 Slots)] (ACCEPTED)
SAMPLE MEMORY: 0(I1S1),9(I2S2),18(I1S3)/27,36
PAYLOAD MEMORY: 0(I1S1),11(I2S2),22(I2S2),33(I1S3),44(I1S3)/-
INSTANCE MEMORY: 8(I2),0(I1)/16
RTPS Operation GET_CACHE_CHANGE SN 4 (Invalid)
RTPS Operation GET_CACHE_CHANGE SN 1
RTPS Operation GET_CACHE_CHANGE SN 2
RTPS Operation GET_CACHE_CHANGE SN 3
DDS Operation WRITE [TS 4s, Instance 3, HANDLE_NIL, Unaligned Payload (1 Slot)] (REJECTED: Payload Memory Full)
RTPS Operation REMOVE_CACHE_CHANGE SN 5 (Invalid)
RTPS Operation REMOVE_CACHE_CHANGE SN 2
SAMPLE MEMORY: 0(I1S1),18(I1S3)/27,36,9
PAYLOAD MEMORY: 0(I1S1),33(I1S3),44(I1S3)/11,22
INSTANCE MEMORY: 8(I2),0(I1)/16
DDS Operation WRITE [TS 4s, Instance 3, HANDLE_NIL, Unaligned Payload (1 Slot)] (ACCEPTED)
SAMPLE MEMORY: 0(I1S1),18(I1S3),27(I3S4)/36,9
PAYLOAD MEMORY: 0(I1S1),33(I1S3),44(I1S3),11(I3S4)/22
INSTANCE MEMORY: 16(I3),8(I2),0(I1)/-
RTPS Operation GET_CACHE_CHANGE SN 4
DDS Operation REGISTER_INSTANCE 3 (No Change)
DDS Operation DISPOSE [TS 5s, Instance 1] (REJECTED: MAX_SAMPLES_PER_INSTANCE Exceeded)
RTPS Operation ACK_CACHE_CHANGE SN 4
DDS Operation DISPOSE [TS 5s, Instance 1] (REJECTED: MAX_SAMPLES_PER_INSTANCE Exceeded)
RTPS Operation ACK_CACHE_CHANGE SN 1
DDS Operation DISPOSE [TS 5s, Instance 1] (ACCEPTED)
SAMPLE MEMORY: 18(I1S3),27(I3S4),36(I1S5)/9,0
PAYLOAD MEMORY: 33(I1S3),44(I1S3),11(I3S4),22(I1S5)/0
INSTANCE MEMORY: 16(I3),8(I2),0(I1)/-
RTPS Operation GET_MIN_SN (Expected SN 3)
RTPS Operation GET_MAX_SN (Expected SN 5)
RTPS Operation GET_CACHE_CHANGE SN 5
DDS Operation WRITE [TS 6s, Instance 4, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)
RTPS Operation ACK_CACHE_CHANGE SN 3
RTPS Operation ACK_CACHE_CHANGE SN 4
RTPS Operation ACK_CACHE_CHANGE SN 5
DDS Operation WRITE [TS 6s, Instance 4, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)
DDS Operation UNREGISTER_INSTANCE [TS 6s, Instance 1] (ACCEPTED)
SAMPLE MEMORY: 27(I3S4),36(I1S5),9(I1S6)/0,18
PAYLOAD MEMORY: 11(I3S4),22(I1S5),0(I1S6)/33,44
INSTANCE MEMORY: 16(I3),8(I2),0(I1)/-
RTPS Operation GET_MIN_SN (Expected SN 4)
RTPS Operation GET_MAX_SN (Expected SN 6)
RTPS Operation GET_CACHE_CHANGE SN 6
DDS Operation WRITE [TS 7s, Instance 4, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)
RTPS Operation ACK_CACHE_CHANGE SN 6
DDS Operation WRITE [TS 7s, Instance 4, HANDLE_NIL, Aligned Payload] (ACCEPTED)
SAMPLE MEMORY: 27(I3S4),0(I4S7)/18,36,9
PAYLOAD MEMORY: 11(I3S4),33(I4S7)/0,22,44
INSTANCE MEMORY: 0(I4),16(I3),8(I2)/-
RTPS Operation GET_CACHE_CHANGE SN 5 (Invalid)
RTPS Operation GET_CACHE_CHANGE SN 6 (Invalid)
RTPS Operation GET_CACHE_CHANGE SN 7
DDS Operation WRITE [TS 8s, Instance 2, Unaligned Payload (2 Slots)] (ACCEPTED)
SAMPLE MEMORY: 27(I3S4),0(I4S7),18(I2S8)/36,9
PAYLOAD MEMORY: 11(I3S4),33(I4S7),0(I2S8),22(I2S8)/44
INSTANCE MEMORY: 0(I4),16(I3),8(I2)/-
DDS Operation WRITE [TS 9s, Instance 1, Aligned Payload] (REJECTED: Instance not Registered)
DDS Operation REGISTER_INSTANCE 1 (REJECTED: MAX_INSTANCES exceeded)
DDS Operation UNREGISTER_INSTANCE [TS 9s, Instance 3] (ACCEPTED)
SAMPLE MEMORY: 27(I3S4),0(I4S7),18(I2S8),36(I3S9)/9
PAYLOAD MEMORY: 11(I3S4),33(I4S7),0(I2S8),22(I2S8),44(I3S9)/-
INSTANCE MEMORY: 0(I4),16(I3),8(I2)/-
RTPS Operation GET_MIN_SN (Expected SN 4)
RTPS Operation GET_MAX_SN (Expected SN 9)
RTPS Operation GET_CACHE_CHANGE SN 8
RTPS Operation GET_CACHE_CHANGE SN 9
RTPS Operation ACK_CACHE_CHANGE SN 9
DDS Operation REGISTER_INSTANCE 1 (ACCPETED)
SAMPLE MEMORY: 0(I4S7),18(I2S8)/9,27,36
PAYLOAD MEMORY: 33(I4S7),0(I2S8),22(I2S8)/44,11
INSTANCE MEMORY: 16(I1),0(I4),8(I2)/-
DDS Operation WRITE [TS 10s, Instance 1, Aligned Payload] (ACCEPTED)
SAMPLE MEMORY: 0(I4S7),18(I2S8),9(I1S10)/27,36
PAYLOAD MEMORY: 33(I4S7),0(I2S8),22(I2S8),44(I1S10)/11
INSTANCE MEMORY: 16(I1),0(I4),8(I2)/-
DDS Operation WRITE [TS 11s, Instance 1, Aligned Payload] (ACCEPTED)
SAMPLE MEMORY: 0(I4S7),18(I2S8),9(I1S10),27(I4S11)/36
PAYLOAD MEMORY: 33(I4S7),0(I2S8),22(I2S8),44(I1S10),11(I4S11)/-
INSTANCE MEMORY: 16(I1),0(I4),8(I2)/-
DDS Operation WRITE [TS 12s, Instance 2, Aligned Payload] (REJECTED: Payload Memory Full)
RTPS Operation ACK_CACHE_CHANGE SN 8
DDS Operation WRITE [TS 12s, Instance 2, Aligned Payload] (ACCEPTED)
SAMPLE MEMORY: 0(I4S7),9(I1S10),27(I4S11),36(I2S12)/18
PAYLOAD MEMORY: 33(I4S7),44(I1S10),11(I4S11),0(I2S12)/22
INSTANCE MEMORY: 16(I1),0(I4),8(I2)/-
DDS Operation WRITE [TS 13s, Instance 4, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded)
RTPS Operation ACK_CACHE_CHANGE SN 7
DDS Operation WRITE [TS 13s, Instance 4, Aligned Payload] (ACCEPTED)
SAMPLE MEMORY: 9(I1S10),27(I4S11),36(I2S12),18(I4S13)/0
PAYLOAD MEMORY: 44(I1S10),11(I4S11),0(I2S12),22(I4S13)/33
INSTANCE MEMORY: 16(I1),0(I4),8(I2)/-
RTPS Operation GET_MIN_SN (Expected SN 4)
RTPS Operation GET_MAX_SN (Expected SN 9)
RTPS Operation GET_CACHE_CHANGE SN 10
RTPS Operation GET_CACHE_CHANGE SN 11
RTPS Operation GET_CACHE_CHANGE SN 12
RTPS Operation GET_CACHE_CHANGE SN 13
RTPS Operation ACK_CACHE_CHANGE SN 12
DDS Operation UNREGISTER_INSTANCE [TS 14s, Instance 2] (ACCEPTED)
SAMPLE MEMORY: 9(I1S10),27(I4S11),18(I4S13),0(I2S14)/36
PAYLOAD MEMORY: 44(I1S10),11(I4S11),22(I4S13),33(I2S14)/0
INSTANCE MEMORY: 16(I1),0(I4),8(I2)/-
RTPS Operation ACK_CACHE_CHANGE SN 11
DDS Operation WRITE [TS 15s, Instance 4, Aligned Payload (2 Slots)] (REJECTED: Payload Memory Full)
RTPS Operation REMOVE_CACHE_CHANGE SN 11
SAMPLE MEMORY: 9(I1S10),18(I4S13),0(I2S14)/36,27
PAYLOAD MEMORY: 44(I1S10),22(I4S13),33(I2S14)/11,0
INSTANCE MEMORY: 16(I1),0(I4),8(I2)/-
DDS Operation WRITE [TS 15s, Instance 4, Aligned Payload (2 Slots)] (ACCEPTED)
SAMPLE MEMORY: 9(I1S10),18(I4S13),0(I2S14),36(I4S15)/27
PAYLOAD MEMORY: 44(I1S10),22(I4S13),33(I2S14),11(I4S15),0(I4S15)/-
INSTANCE MEMORY: 16(I1),0(I4),8(I2)/-
DDS Operation UNREGISTER_INSTANCE [TS 16s, Instance 1] (REJECTED: Payload memory Full, MAX_SAMPLES exceeded)
RTPS Operation ACK_CACHE_CHANGE SN 10
DDS Operation UNREGISTER_INSTANCE [TS 16s, Instance 1] (ACCEPTED)
SAMPLE MEMORY: 18(I4S13),0(I2S14),36(I4S15),27(I1S16)/9
PAYLOAD MEMORY: 22(I4S13),33(I2S14),11(I4S15),0(I4S15),44(I1S16)/-
INSTANCE MEMORY: 16(I1),0(I4),8(I2)/-
DDS Operation DISPOSE [TS 17s, Instance 3] (REJECTED: Payload memory Full, MAX_SAMPLES exceeded)
RTPS Operation ACK_CACHE_CHANGE SN 13
RTPS Operation ACK_CACHE_CHANGE SN 14
DDS Operation DISPOSE [TS 17s, Instance 3] (ACCEPTED)
SAMPLE MEMORY: 36(I4S15),27(I1S16),9(I3S17)/18,0
PAYLOAD MEMORY: 11(I4S15),0(I4S15),44(I1S16),22(I3S17)/33
INSTANCE MEMORY: 8(I3),16(I1),0(I4)/-
RTPS Operation GET_MIN_SN (Expected SN 15)
RTPS Operation GET_MAX_SN (Expected SN 17)
RTPS Operation GET_CACHE_CHANGE SN 15
RTPS Operation GET_CACHE_CHANGE SN 16
RTPS Operation GET_CACHE_CHANGE SN 17
RTPS Operation REMOVE_CACHE_CHANGE SN 15
SAMPLE MEMORY: 27(I1S16),9(I3S17)/18,0,36
PAYLOAD MEMORY: 44(I1S16),22(I3S17)/11,0,33
INSTANCE MEMORY: 8(I3),16(I1),0(I4)/-
DDS Operation WRITE [TS 18s, Instance 3, Aligned Payload] (ACCEPTED)
SAMPLE MEMORY: 27(I1S16),9(I3S17),18(I3S18)/0,36
PAYLOAD MEMORY: 44(I1S16),22(I3S17),11(I3S18)/0,33
INSTANCE MEMORY: 8(I3),16(I1),0(I4)/-
DDS Operation WRITE [TS 19s, Instance 4, Aligned Payload] (ACCEPTED)
SAMPLE MEMORY: 27(I1S16),9(I3S17),18(I3S18),0(I4S19)/36
PAYLOAD MEMORY: 44(I1S16),22(I3S17),11(I3S18),0(I4S19)/33
INSTANCE MEMORY: 8(I3),16(I1),0(I4)/-
DDS Operation WRITE [TS 20s, Instance 2, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded, MAX_INSTANCES exceeded)
RTPS Operation ACK_CACHE_CHANGE SN 16
DDS Operation WRITE [TS 20s, Instance 2, Aligned Payload] (ACCEPTED)
SAMPLE MEMORY: 9(I3S17),18(I3S18),0(I4S19),36(I2S20)/27
PAYLOAD MEMORY: 22(I3S17),11(I3S18),0(I4S19),33(I2S20)/44
INSTANCE MEMORY: 16(I2),8(I3),0(I4)/-
RTPS Operation ACK_CACHE_CHANGE SN 17
DDS Operation UNREGISTER_INSTANCE [TS 21s, Instance 4] (ACCEPTED)
SAMPLE MEMORY: 18(I3S18),0(I4S19),36(I2S20),27(I4S21)/9
PAYLOAD MEMORY: 11(I3S18),0(I4S19),33(I2S20),44(I4S21)/22
INSTANCE MEMORY: 16(I2),8(I3),0(I4)/-
RTPS Operation ACK_CACHE_CHANGE SN 19
DDS Operation WRITE [TS 22s, Instance 1, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded, MAX_INSTANCES exceeded)
RTPS Operation REMOVE_CACHE_CHANGE SN 19
SAMPLE MEMORY: 18(I3S18),36(I2S20),27(I4S21)/9,0
PAYLOAD MEMORY: 11(I3S18),33(I2S20),44(I4S21)/0,22
INSTANCE MEMORY: 16(I2),8(I3),0(I4)/-
RTPS Operation REMOVE_CACHE_CHANGE SN 21
SAMPLE MEMORY: 18(I3S18),36(I2S20)/9,0,27
PAYLOAD MEMORY: 11(I3S18),33(I2S20)/44,0,22
INSTANCE MEMORY: 16(I2),8(I3),0(I4)/-
DDS Operation UNREGISTER_INSTANCE [TS 22s, Instance 2] (ACCEPTED)
SAMPLE MEMORY: 18(I3S18),36(I2S20),9(I2S22)/0,27
PAYLOAD MEMORY: 11(I3S18),33(I2S20),44(I2S22)/0,22
INSTANCE MEMORY: 16(I2),8(I3),0(I4)/-
DDS Operation UNREGISTER_INSTANCE [TS 23s, Instance 3] (ACCEPTED)
SAMPLE MEMORY: 18(I3S18),36(I2S20),9(I2S22),0(I3S23)/27
PAYLOAD MEMORY: 11(I3S18),33(I2S20),44(I2S22),0(I3S23)/22
INSTANCE MEMORY: 16(I2),8(I3),0(I4)/-
DDS Operation WRITE [TS 24s, Instance 1, Aligned Payload] (REJECTED: MAX_SAMPLES exceeded, MAX_INSTANCES exceeded)
RTPS Operation ACK_CACHE_CHANGE SN 20
DDS Operation WRITE [TS 24s, Instance 1, Aligned Payload] (ACCEPTED)
SAMPLE MEMORY: 18(I3S18),9(I2S22),0(I3S23),27(I1S24)/36
PAYLOAD MEMORY: 11(I3S18),44(I2S22),0(I3S23),22(I1S24)/33
INSTANCE MEMORY: 0(I1),16(I2),8(I3)/-
RTPS Operation ACK_CACHE_CHANGE SN 22
RTPS Operation NACK_CACHE_CHANGE SN 22
DDS Operation REGISTER_INSTANCE 4 (REJECTED: MAX_INSTANCES exceeded)
RTPS Operation ACK_CACHE_CHANGE SN 22
DDS Operation REGISTER_INSTANCE 2 (ACCEPTED)
DDS Operation REGISTER_INSTANCE 4 (REJECTED: MAX_INSTANCES exceeded)
RTPS Operation ACK_CACHE_CHANGE SN 18
RTPS Operation ACK_CACHE_CHANGE SN 23
DDS Operation WRITE [TS 25s, Instance 3, Aligned Payload] (ACCEPTED)
SAMPLE MEMORY: 9(I2S22),0(I3S23),27(I1S24),36(I3S25)/18
PAYLOAD MEMORY: 44(I2S22),0(I3S23),22(I1S24),33(I3S25)/11
INSTANCE MEMORY: 0(I1),16(I2),8(I3)/-
DDS Operation REGISTER_INSTANCE 4 (REJECTED: MAX_INSTANCES exceeded)
DDS Operation UNREGISTER_INSTANCE [TS 26s, Instance 4] (REJECTED: Instance not Registered)
RTPS Operation NACK_CACHE_CHANGE SN 22
RTPS Operation NACK_CACHE_CHANGE SN 23
DDS Operation UNREGISTER_INSTANCE [TS 26s, Instance 3] (REJECTED: MAX_SAMPLES_PER_INSTANCE exceeded, MAX_SAMPLES exceeded)
RTPS Operation ACK_CACHE_CHANGE SN 22
DDS Operation UNREGISTER_INSTANCE [TS 26s, Instance 3] (REJECTED: MAX_SAMPLES_PER_INSTANCE exceeded, MAX_SAMPLES exceeded)
RTPS Operation ACK_CACHE_CHANGE SN 23
DDS Operation UNREGISTER_INSTANCE [TS 26s, Instance 3] (ACCEPTED)
SAMPLE MEMORY: 9(I2S22),27(I1S24),36(I3S25),18(I3S26)/0
PAYLOAD MEMORY: 44(I2S22),22(I1S24),33(I3S25),11(I3S26)/0
INSTANCE MEMORY: 0(I1),16(I2),8(I3)/-
RTPS Operation ACK_CACHE_CHANGE SN 25
DDS Operation DISPOSE [TS 27s, Instance 3] (ACCEPTED)
SAMPLE MEMORY: 9(I2S22),27(I1S24),18(I3S26),0(I3S27)/36
PAYLOAD MEMORY: 44(I2S22),22(I1S24),11(I3S26),0(I3S27)/33
INSTANCE MEMORY: 0(I1),16(I2),8(I3)/-
RTPS Operation ACK_CACHE_CHANGE SN 26
RTPS Operation ACK_CACHE_CHANGE SN 27
DDS Operation REGISTER_INSTANCE 4 (ACCEPTED)
SAMPLE MEMORY: 9(I2S22),27(I1S24)/36,18,0
PAYLOAD MEMORY: 44(I2S22),22(I1S24)/0,11,33
INSTANCE MEMORY: 8(I4),0(I1),16(I2)/-
RTPS Operation GET_MIN_SN (Expected SN 22)
RTPS Operation GET_MAX_SN (Expected SN 24)
RTPS Operation GET_CACHE_CHANGE SN 22
RTPS Operation GET_CACHE_CHANGE SN 24
RTPS Operation NACK_CACHE_CHANGE SN 22
RTPS Operation NACK_CACHE_CHANGE SN 24
DDS Operation WRITE [TS 28s, Instance 4, Aligned Payload] (ACCEPTED)
SAMPLE MEMORY: 9(I2S22),27(I1S24),36(I4S28)/18,0
PAYLOAD MEMORY: 44(I2S22),22(I1S24),0(I4S28)/11,33
INSTANCE MEMORY: 8(I4),0(I1),16(I2)/-
DDS Operation WRITE [TS 29s, Instance 2, Aligned Payload] (ACCEPTED)
SAMPLE MEMORY: 9(I2S22),27(I1S24),36(I4S28),18(I2S29)/0
PAYLOAD MEMORY: 44(I2S22),22(I1S24),0(I4S28),11(I2S29)/33
INSTANCE MEMORY: 8(I4),0(I1),16(I2)/-
RTPS Operation ACK_CACHE_CHANGE SN 24
RTPS Operation ACK_CACHE_CHANGE SN 28
DDS Operation WRITE [TS 30s, Instance 1, Aligned Payload] (ACCEPTED)
SAMPLE MEMORY: 9(I2S22),36(I4S28),18(I2S29),0(I1S30)/27
PAYLOAD MEMORY: 44(I2S22),0(I4S28),11(I2S29),33(I1S30)/22
INSTANCE MEMORY: 8(I4),0(I1),16(I2)/-
RTPS Operation REMOVE_CACHE_CHANGE SN 28
SAMPLE MEMORY: 9(I2S22),18(I2S29),0(I1S30)/27,36
PAYLOAD MEMORY: 44(I2S22),11(I2S29),33(I1S30)/0,22
INSTANCE MEMORY: 8(I4),0(I1),16(I2)/-
RTPS Operation ACK_CACHE_CHANGE SN 22
RTPS Operation ACK_CACHE_CHANGE SN 29
DDS Operation WRITE [TS 31s, Instance 2, Aligned Payload] (ACCEPTED)
SAMPLE MEMORY: 18(I2S29),0(I1S30),27(I2S31)/36,9
PAYLOAD MEMORY: 11(I2S29),33(I1S30),0(I2S31)/44,22
INSTANCE MEMORY: 8(I4),0(I1),16(I2)/-
RTPS Operation GET_MIN_SN (Expected SN 29)
RTPS Operation GET_MAX_SN (Expected SN 31)
RTPS Operation GET_CACHE_CHANGE SN 29
RTPS Operation GET_CACHE_CHANGE SN 30
RTPS Operation GET_CACHE_CHANGE SN 31
DDS Operation LOOKUP_INSTANCE [Instance 1]
DDS Operation LOOKUP_INSTANCE [Unknown Instance]

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SAMPLE MEMORY: -/0,8,16,24,32
PAYLOAD MEMORY: -/0,11,22,33,44
RTPS Operation GET_MIN_SN (Expected SEQUENCENUMBER_UNKNOWN)
RTPS Operation GET_MAX_SN (Expected SEQUENCENUMBER_UNKNOWN)
DDS Operation WRITE [TS 1s, Aligned Payload] (ACCEPTED)
SAMPLE MEMORY: 0(S1)/8,16,24,32
PAYLOAD MEMORY: 0(S1)/11,22,33,44
DDS Operation WRITE [TS 2s, Unaligned Payload (2 Slots)] (ACCEPTED)
SAMPLE MEMORY: 0(S1),8(S2)/16,24,32
PAYLOAD MEMORY: 0(S1),11(S2),22(S2)/33,44
DDS Operation REGISTER_INSTANCE 2 (Illegal Operation)
DDS Operation DISPOSE [TS 3s] (ACCEPTED)
SAMPLE MEMORY: 0(S1),8(S2),16(S3)/24,32
PAYLOAD MEMORY: 0(S1),11(S2),22(S2),33(S3)/44
RTPS Operation GET_MIN_SN (Expected SN 1)
RTPS Operation GET_MAX_SN (Expected SN 3)
RTPS Operation GET_CACHE_CHANGE SN 4 (Invalid)
RTPS Operation GET_CACHE_CHANGE SN 1
RTPS Operation GET_CACHE_CHANGE SN 2
RTPS Operation GET_CACHE_CHANGE SN 3
DDS Operation WRITE [TS 2s, Aligned Payload] (ACCEPTED)
SAMPLE MEMORY: 0(S1),8(S2),16(S3),24(S4)/32
PAYLOAD MEMORY: 0(S1),11(S2),22(S2),33(S3),44(S4)/-
DDS Operation UNREGISTER_INSTANCE [TS 5s] (REJECTED: Payload Memory Full)
RTPS Operation ACK_CACHE_CHANGE SN 1
DDS Operation UNREGISTER_INSTANCE [TS 5s] (ACCEPTED)
SAMPLE MEMORY: 8(S2),16(S3),24(S4),32(S5)/0
PAYLOAD MEMORY: 11(S2),22(S2),33(S3),44(S4),0(S5)/-
DDS Operation WRITE [TS 6s, Aligned Payload] (REJECTED: Payload Memory Full)
RTPS Operation ACK_CACHE_CHANGE SN 2
RTPS Operation ACK_CACHE_CHANGE SN 3
RTPS Operation NACK_CACHE_CHANGE SN 2
DDS Operation WRITE [TS 6s, Aligned Payload] (ACCEPTED)
SAMPLE MEMORY: 8(S2),24(S4),32(S5),0(S6)/16
PAYLOAD MEMORY: 11(S2),22(S2),44(S4),0(S5),33(S6)/-
DDS Operation DISPOSE [TS 7s] (REJECTED: Payload Memory Full)
RTPS Operation ACK_CACHE_CHANGE SN 2
RTPS Operation ACK_CACHE_CHANGE SN 2
DDS Operation DISPOSE [TS 7s] (ACCEPTED)
SAMPLE MEMORY: 24(S4),32(S5),0(S6),16(S7)/8
PAYLOAD MEMORY: 44(S4),0(S5),33(S6),11(S7)/22
DDS Operation UNREGISTER_INSTANCE [TS 8s] (REJECTED: MAX_SAMPLES exceeded)
RTPS Operation ACK_CACHE_CHANGE SN 5
DDS Operation UNREGISTER_INSTANCE [TS 8s] (ACCEPTED)
SAMPLE MEMORY: 24(S4),0(S6),16(S7),8(S8)/32
PAYLOAD MEMORY: 44(S4),33(S6),11(S7),22(S8)/0
RTPS Operation GET_MIN_SN (Expected SN 4)
RTPS Operation GET_MAX_SN (Expected SN 8)
RTPS Operation GET_CACHE_CHANGE SN 4
RTPS Operation GET_CACHE_CHANGE SN 6
RTPS Operation GET_CACHE_CHANGE SN 7
RTPS Operation GET_CACHE_CHANGE SN 8
RTPS Operation ACK_CACHE_CHANGE SN 6
RTPS Operation ACK_CACHE_CHANGE SN 8
DDS Operation DISPOSE [TS 9s] (ACCEPTED)
SAMPLE MEMORY: 24(S4),16(S7),8(S8),32(S9)/0
PAYLOAD MEMORY: 44(S4),11(S7),22(S8),0(S9)/33
DDS Operation UNREGISTER_INSTANCE [TS 10s] (ACCEPTED)
SAMPLE MEMORY: 24(S4),16(S7),32(S9),0(S10)/8
PAYLOAD MEMORY: 44(S4),11(S7),0(S9),33(S10)/22
RTPS Operation ACK_CACHE_CHANGE SN 7
DDS Operation WRITE [TS 11s, Aligned Payload (2 Slots)] (REJECTED: Payload Memory Full)
RTPS Operation REMOVE_CACHE_CHANGE SN 12 (Invalid)
RTPS Operation REMOVE_CACHE_CHANGE SN 4
SAMPLE MEMORY: 16(S7),32(S9),0(S10)/8,24
PAYLOAD MEMORY: 11(S7),0(S9),33(S10)/44,22
DDS Operation WRITE [TS 11s, Aligned Payload (2 Slots)] (ACCEPTED)
SAMPLE MEMORY: 16(S7),32(S9),0(S10),8(S11)/24
PAYLOAD MEMORY: 11(S7),0(S9),33(S10),44(S11),22(S11)/-

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SAMPLE MEMORY: -/0,9,18,27,36
PAYLOAD MEMORY: -/0,11,22,33,44
INSTANCE MEMORY: -/0,8,16
RTPS Operation GET_MIN_SN (Expected SEQUENCENUMBER_UNKNOWN)
RTPS Operation GET_MAX_SN (Expected SEQUENCENUMBER_UNKNOWN)
DDS Operation WRITE [TS 1s, Instance 1, Aligned Payload] (REJECTED: Instance not Registered)
DDS Operation WRITE [TS 1s, Instance 1, HANDLE_NIL, Aligned Payload] (ACCEPTED)
SAMPLE MEMORY: 0(I1S1)/9,18,27,36
PAYLOAD MEMORY: 0(I1S1)/11,22,33,44
INSTANCE MEMORY: 0(I1)/8,16
RTPS Operation GET_MIN_SN (Expected SN 1)
RTPS Operation GET_MAX_SN (Expected SN 1)
DDS Operation WRITE [TS 1s, Instance 1, Unaligned Payload (2 Slots)] (ACCEPTED)
SAMPLE MEMORY: 0(I1S1),9(I1S2)/18,27,36
PAYLOAD MEMORY: 0(I1S1),11(I1S2),22(I1S2)/33,44
INSTANCE MEMORY: 0(I1)/8,16
DDS Operation DISPOSE [TS 3s, Instance 2] (REJECTED: Instance not Registered)
DDS Operation REGISTER_INSTANCE 2 (ACCEPTED)
SAMPLE MEMORY: 0(I1S1),9(I1S2)/18,27,36
PAYLOAD MEMORY: 0(I1S1),11(I1S2),22(I1S2)/33,44
INSTANCE MEMORY: 8(I2),0(I1)/16
DDS Operation DISPOSE [TS 3s, Instance 1] (ACCEPTED)
SAMPLE MEMORY: 0(I1S1),9(I1S2),18(I2S3)/27,36
PAYLOAD MEMORY: 0(I1S1),11(I1S2),22(I1S2),33(I2S3)/44
INSTANCE MEMORY: 8(I2),0(I1)/16
RTPS Operation GET_MIN_SN (Expected SN 1)
RTPS Operation GET_MAX_SN (Expected SN 3)
RTPS Operation GET_CACHE_CHANGE SN 4 (Invalid)
RTPS Operation GET_CACHE_CHANGE SN 1
RTPS Operation GET_CACHE_CHANGE SN 2
RTPS Operation GET_CACHE_CHANGE SN 3
DDS Operation WRITE [TS 4s, Instance 1, Aligned Payload] (ACCEPTED)
SAMPLE MEMORY: 0(I1S1),9(I1S2),18(I2S3),27(I2S4)/36
PAYLOAD MEMORY: 0(I1S1),11(I1S2),22(I1S2),33(I2S3),44(I2S4)/-
INSTANCE MEMORY: 8(I2),0(I1)/16
DDS Operation WRITE [TS 5s, Instance 3, HANDLE_NIL, Aligned Payload] (ACCEPTED)
SAMPLE MEMORY: 9(I1S2),18(I2S3),27(I2S4),36(I3S5)/0
PAYLOAD MEMORY: 11(I1S2),22(I1S2),33(I2S3),44(I2S4),0(I3S5)/-
INSTANCE MEMORY: 16(I3),8(I2),0(I1)/-
RTPS Operation ACK_CACHE_CHANGE SN 3
DDS Operation WRITE [TS 6s, Instance 3, Aligned Payload] (ACCEPTED)
SAMPLE MEMORY: 9(I1S2),27(I2S4),36(I3S5),0(I3S6)/18
PAYLOAD MEMORY: 11(I1S2),22(I1S2),44(I2S4),0(I3S5),33(I3S6)/-
INSTANCE MEMORY: 16(I3),8(I2),0(I1)/-
RTPS Operation GET_MIN_SN (Expected SN 2)
RTPS Operation GET_MAX_SN (Expected SN 6)
RTPS Operation GET_CACHE_CHANGE SN 2
RTPS Operation GET_CACHE_CHANGE SN 4
RTPS Operation GET_CACHE_CHANGE SN 5
RTPS Operation GET_CACHE_CHANGE SN 6
DDS Operation DISPOSE [TS 7s, Instance 1] (ACCEPTED)
SAMPLE MEMORY: 27(I2S4),36(I3S5),0(I3S6),18(I1S7)/9
PAYLOAD MEMORY: 44(I2S4),0(I3S5),33(I3S6),11(I1S7)/22
INSTANCE MEMORY: 16(I3),8(I2),0(I1)/-
RTPS Operation ACK_CACHE_CHANGE SN 5
DDS Operation WRITE [TS 8s, Instance 2, Aligned Payload (2 Slots)] (REJECTED: Payload Memory Full)
RTPS Operation REMOVE_CACHE_CHANGE SN 3 (Invalid)
RTPS Operation REMOVE_CACHE_CHANGE SN 5
SAMPLE MEMORY: 27(I2S4),0(I3S6),18(I1S7)/9,36
PAYLOAD MEMORY: 44(I2S4),33(I3S6),11(I1S7)/0,22
INSTANCE MEMORY: 16(I3),8(I2),0(I1)/-
DDS Operation WRITE [TS 8s, Instance 2, Aligned Payload (2 Slots)] (ACCEPTED)
SAMPLE MEMORY: 27(I2S4),0(I3S6),18(I1S7),9(I2S8)/36
PAYLOAD MEMORY: 44(I2S4),33(I3S6),11(I1S7),0(I2S8),22(I2S8)/-
INSTANCE MEMORY: 16(I3),8(I2),0(I1)/-
RTPS Operation ACK_CACHE_CHANGE SN 7
DDS Operation DISPOSE [TS 9s, Instance 3] (ACCEPTED)
SAMPLE MEMORY: 27(I2S4),0(I3S6),9(I2S8),36(I3S9)/18
PAYLOAD MEMORY: 44(I2S4),33(I3S6),0(I2S8),22(I2S8),11(I3S9)/-
INSTANCE MEMORY: 16(I3),8(I2),0(I1)/-
RTPS Operation GET_MIN_SN (Expected SN 4)
RTPS Operation GET_MAX_SN (Expected SN 9)
RTPS Operation GET_CACHE_CHANGE SN 4
RTPS Operation GET_CACHE_CHANGE SN 6
RTPS Operation GET_CACHE_CHANGE SN 8
RTPS Operation GET_CACHE_CHANGE SN 9
DDS Operation UNREGISTER_INSTANCE [TS 10s, Instance 1] (ACCEPTED)
SAMPLE MEMORY: 0(I3S6),9(I2S8),36(I3S9),18(I1S10)/27
PAYLOAD MEMORY: 33(I3S6),0(I2S8),22(I2S8),11(I3S9),44(I1S10)/-
INSTANCE MEMORY: 16(I3),8(I2),0(I1)/-
RTPS Operation ACK_CACHE_CHANGE SN 9
DDS Operation UNREGISTER_INSTANCE [TS 11s, Instance 2] (ACCEPTED)
SAMPLE MEMORY: 0(I3S6),9(I2S8),18(I1S10),27(I2S11)/36
PAYLOAD MEMORY: 33(I3S6),0(I2S8),22(I2S8),44(I1S10),11(I2S11)/-
INSTANCE MEMORY: 16(I3),8(I2),0(I1)/-
RTPS Operation ACK_CACHE_CHANGE SN 6
RTPS Operation ACK_CACHE_CHANGE SN 8
RTPS Operation ACK_CACHE_CHANGE SN 11
DDS Operation WRITE [TS 12s, Instance 4, HANDLE_NIL, Aligned Payload] (ACCEPTED)
SAMPLE MEMORY: 18(I1S10),36(I4S12)/0,9,27
PAYLOAD MEMORY: 44(I1S10),33(I4S12)/11,0,22
INSTANCE MEMORY: 8(I4),16(I3),0(I1)/-
RTPS Operation GET_MIN_SN (Expected SN 10)
RTPS Operation GET_MAX_SN (Expected SN 12)
RTPS Operation GET_CACHE_CHANGE SN 10
RTPS Operation GET_CACHE_CHANGE SN 12
DDS Operation REGISTER_INSTANCE 2 (REJECTED: MAX_INSTANCES exceeded)
RTPS Operation ACK_CACHE_CHANGE SN 10
DDS Operation REGISTER_INSTANCE 2 (ACCEPTED)
SAMPLE MEMORY: 36(I4S12)/0,9,27,18
PAYLOAD MEMORY: 33(I4S12)/44,11,0,22
INSTANCE MEMORY: 0(I2),8(I4),16(I3)/-
DDS Operation WRITE [TS 13s, Instance 2, Aligned Payload] (ACCEPTED)
SAMPLE MEMORY: 36(I4S12),0(I2S13)/9,27,18
PAYLOAD MEMORY: 33(I4S12),44(I2S13)/11,0,22
INSTANCE MEMORY: 0(I2),8(I4),16(I3)/-
DDS Operation REGISTER_INSTANCE 2 (ACCEPTED)
DDS Operation WRITE [TS 14s, Instance 2, Aligned Payload] (ACCEPTED)
SAMPLE MEMORY: 36(I4S12),0(I2S13),9(I2S14)/27,18
PAYLOAD MEMORY: 33(I4S12),44(I2S13),11(I2S14)/0,22
INSTANCE MEMORY: 0(I2),8(I4),16(I3)/-
DDS Operation WRITE [TS 15s, Instance 2, Aligned Payload] (ACCEPTED)
SAMPLE MEMORY: 36(I4S12),9(I2S14),27(I2S15)/18,0
PAYLOAD MEMORY: 33(I4S12),11(I2S14),0(I2S15)/44,22
INSTANCE MEMORY: 0(I2),8(I4),16(I3)/-
RTPS Operation ACK_CACHE_CHANGE SN 15
DDS Operation WRITE [TS 16s, Instance 2, Aligned Payload] (ACCEPTED)
SAMPLE MEMORY: 36(I4S12),9(I2S14),18(I2S16)/0,27
PAYLOAD MEMORY: 33(I4S12),11(I2S14),44(I2S16)/0,22
INSTANCE MEMORY: 0(I2),8(I4),16(I3)/-
RTPS Operation ACK_CACHE_CHANGE SN 12
DDS Operation UNREGISTER_INSTANCE [TS 17s, Instance 2] (ACCEPTED)
SAMPLE MEMORY: 36(I4S12),18(I2S16),0(I2S17)/27,9
PAYLOAD MEMORY: 33(I4S12),44(I2S16),0(I2S17)/11,22
INSTANCE MEMORY: 0(I2),8(I4),16(I3)/-
RTPS Operation GET_MIN_SN (Expected SN 12)
RTPS Operation GET_MAX_SN (Expected SN 17)
RTPS Operation GET_CACHE_CHANGE SN 12
RTPS Operation GET_CACHE_CHANGE SN 16
RTPS Operation GET_CACHE_CHANGE SN 17
DDS Operation UNREGISTER_INSTANCE [TS 18s, Instance 4] (ACCEPTED)
SAMPLE MEMORY: 36(I4S12),18(I2S16),0(I2S17),27(I4S18)/9
PAYLOAD MEMORY: 33(I4S12),44(I2S16),0(I2S17),11(I4S178)/22
INSTANCE MEMORY: 0(I2),8(I4),16(I3)/-
RTPS Operation NACK_CACHE_CHANGE SN 12
RTPS Operation ACK_CACHE_CHANGE SN 18
DDS Operation UNREGISTER_INSTANCE [TS 19s, Instance 3] (ACCEPTED)
SAMPLE MEMORY: 36(I4S12),18(I2S16),0(I2S17),9(I3S19)/27
PAYLOAD MEMORY: 33(I4S12),44(I2S16),0(I2S17),22(I3S19)/11
INSTANCE MEMORY: 0(I2),8(I4),16(I3)/-
DDS Operation WRITE [TS 20s, Instance 3, Aligned Payload] (ACCEPTED)
SAMPLE MEMORY: 18(I2S16),0(I2S17),9(I3S19),27(I3S20)/36
PAYLOAD MEMORY: 44(I2S16),0(I2S17),22(I3S19),11(I3S20)/33
INSTANCE MEMORY: 0(I2),8(I4),16(I3)/-
DDS Operation WRITE [TS 21s, Instance 3, Aligned Payload] (ACCEPTED)
SAMPLE MEMORY: 18(I2S16),0(I2S17),27(I3S20),36(I3S21)/9
PAYLOAD MEMORY: 44(I2S16),0(I2S17),11(I3S20),33(I3S21)/22
INSTANCE MEMORY: 0(I2),8(I4),16(I3)/-
RTPS Operation ACK_CACHE_CHANGE SN 16
DDS Operation WRITE [TS 22s, Instance 3, Aligned Payload] (ACCEPTED)
SAMPLE MEMORY: 18(I2S16),0(I2S17),36(I3S21),9(I3S22)/27
PAYLOAD MEMORY: 44(I2S16),0(I2S17),33(I3S21),22(I3S22)/11
INSTANCE MEMORY: 0(I2),8(I4),16(I3)/-
RTPS Operation ACK_CACHE_CHANGE SN 22
DDS Operation WRITE [TS 23s, Instance 3, Aligned Payload] (ACCEPTED)
SAMPLE MEMORY: 18(I2S16),0(I2S17),36(I3S21),27(I3S23)/9
PAYLOAD MEMORY: 44(I2S16),0(I2S17),33(I3S21),11(I3S23)/22
INSTANCE MEMORY: 0(I2),8(I4),16(I3)/-
RTPS Operation GET_MIN_SN (Expected SN 16)
RTPS Operation GET_MAX_SN (Expected SN 23)
RTPS Operation GET_CACHE_CHANGE SN 21
RTPS Operation GET_CACHE_CHANGE SN 22
RTPS Operation GET_CACHE_CHANGE SN 23
DDS Operation UNREGISTER_INSTANCE [TS 24s, HANDLE_NIL, Instance 1] (REJECTED: Instance not Registered)
DDS Operation WRITE [TS 24s, Instance 1, HANDLE_NIL, Aligned Payload] (ACCEPTED)
SAMPLE MEMORY: 0(I2S17),36(I3S21),27(I3S23),9(I1S24)/18
PAYLOAD MEMORY: 0(I2S17),33(I3S21),11(I3S23),22(I1S24)/44
INSTANCE MEMORY: 8(I1),0(I2),16(I3)/-
DDS Operation WRITE [TS 25s, Instance 4, HANDLE_NIL Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)
RTPS Operation ACK_CACHE_CHANGE SN 21
DDS Operation WRITE [TS 25s, Instance 4, HANDLE_NIL Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)
RTPS Operation ACK_CACHE_CHANGE SN 17
DDS Operation WRITE [TS 25s, Instance 4, HANDLE_NIL, Aligned Payload] (ACCEPTED)
SAMPLE MEMORY: 36(I3S21),27(I3S23),9(I1S24),18(I4S25)/0
PAYLOAD MEMORY: 33(I3S21),11(I3S23),22(I1S24),22(I4S25)/0
INSTANCE MEMORY: 0(I4),8(I1),16(I3)/-
RTPS Operation ACK_CACHE_CHANGE SN 21
DDS Operation WRITE [TS 26s, Instance 2, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)
RTPS Operation ACK_CACHE_CHANGE SN 24
DDS Operation WRITE [TS 26s, Instance 2, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)
DDS Operation UNREGISTER_INSTANCE [TS 26s, Instance 1] (ACCEPTED)
SAMPLE MEMORY: 27(I3S23),9(I1S24),18(I4S25),0(I1S26)/36
PAYLOAD MEMORY: 11(I3S23),22(I1S24),22(I4S25),0(I1S26)/33
INSTANCE MEMORY: 0(I4),8(I1),16(I3)/-
DDS Operation REGISTER_INSTANCE 1 (ACCEPTED)
DDS Operation WRITE [TS 27s, Instance 2, HANDLE_NIL, Aligned Payload] (REJECTED: MAX_INSTANCES exceeded)
DDS Operation UNREGISTER_INSTANCE [TS 27s, Instance 3] (ACCEPTED)
SAMPLE MEMORY: 27(I3S23),18(I4S25),0(I1S26),36(I3S27)/9
PAYLOAD MEMORY: 11(I3S23),22(I4S25),0(I1S26),33(I3S27)/22
INSTANCE MEMORY: 0(I4),8(I1),16(I3)/-
DDS Operation DISPOSE [TS 28s, Instance 3] (ACCEPTED)
SAMPLE MEMORY: 18(I4S25),0(I1S26),36(I3S27),9(I3S28)/27
PAYLOAD MEMORY: 22(I4S25),0(I1S26),33(I3S27),22(I3S28)/11
INSTANCE MEMORY: 0(I4),8(I1),16(I3)/-
RTPS Operation ACK_CACHE_CHANGE SN 27
RTPS Operation ACK_CACHE_CHANGE SN 28
DDS Operation WRITE [TS 29s, Instance 2, HANDLE_NIL, Aligned Payload] (ACCEPTED)
SAMPLE MEMORY: 18(I4S25),0(I1S26),27(I2S29)/36,9
PAYLOAD MEMORY: 22(I4S25),0(I1S26),11(I2S29)/22,33
INSTANCE MEMORY: 16(I2),0(I4),8(I1)/-
RTPS Operation GET_MIN_SN (Expected SN 25)
RTPS Operation GET_MAX_SN (Expected SN 29)
RTPS Operation GET_CACHE_CHANGE SN 25
RTPS Operation GET_CACHE_CHANGE SN 26
RTPS Operation GET_CACHE_CHANGE SN 29
DDS Operation WRITE [TS 30s, Instance 2, Aligned Payload] (ACCEPTED)
SAMPLE MEMORY: 18(I4S25),0(I1S26),27(I2S29),36(I2S30)/9
PAYLOAD MEMORY: 22(I4S25),0(I1S26),11(I2S29),22(I2S30)/33
INSTANCE MEMORY: 16(I2),0(I4),8(I1)/-
RTPS Operation ACK_CACHE_CHANGE SN 25
RTPS Operation ACK_CACHE_CHANGE SN 26
DDS Operation WRITE [TS 31s, Instance 4, Aligned Payload] (ACCEPTED)
SAMPLE MEMORY: 0(I1S26),27(I2S29),36(I2S30),9(I4S31)/18
PAYLOAD MEMORY: 0(I1S26),11(I2S29),22(I2S30),33(I4S31)/22
INSTANCE MEMORY: 16(I2),0(I4),8(I1)/-
RTPS Operation REMOVE_CACHE_CHANGE SN 31
SAMPLE MEMORY: 0(I1S26),27(I2S29),36(I2S30)/18,9
PAYLOAD MEMORY: 0(I1S26),11(I2S29),22(I2S30)/33,22
INSTANCE MEMORY: 16(I2),0(I4),8(I1)/-
RTPS Operation ACK_CACHE_CHANGE SN 29
RTPS Operation ACK_CACHE_CHANGE SN 30
DDS Operation WRITE [TS 32s, Instance 2, Aligned Payload] (ACCEPTED)
SAMPLE MEMORY: 0(I1S26),36(I2S30),18(I2S32)/9,27
PAYLOAD MEMORY: 0(I1S26),22(I2S30),33(I2S32)/11,22
INSTANCE MEMORY: 16(I2),0(I4),8(I1)/-

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-- TEST: GET_MIN_SN/GET_MAX_SN ON EMPTY
-- TEST: GET_MIN_SN/GET_MAX_SN ON 1 SAMPLE
-- TEST: GET_MIN_SN/GET_MAX_SN ON >1 SAMPLE
-- TEST: ADD SAMPLE WITH KEY_HASH [UNKNOWN INSTANCE]
-- TEST: ADD SAMPLE WITH KEY_HASH [KNOWN INSTANCE]
-- TEST: ADD SAMPLE WITH HANDLE_NIL [UNKNOWN INSTANCE]
-- TEST: ADD SAMPLE WITH HANDLE_NIL [KNOWN INSTANCE]
-- TEST: NORMAL WRITE
-- TEST: WRITE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES]
-- TEST: WRITE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES]
-- TEST: WRITE ON DISPOSED INSTANCE
-- TEST: WRITE ON UNREGISTERED INSTANCE
-- TEST: WRITE ALIGNED PAYLOAD
-- TEST: WRITE UNALIGNED PAYLOAD [>1 SLOT]
-- TEST: WRITE UNALIGNED PAYLOAD [<1 SLOT]
-- TEST: NORMAL REGISTER
-- TEST: REGISTER INSTANCE [KNOWN INSTANCE]
-- TEST: REGISTER INSTANCE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCE]
-- TEST: REGISTER INSTANCE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE]
-- TEST: REGISTER ON UNREGISTERED INSTANCE
-- TEST: NORMAL DISPOSE
-- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES]
-- TEST: DISPOSE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES]
-- TEST: DISPOSE ON UNREGISTERED INSTANCE
-- TEST: GET_CACHE_CHANGE [UNKNOWN SN]
-- TEST: GET_CACHE_CHANGE [KNOWN SN, ALIGNED PAYLOAD]
-- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, >1 SLOT]
-- TEST: GET_CACHE_CHANGE [KNOWN SN, UNALIGNED PAYLOAD, <1 SLOT]
-- TEST: NORMAL ACK_CACHE_CHANGE
-- TEST: ACK_CACHE_CHANGE [ALREADY ACKed SN]
-- TEST: NORMAL NACK_CACHE_CHANGE
-- TEST: REMOVE_CACHE_CHANGE [UNKNOWN SN]
-- TEST: REMOVE_CACHE_CHANGE [KNOWN SN]
-- TEST: NORMAL UNREGISTER
-- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITHOUT ACKed SAMPLES]
-- TEST: UNREGISTER INSTANCE ON PAYLOAD MEMORY FULL [WITH ACKed SAMPLES]
-- TEST: UNREGISTER ON DISPOSED INSTANCE
-- TEST: UNREGISTER UNKNOWN INSTANCE
-- TEST: REMOVE STALE INSTANCE WITH 0 SAMPLES
-- TEST: REMOVE STALE INSTANCE WITH 1 SAMPLES
-- TEST: REMOVE STALE INSTANCE WITH >1 SAMPLES
-- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH STALE INSTANCE]
-- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITHOUT STALE INSTANCES]
-- TEST: ADD SAMPLE ON MAX_INSTANCES [UNKNOWN INSTANCE, WITH FULLY ACKed INSTANCE, WITHOUT STALE INSTANCE]
-- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITHOUT ACKed SAMPLES]
-- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES]
-- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed INSTANCE SAMPLE]
-- TEST: ADD SAMPLE ON MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE, WITH ACKed INSTANCE SAMPLES(>1)]
-- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITHOUT ACKed SAMPLES]
-- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLE]
-- TEST: ADD SAMPLE ON MAX_SAMPLES [KNOWN INSTANCE,WITH ACKed SAMPLES (>1)]
-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITHOUT ACKed SAMPLES]
-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITH ACKed SAMPLES, WITHOUT ACKed INSTANCE SAMPLES]
-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_SAMPLES_PER_INSTANCE [KNOWN INSTANCE,WITH ACKed INSTANCE SAMPLES]
-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE, WITHOUT ACKed SAMPLE]
-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITHOUT STALE INSTANCES,WITHOUT ACKed SAMPLES]
-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITHOUT STALE INSTANCE, WITH ACKed SAMPLE]
-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE (>0 SAMPLES)]
-- TEST: ADD SAMPLE ON MAX_SAMPLES & MAX_INSTANCES [UNKNOWN INSTANCE,WITH STALE INSTANCE, WITH ACKed SAMPLE]
-- TEST: ADD SAMPLE ON PAYLOAD FULL & MAX_INSTANCES [UNKNOWN INSTANCE,WITH ACKed SAMPLES,WITH STALE INSTANCE (>= 1 SAMPLE)] (Induce Double Remove)
-- TEST: ADD SAMPLE BIGGER THAN AVAILABLE MEMORY SPACE [WITH ACKed SAMPLES]
-- TEST: INSTANCE LOOKUP [KNOWN INSTANCE]
-- TEST: INSTANCE LOOKUP [UNKNOWN INSTANCE]

11
src/Tests/testbench.pro
View File

@ -18,6 +18,7 @@ analyze ../rtps_builtin_endpoint.vhd
analyze ../rtps_out.vhd
analyze ../rtps_reader.vhd
analyze ../rtps_writer.vhd
analyze ../dds_writer.vhd
analyze Level_0/L0_rtps_handler_test1.vhd
analyze Level_0/L0_rtps_handler_test2.vhd
analyze Level_0/L0_rtps_builtin_endpoint_test1.vhd
@ -53,6 +54,10 @@ analyze Level_1/L1_rtps_writer_test1_vrkdn.vhd
analyze Level_1/L1_rtps_writer_test1_trkdn.vhd
analyze Level_1/L1_rtps_writer_test2_vrkdn.vhd
analyze Level_0/L0_rtps_writer_test2_vrkdp.vhd
analyze Level_0/L0_dds_writer_test1_aik.vhd
analyze Level_0/L0_dds_writer_test1_ain.vhd
analyze Level_0/L0_dds_writer_test1_lik.vhd
analyze Level_0/L0_dds_writer_test1_afk.vhd
#simulate L0_rtps_handler_test1
#simulate L0_rtps_handler_test2
@ -88,4 +93,8 @@ analyze Level_0/L0_rtps_writer_test2_vrkdp.vhd
#simulate L1_rtps_writer_test1_vrkdn
#simulate L1_rtps_writer_test1_trkdn
#simulate L1_rtps_writer_test2_vrkdn
simulate L0_rtps_writer_test2_vrkdp
#simulate L0_rtps_writer_test2_vrkdp
simulate L0_dds_writer_test1_aik
#simulate L0_dds_writer_test1_ain
#simulate L0_dds_writer_test1_lik
#simulate L0_dds_writer_test1_afk

1183
src/dds_writer.vhd
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File diff suppressed because it is too large Load Diff

2
src/rtps_config_package.vhd
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@ -42,7 +42,7 @@ package rtps_config_package is
constant OPCODE_LIVELINESS_UPDATE : std_logic_vector(ENDPOINT_MATCH_OPCODE_WIDTH-1 downto 0) := x"55000003";
type HISTORY_CACHE_OPCODE_TYPE is (NOP, ADD_CACHE_CHANGE, GET_CACHE_CHANGE, ACK_CACHE_CHANGE, NACK_CACHE_CHANGE, REMOVE_CACHE_CHANGE, REMOVE_WRITER, GET_MIN_SN, GET_MAX_SN);
type KEY_HOLDER_TYPE is (NOP, PUSH_DATA, PUSH_SERIALIZED_KEY, READ_KEY_HASH, READ_SERIALIZED_KEY);
type KEY_HOLDER_OPCODE_TYPE is (NOP, PUSH_DATA, PUSH_SERIALIZED_KEY, READ_KEY_HASH, READ_SERIALIZED_KEY);
type KEY_GENERATOR_OPCODE_TYPE is (NOP, WRITE_PAYLOAD, READ_KEY, READ_SIZE);
type HISTORY_CACHE_RESPONSE_TYPE is (OK, REJECTED, INVALID, ERROR);
type DDS_WRITER_OPCODE_TYPE is (NOP, REGISTER_INSTANCE, WRITE, DISPOSE, UNREGISTER_INSTANCE, LOOKUP_INSTANCE, WAIT_FOR_ACKNOWLEDGEMENTS, GET_OFFERED_DEADLINE_MISSED_STATUS, ASSERT_LIVELINESS, GET_LIVELINESS_LOST_STATUS);

1
src/rtps_test_package.vhd
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@ -48,6 +48,7 @@ package rtps_test_package is
subtype TEST_READER_ENDPOINT_MEMORY_FRAME_TYPE_A is TEST_MEMORY_TYPE(0 to READER_ENDPOINT_FRAME_SIZE_A-1);
subtype TEST_READER_ENDPOINT_MEMORY_FRAME_TYPE_B is TEST_MEMORY_TYPE(0 to READER_ENDPOINT_FRAME_SIZE_B-1);
constant LOCATOR_PORT_WIDTH : natural := CDR_LONG_WIDTH;
constant LOCATOR_ADDR_WIDTH : natural := 4*CDR_LONG_WIDTH;