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Remove RTPS_OUT_DATA_TYPE and modify rtps_out with generic

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This commit is contained in:
John Ring 2022-03-19 15:37:20 +01:00
parent ab20cad4d6
commit ad03ae6ecd
26 changed files with 36 additions and 37 deletions
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2
src/TEMPLATE_dds_top.vhd
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@ -106,7 +106,7 @@ architecture arch of dds_top is
signal data_dw_wi, data_wi_dw : WARRAY_DATA_TYPE;
signal status_dw_wi : STATUS_KIND_WARRAY_TYPE;
signal empty_firo_ro, read_ro_firo, last_word_firo_ro : std_logic_vector(0 to NUM_ENDPOINTS);
signal data_firo_ro : RTPS_OUT_DATA_TYPE;
signal data_firo_ro : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS);
-- ###GENERATED START###
-- INTERFACE-USER SIGNALS
-- ###GENERATED END###

2
src/Tests/Level_0/L0_rtps_out_test1.vhd
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@ -40,7 +40,7 @@ architecture testbench of L0_rtps_out_test1 is
signal clk, wr_sig, full : std_logic := '0';
signal reset : std_logic := '1';
signal data_out : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal data_in : RTPS_OUT_DATA_TYPE := (others => (others => '0'));
signal data_in : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS) := (others => (others => '0'));
signal last_word_in, rd_sig, empty : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0');
signal stim_stage : TEST_STAGE_ARRAY_TYPE := (others => IDLE);

2
src/Tests/Level_1/L1_rtps_discovery_module_test1.vhd
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@ -96,7 +96,7 @@ architecture testbench of L1_rtps_discovery_module_test1 is
signal test_time : TIME_TYPE := TIME_ZERO;
signal fifo_in, fifo_out : std_logic_vector(WORD_WIDTH downto 0) := (others => '0');
signal fifo_wr, fifo_empty, fifo_full : std_logic := '0';
signal rtps_out_data : RTPS_OUT_DATA_TYPE := (others => (others => '0'));
signal rtps_out_data : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS) := (others => (others => '0'));
signal rtps_out_rd, rtps_out_last_word_in, rtps_out_empty : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0');
signal alive : std_logic_vector (0 to NUM_ENDPOINTS-1) := (others => '0');

2
src/Tests/Level_1/L1_rtps_reader_test1_trk.vhd
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@ -65,7 +65,7 @@ architecture testbench of L1_rtps_reader_test1_trk is
signal test_time : TIME_TYPE := TIME_ZERO;
signal fifo_in, fifo_out : std_logic_vector(WORD_WIDTH downto 0) := (others => '0');
signal fifo_wr, fifo_empty, fifo_full : std_logic := '0';
signal rtps_out_data : RTPS_OUT_DATA_TYPE := (others => (others => '0'));
signal rtps_out_data : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS) := (others => (others => '0'));
signal rtps_out_rd, rtps_out_last_word_in, rtps_out_empty : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0');
-- *FUNCTION DECLARATION*

2
src/Tests/Level_1/L1_rtps_reader_test1_vrk.vhd
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@ -66,7 +66,7 @@ architecture testbench of L1_rtps_reader_test1_vrk is
signal test_time : TIME_TYPE := TIME_ZERO;
signal fifo_in, fifo_out : std_logic_vector(WORD_WIDTH downto 0) := (others => '0');
signal fifo_wr, fifo_empty, fifo_full : std_logic := '0';
signal rtps_out_data : RTPS_OUT_DATA_TYPE := (others => (others => '0'));
signal rtps_out_data : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS) := (others => (others => '0'));
signal rtps_out_rd, rtps_out_last_word_in, rtps_out_empty : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0');
-- *FUNCTION DECLARATION*

2
src/Tests/Level_1/L1_rtps_writer_test1_tbkdp.vhd
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@ -53,7 +53,7 @@ architecture testbench of L1_rtps_writer_test1_tbkdp is
signal test_time : TIME_TYPE := TIME_ZERO;
signal fifo_in, fifo_out : std_logic_vector(WORD_WIDTH downto 0) := (others => '0');
signal fifo_wr, fifo_empty, fifo_full : std_logic := '0';
signal rtps_out_data : RTPS_OUT_DATA_TYPE := (others => (others => '0'));
signal rtps_out_data : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS) := (others => (others => '0'));
signal rtps_out_rd, rtps_out_last_word_in, rtps_out_empty : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0');
signal test_cc : TEST_CC_ARRAY_TYPE := (others => DEFAULT_CACHE_CHANGE);
-- Signal containing the current fill level of the test_cc array

2
src/Tests/Level_1/L1_rtps_writer_test1_trkdn.vhd
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@ -54,7 +54,7 @@ architecture testbench of L1_rtps_writer_test1_trkdn is
signal test_time : TIME_TYPE := TIME_ZERO;
signal fifo_in, fifo_out : std_logic_vector(WORD_WIDTH downto 0) := (others => '0');
signal fifo_wr, fifo_empty, fifo_full : std_logic := '0';
signal rtps_out_data : RTPS_OUT_DATA_TYPE := (others => (others => '0'));
signal rtps_out_data : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS) := (others => (others => '0'));
signal rtps_out_rd, rtps_out_last_word_in, rtps_out_empty : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0');
signal test_cc : TEST_CC_ARRAY_TYPE := (others => DEFAULT_CACHE_CHANGE);
-- Signal containing the current fill level of the test_cc array

2
src/Tests/Level_1/L1_rtps_writer_test1_trkdp.vhd
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@ -53,7 +53,7 @@ architecture testbench of L1_rtps_writer_test1_trkdp is
signal test_time : TIME_TYPE := TIME_ZERO;
signal fifo_in, fifo_out : std_logic_vector(WORD_WIDTH downto 0) := (others => '0');
signal fifo_wr, fifo_empty, fifo_full : std_logic := '0';
signal rtps_out_data : RTPS_OUT_DATA_TYPE := (others => (others => '0'));
signal rtps_out_data : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS) := (others => (others => '0'));
signal rtps_out_rd, rtps_out_last_word_in, rtps_out_empty : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0');
signal test_cc : TEST_CC_ARRAY_TYPE := (others => DEFAULT_CACHE_CHANGE);
-- Signal containing the current fill level of the test_cc array

2
src/Tests/Level_1/L1_rtps_writer_test1_vbkdp.vhd
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@ -53,7 +53,7 @@ architecture testbench of L1_rtps_writer_test1_vbkdp is
signal test_time : TIME_TYPE := TIME_ZERO;
signal fifo_in, fifo_out : std_logic_vector(WORD_WIDTH downto 0) := (others => '0');
signal fifo_wr, fifo_empty, fifo_full : std_logic := '0';
signal rtps_out_data : RTPS_OUT_DATA_TYPE := (others => (others => '0'));
signal rtps_out_data : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS) := (others => (others => '0'));
signal rtps_out_rd, rtps_out_last_word_in, rtps_out_empty : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0');
signal test_cc : TEST_CC_ARRAY_TYPE := (others => DEFAULT_CACHE_CHANGE);
-- Signal containing the current fill level of the test_cc array

2
src/Tests/Level_1/L1_rtps_writer_test1_vrkdn.vhd
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@ -53,7 +53,7 @@ architecture testbench of L1_rtps_writer_test1_vrkdn is
signal test_time : TIME_TYPE := TIME_ZERO;
signal fifo_in, fifo_out : std_logic_vector(WORD_WIDTH downto 0) := (others => '0');
signal fifo_wr, fifo_empty, fifo_full : std_logic := '0';
signal rtps_out_data : RTPS_OUT_DATA_TYPE := (others => (others => '0'));
signal rtps_out_data : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS) := (others => (others => '0'));
signal rtps_out_rd, rtps_out_last_word_in, rtps_out_empty : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0');
signal test_cc : TEST_CC_ARRAY_TYPE := (others => DEFAULT_CACHE_CHANGE);
-- Signal containing the current fill level of the test_cc array

2
src/Tests/Level_1/L1_rtps_writer_test1_vrkdp.vhd
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@ -53,7 +53,7 @@ architecture testbench of L1_rtps_writer_test1_vrkdp is
signal test_time : TIME_TYPE := TIME_ZERO;
signal fifo_in, fifo_out : std_logic_vector(WORD_WIDTH downto 0) := (others => '0');
signal fifo_wr, fifo_empty, fifo_full : std_logic := '0';
signal rtps_out_data : RTPS_OUT_DATA_TYPE := (others => (others => '0'));
signal rtps_out_data : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS) := (others => (others => '0'));
signal rtps_out_rd, rtps_out_last_word_in, rtps_out_empty : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0');
signal test_cc : TEST_CC_ARRAY_TYPE := (others => DEFAULT_CACHE_CHANGE);
-- Signal containing the current fill level of the test_cc array

2
src/Tests/Level_1/L1_rtps_writer_test1_vrksp.vhd
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@ -53,7 +53,7 @@ architecture testbench of L1_rtps_writer_test1_vrksp is
signal test_time : TIME_TYPE := TIME_ZERO;
signal fifo_in, fifo_out : std_logic_vector(WORD_WIDTH downto 0) := (others => '0');
signal fifo_wr, fifo_empty, fifo_full : std_logic := '0';
signal rtps_out_data : RTPS_OUT_DATA_TYPE := (others => (others => '0'));
signal rtps_out_data : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS) := (others => (others => '0'));
signal rtps_out_rd, rtps_out_last_word_in, rtps_out_empty : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0');
signal test_cc : TEST_CC_ARRAY_TYPE := (others => DEFAULT_CACHE_CHANGE);
-- Signal containing the current fill level of the test_cc array

2
src/Tests/Level_1/L1_rtps_writer_test1_vrndp.vhd
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@ -53,7 +53,7 @@ architecture testbench of L1_rtps_writer_test1_vrndp is
signal test_time : TIME_TYPE := TIME_ZERO;
signal fifo_in, fifo_out : std_logic_vector(WORD_WIDTH downto 0) := (others => '0');
signal fifo_wr, fifo_empty, fifo_full : std_logic := '0';
signal rtps_out_data : RTPS_OUT_DATA_TYPE := (others => (others => '0'));
signal rtps_out_data : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS) := (others => (others => '0'));
signal rtps_out_rd, rtps_out_last_word_in, rtps_out_empty : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0');
signal test_cc : TEST_CC_ARRAY_TYPE := (others => DEFAULT_CACHE_CHANGE);
-- Signal containing the current fill level of the test_cc array

2
src/Tests/Level_1/L1_rtps_writer_test2_vrkdn.vhd
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@ -52,7 +52,7 @@ architecture testbench of L1_rtps_writer_test2_vrkdn is
signal test_time : TIME_TYPE := TIME_ZERO;
signal fifo_in, fifo_out : std_logic_vector(WORD_WIDTH downto 0) := (others => '0');
signal fifo_wr, fifo_empty, fifo_full : std_logic := '0';
signal rtps_out_data : RTPS_OUT_DATA_TYPE := (others => (others => '0'));
signal rtps_out_data : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS) := (others => (others => '0'));
signal rtps_out_rd, rtps_out_last_word_in, rtps_out_empty : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0');
signal test_cc : TEST_CC_ARRAY_TYPE := (others => DEFAULT_CACHE_CHANGE);
-- Signal containing the current fill level of the test_cc array

2
src/Tests/Level_1/L1_rtps_writer_test2_vrksn.vhd
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@ -52,7 +52,7 @@ architecture testbench of L1_rtps_writer_test2_vrksn is
signal test_time : TIME_TYPE := TIME_ZERO;
signal fifo_in, fifo_out : std_logic_vector(WORD_WIDTH downto 0) := (others => '0');
signal fifo_wr, fifo_empty, fifo_full : std_logic := '0';
signal rtps_out_data : RTPS_OUT_DATA_TYPE := (others => (others => '0'));
signal rtps_out_data : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS) := (others => (others => '0'));
signal rtps_out_rd, rtps_out_last_word_in, rtps_out_empty : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0');
signal test_cc : TEST_CC_ARRAY_TYPE := (others => DEFAULT_CACHE_CHANGE);
-- Signal containing the current fill level of the test_cc array

2
src/Tests/Level_1/L1_rtps_writer_test3_vrkdn.vhd
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@ -54,7 +54,7 @@ architecture testbench of L1_rtps_writer_test3_vrkdn is
signal test_time : TIME_TYPE := TIME_ZERO;
signal fifo_in, fifo_out : std_logic_vector(WORD_WIDTH downto 0) := (others => '0');
signal fifo_wr, fifo_empty, fifo_full : std_logic := '0';
signal rtps_out_data : RTPS_OUT_DATA_TYPE := (others => (others => '0'));
signal rtps_out_data : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS) := (others => (others => '0'));
signal rtps_out_rd, rtps_out_last_word_in, rtps_out_empty : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0');
signal test_cc : TEST_CC_ARRAY_TYPE := (others => DEFAULT_CACHE_CHANGE);
-- Signal containing the current fill level of the test_cc array

2
src/Tests/Level_2/L2_Testbench_Lib2.vhd
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@ -80,7 +80,7 @@ architecture arch of L2_Testbench_Lib2 is
signal data_out_rbe : std_logic_vector(WORD_WIDTH-1 downto 0);
signal last_word_out_rh_be_s, last_word_out_rh_ue_s : std_logic;
signal data_out_rh_be_s, data_out_rh_ue_s : std_logic_vector(WORD_WIDTH-1 downto 0);
signal data_rtps_out_s : RTPS_OUT_DATA_TYPE;
signal data_rtps_out_s : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS);
signal last_word_rtps_out_s : std_logic_vector(0 to NUM_ENDPOINTS);
begin

2
src/Tests/Level_2/L2_Testbench_Lib3.vhd
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@ -89,7 +89,7 @@ architecture arch of L2_Testbench_Lib3 is
signal data_out_rbe : std_logic_vector(WORD_WIDTH-1 downto 0);
signal last_word_out_rh_be_s, last_word_out_rh_ue_s : std_logic;
signal data_out_rh_be_s, data_out_rh_ue_s : std_logic_vector(WORD_WIDTH-1 downto 0);
signal data_rtps_out_s : RTPS_OUT_DATA_TYPE;
signal data_rtps_out_s : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS);
signal last_word_rtps_out_s : std_logic_vector(0 to NUM_ENDPOINTS);

2
src/Tests/Level_2/L2_testbench_Lib4.vhd
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@ -101,7 +101,7 @@ architecture arch of L2_Testbench_Lib4 is
signal data_dw_wi, data_wi_dw : WARRAY_DATA_TYPE;
signal status_dw_wi : STATUS_KIND_WARRAY_TYPE;
signal empty_firo_ro, read_ro_firo, last_word_firo_ro : std_logic_vector(0 to NUM_ENDPOINTS);
signal data_firo_ro : RTPS_OUT_DATA_TYPE;
signal data_firo_ro : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS);
signal sample_info_ri_user : SAMPLE_INFO_TYPE;
signal start_user_ri, ack_ri_user, get_data_user_ri, done_ri_user, sample_info_valid_ri_user, sample_info_ack_user_ri, eoc_ri_user, decode_error_ri_user, valid_ri_user : std_logic;
signal opcode_user_ri : DDS_READER_OPCODE_TYPE;

2
src/Tests/Level_2/L2_testbench_Lib5.vhd
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@ -137,7 +137,7 @@ architecture arch of L2_Testbench_Lib5 is
signal data_dw_wi, data_wi_dw : WARRAY_DATA_TYPE;
signal status_dw_wi : STATUS_KIND_WARRAY_TYPE;
signal empty_firo_ro, read_ro_firo, last_word_firo_ro : std_logic_vector(0 to NUM_ENDPOINTS);
signal data_firo_ro : RTPS_OUT_DATA_TYPE;
signal data_firo_ro : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS);
begin

2
src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib2.vhd
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@ -101,7 +101,7 @@ architecture arch of L2_Testbench_ROS_Lib2 is
signal data_dw_wi, data_wi_dw : WARRAY_DATA_TYPE;
signal status_dw_wi : STATUS_KIND_WARRAY_TYPE;
signal empty_firo_ro, read_ro_firo, last_word_firo_ro : std_logic_vector(0 to NUM_ENDPOINTS);
signal data_firo_ro : RTPS_OUT_DATA_TYPE;
signal data_firo_ro : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS);
signal service_if : SERVICE_INTERFACE_ARRAY_TYPE(0 to NUM_SERVICES-1);
-- ###GENERATED START###

2
src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib3.vhd
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@ -118,7 +118,7 @@ architecture arch of L2_Testbench_ROS_Lib3 is
signal data_dw_wi, data_wi_dw : WARRAY_DATA_TYPE;
signal status_dw_wi : STATUS_KIND_WARRAY_TYPE;
signal empty_firo_ro, read_ro_firo, last_word_firo_ro : std_logic_vector(0 to NUM_ENDPOINTS);
signal data_firo_ro : RTPS_OUT_DATA_TYPE;
signal data_firo_ro : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS);
signal service_if : SERVICE_INTERFACE_ARRAY_TYPE(0 to NUM_SERVICES-1);
-- ###GENERATED START###
-- INTERFACE-USER SIGNALS

2
src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib4.vhd
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@ -103,7 +103,7 @@ architecture arch of L2_Testbench_ROS_Lib4 is
signal data_dw_wi, data_wi_dw : WARRAY_DATA_TYPE;
signal status_dw_wi : STATUS_KIND_WARRAY_TYPE;
signal empty_firo_ro, read_ro_firo, last_word_firo_ro : std_logic_vector(0 to NUM_ENDPOINTS);
signal data_firo_ro : RTPS_OUT_DATA_TYPE;
signal data_firo_ro : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS);
signal action_if : ACTION_INTERFACE_ARRAY_TYPE(0 to NUM_ACTIONS-1);
-- ###GENERATED START###
signal start_s, ack_s, done_s : std_logic;

2
src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib5.vhd
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@ -149,7 +149,7 @@ architecture arch of L2_Testbench_ROS_Lib5 is
signal data_dw_wi, data_wi_dw : WARRAY_DATA_TYPE;
signal status_dw_wi : STATUS_KIND_WARRAY_TYPE;
signal empty_firo_ro, read_ro_firo, last_word_firo_ro : std_logic_vector(0 to NUM_ENDPOINTS);
signal data_firo_ro : RTPS_OUT_DATA_TYPE;
signal data_firo_ro : WORD_ARRAY_TYPE(0 to NUM_ENDPOINTS);
signal action_if : ACTION_INTERFACE_ARRAY_TYPE(0 to NUM_ACTIONS-1);
begin

2
src/rtps_config_package.vhd
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@ -121,8 +121,6 @@ package rtps_config_package is
constant READER_DEFAULT_QOS_MATCH : DEFAULT_QOS_MATCH_TYPE; -- Deferred to Package Body
constant WRITER_DEFAULT_QOS_MATCH : DEFAULT_QOS_MATCH_TYPE; -- Deferred to Package Body
type RTPS_OUT_DATA_TYPE is array (0 to NUM_ENDPOINTS) of std_logic_vector(WORD_WIDTH-1 downto 0);
constant CLOCK_DURATION : DURATION_TYPE := gen_duration(CLOCK_PERIOD);
-- Swap "data" to Big Endian representation.

23
src/rtps_out.vhd
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@ -12,6 +12,7 @@ use work.rtps_config_package.all;
entity rtps_out is
generic (
RTPS_OUT_WIDTH : natural := NUM_ENDPOINTS+1;
-- Max Serialized Payload Size in a UDP Stream (Bytes) [MAX_PAYLOAD(65536) - IPv4_HEADER(20) - UDP_HEADER(8) + FORMAT_HEADER(16)]
MAX_BUFFER_SIZE : natural := 65524/(WORD_WIDTH/BYTE_WIDTH)
);
@ -20,10 +21,10 @@ entity rtps_out is
clk : in std_logic;
reset : in std_logic;
-- INPUT
empty : in std_logic_vector(0 to NUM_ENDPOINTS);
rd : out std_logic_vector(0 to NUM_ENDPOINTS);
data_in : in RTPS_OUT_DATA_TYPE;
last_word_in: in std_logic_vector(0 to NUM_ENDPOINTS);
empty : in std_logic_vector(0 to RTPS_OUT_WIDTH-1);
rd : out std_logic_vector(0 to RTPS_OUT_WIDTH-1);
data_in : in WORD_ARRAY_TYPE(0 to RTPS_OUT_WIDTH-1);
last_word_in: in std_logic_vector(0 to RTPS_OUT_WIDTH-1);
-- OUTPUT
full : in std_logic;
wr : out std_logic;
@ -42,7 +43,7 @@ architecture arch of rtps_out is
type OUTPUT_STAGE_TYPE is (IDLE, SRC_ADDR_HEADER, DEST_ADDR_HEADER, PORT_HEADER, PACKET_LENGTH, WRITE_PRIMER, WRITE, FINALIZE_WRITE);
-- *SIGNAL DECLARATION*
signal selector, selector_next : natural range 0 to NUM_ENDPOINTS;
signal selector, selector_next : natural range 0 to RTPS_OUT_WIDTH-1;
signal buff, buff_next : BUFFER_TYPE;
signal in_pntr, in_pntr_next : unsigned(BUFFER_ADDR_WIDTH downto 0);
signal out_pntr, out_pntr_next : unsigned(BUFFER_ADDR_WIDTH downto 0);
@ -107,7 +108,7 @@ begin
-- Currently Selected Input FIFO is empty
if (empty(selector) = '1') then
-- Wrap from End to BEgining (Circular selection)
if (selector = NUM_ENDPOINTS) then
if (selector = RTPS_OUT_WIDTH-1) then
selector_next <= 0;
else
-- Select next input FIFO
@ -134,7 +135,7 @@ begin
input_stage_next <= IDLE;
in_pntr_next <= to_unsigned(MAX_BUFFER_SIZE, in_pntr'length);
-- Select next input FIFO (Prevent lifelock)
if (selector = NUM_ENDPOINTS) then
if (selector = RTPS_OUT_WIDTH-1) then
selector_next <= 0;
else
selector_next <= selector + 1;
@ -154,7 +155,7 @@ begin
input_stage_next <= IDLE;
in_pntr_next <= to_unsigned(MAX_BUFFER_SIZE, in_pntr'length);
-- Select next input FIFO (Prevent lifelock)
if (selector = NUM_ENDPOINTS) then
if (selector = RTPS_OUT_WIDTH-1) then
selector_next <= 0;
else
selector_next <= selector + 1;
@ -174,7 +175,7 @@ begin
input_stage_next <= IDLE;
in_pntr_next <= to_unsigned(MAX_BUFFER_SIZE, in_pntr'length);
-- Select next input FIFO (Prevent lifelock)
if (selector = NUM_ENDPOINTS) then
if (selector = RTPS_OUT_WIDTH-1) then
selector_next <= 0;
else
selector_next <= selector + 1;
@ -204,7 +205,7 @@ begin
input_stage_next <= IDLE;
in_pntr_next <= to_unsigned(MAX_BUFFER_SIZE, in_pntr'length);
-- Select next input FIFO (Prevent lifelock)
if (selector = NUM_ENDPOINTS) then
if (selector = RTPS_OUT_WIDTH-1) then
selector_next <= 0;
else
selector_next <= selector + 1;
@ -228,7 +229,7 @@ begin
input_stage_next <= IDLE;
in_pntr_next <= to_unsigned(MAX_BUFFER_SIZE, in_pntr'length);
-- Select next input FIFO (Prevent lifelock)
if (selector = NUM_ENDPOINTS) then
if (selector = RTPS_OUT_WIDTH-1) then
selector_next <= 0;
else
selector_next <= selector + 1;