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Change decoding convention

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In muti-word decoding do not call the "FETCH" stage in the
last-to-second sub-stage.
This commit is contained in:
John Ring 2022-02-04 19:47:47 +01:00
parent 158ab05a4d
commit c9d4b55d4a
8 changed files with 30 additions and 25 deletions
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19
src/IDL-VHDL_Ref.txt
View File

@ -40,18 +40,21 @@ The generated decode_stage first checks the alignement and aligns the stream usi
member is taken, and the 'FETCH' stage is called.
* Primitive size 8
The decode_stage is divided with the help of 'cnt' in 3 sub-stages. A helper double-word latch 'dw_latch'
is used. The first 2 sub-stages latch the word into the helper latch (calling 'FETCH' stage each time),
and the last sub-stage is for latching the final signal in it's final place. In the last sub-stage 8 is
added to the 'align_offset' and the decode_stage of the next declared member is taken.
is used. The first 2 sub-stages latch the word into the helper latch, and the last sub-stage is for
latching the final signal in it's final place. The "FETCH" stage is called in the first and last
sub-stages. In the last sub-stage 8 is added to the 'align_offset' and the decode_stage of the next
declared member is taken.
NOTE: The extra sub-stage is used to push the signal to a memory in a single operation
NOTE: If there is no next declared member, the second-to-last stage should NOT call the "FETCH" stage
* Primitive size 16
The decode_stage is divided with the help of 'cnt' in 5 sub-stages. A helper quad-word latch 'qw_latch'
is used. The first 4 sub-stages latch the word into the helper latch (calling 'FETCH' stage each time),
and the last sub-stage is for latching the final signal in it's final place. In the last sub-stage 16 is
added to the 'align_offset' and the decode_stage of the next declared member is taken.
is used. The first 4 sub-stages latch the word into the helper latch, and the last sub-stage is for
latching the final signal in it's final place. The "FETCH" stage is called in all except the
second-to-last sub-stage. In the last sub-stage 16 is added to the 'align_offset' and the decode_stage
of the next declared member is taken.
NOTE: The extra sub-stage is used to push the signal to a memory in a single operation
NOTE: If there is no next declared member, the second-to-last stage should NOT call the "FETCH" stage
NOTE: If there is no next declared member, the last sub-stage should not call the "FETCH" stage.
(Should be overriden by "SKIP_PAYLOAD")
The alignements and sizes for IDL primitive types are following:

6
src/Tests/Type2_key_holder.vhd
View File

@ -433,10 +433,10 @@ begin
cnt_next <= cnt + 1;
-- Double Word 2/2
when 1 =>
stage_next <= FETCH;
cnt_next <= cnt + 1;
-- Push Double Word
when 2 =>
when 2 =>
stage_next <= FETCH;
align_offset_next <= align_offset + 8;
decode_stage_next <= GET_OPTIONAL_HEADER;
return_stage_next <= GET_TESTSEQUENCE_TESTLONGDOUBLE;
@ -477,10 +477,10 @@ begin
cnt_next <= cnt + 1;
-- Quad Word 4/4
when 3 =>
stage_next <= FETCH;
cnt_next <= cnt + 1;
-- Push Quad Word
when 4 =>
stage_next <= FETCH;
align_offset_next <= align_offset + 16;
-- All Elements processed

4
src/Tests/Type2_reader_interface.vhd
View File

@ -780,7 +780,6 @@ begin
-- Double Word 2/2
when 1 =>
dw_latch_next <= write_sub_vector(dw_latch_next, data_in_latch, 1, TRUE);
stage_next <= FETCH;
cnt_next <= cnt + 1;
-- Push Double Word
when 2 =>
@ -791,6 +790,7 @@ begin
-- Memory Operation Guard
if (TestSequence_TestLongLong_mem_ready_in = '1') then
align_offset_next <= align_offset + 8;
stage_next <= FETCH;
decode_stage_next <= GET_OPTIONAL_HEADER;
return_stage_next <= GET_TESTSEQUENCE_TESTLONGDOUBLE;
cnt_next <= 0;
@ -842,7 +842,6 @@ begin
-- Quad Word 4/4
when 3 =>
qw_latch_next <= write_sub_vector(qw_latch_next, data_in_latch, 3, TRUE);
stage_next <= FETCH;
cnt_next <= cnt + 1;
-- Push Quad Word
when 4 =>
@ -852,6 +851,7 @@ begin
-- Memory Operation Guard
if (TestSequence_TestLongLong_mem_ready_in = '1') then
stage_next <= FETCH;
align_offset_next <= align_offset + 16;
-- All Elements processed

6
src/ros2/TEMPLATE_ros_srv_client.vhd
View File

@ -365,12 +365,12 @@ begin
-- Double Word 2/2
when 1 =>
dw_latch_next((CDR_LONG_LONG_WIDTH/2)-1 downto 0) <= data_in_latch;
stage_next <= FETCH;
cnt_next <= cnt + 1;
-- Push Double Word
when 2 =>
service_info_sig_next.request_id.writer_guid(0) <= get_sub_vector(endian_swap(endian_flag, dw_latch),0,WORD_WIDTH,TRUE);
service_info_sig_next.request_id.writer_guid(1) <= get_sub_vector(endian_swap(endian_flag, dw_latch),1,WORD_WIDTH,TRUE);
stage_next <= FETCH;
align_offset_next <= align_offset + 8;
decode_stage_next <= GET_RID_SN;
cnt_next <= 0;
@ -393,14 +393,14 @@ begin
-- Double Word 2/2
when 1 =>
dw_latch_next((CDR_LONG_LONG_WIDTH/2)-1 downto 0) <= data_in_latch;
stage_next <= FETCH;
cnt_next <= cnt + 1;
-- Push Double Word
when 2 =>
service_info_sig_next.request_id.sequence_number <= to_double_word(unsigned(endian_swap(endian_flag, dw_latch)));
stage_next <= FETCH;
align_offset_next <= align_offset + 8;
-- ###GENERATED START###
stage_next <= TODO;
decode_stage_next <= TODO;
-- ###GENERATED END###
when others =>
null;

6
src/ros2/TEMPLATE_ros_srv_server.vhd
View File

@ -360,12 +360,12 @@ begin
-- Double Word 2/2
when 1 =>
dw_latch_next((CDR_LONG_LONG_WIDTH/2)-1 downto 0) <= data_in_latch;
stage_next <= FETCH;
cnt_next <= cnt + 1;
-- Push Double Word
when 2 =>
service_info_sig_next.request_id.writer_guid(0) <= get_sub_vector(endian_swap(endian_flag, dw_latch),0,WORD_WIDTH,TRUE);
service_info_sig_next.request_id.writer_guid(1) <= get_sub_vector(endian_swap(endian_flag, dw_latch),1,WORD_WIDTH,TRUE);
stage_next <= FETCH;
align_offset_next <= align_offset + 8;
decode_stage_next <= GET_RID_SN;
cnt_next <= 0;
@ -388,14 +388,14 @@ begin
-- Double Word 2/2
when 1 =>
dw_latch_next((CDR_LONG_LONG_WIDTH/2)-1 downto 0) <= data_in_latch;
stage_next <= FETCH;
cnt_next <= cnt + 1;
-- Push Double Word
when 2 =>
service_info_sig_next.request_id.sequence_number <= to_double_word(unsigned(endian_swap(endian_flag, dw_latch)));
stage_next <= FETCH;
align_offset_next <= align_offset + 8;
-- ###GENERATED START###
stage_next <= TODO;
decode_stage_next <= TODO;
-- ###GENERATED END###
when others =>
null;

5
src/ros2/example_interfaces/AddTwoInts_ros_srv_client.vhd
View File

@ -362,12 +362,12 @@ begin
-- Double Word 2/2
when 1 =>
dw_latch_next((CDR_LONG_LONG_WIDTH/2)-1 downto 0) <= data_in_latch;
stage_next <= FETCH;
cnt_next <= cnt + 1;
-- Push Double Word
when 2 =>
service_info_sig_next.request_id.writer_guid(0) <= get_sub_vector(endian_swap(endian_flag, dw_latch),0,WORD_WIDTH,TRUE);
service_info_sig_next.request_id.writer_guid(1) <= get_sub_vector(endian_swap(endian_flag, dw_latch),1,WORD_WIDTH,TRUE);
stage_next <= FETCH;
align_offset_next <= align_offset + 8;
decode_stage_next <= GET_RID_SN;
cnt_next <= 0;
@ -390,11 +390,11 @@ begin
-- Double Word 2/2
when 1 =>
dw_latch_next((CDR_LONG_LONG_WIDTH/2)-1 downto 0) <= data_in_latch;
stage_next <= FETCH;
cnt_next <= cnt + 1;
-- Push Double Word
when 2 =>
service_info_sig_next.request_id.sequence_number <= to_double_word(unsigned(endian_swap(endian_flag, dw_latch)));
stage_next <= FETCH;
align_offset_next <= align_offset + 8;
-- ###GENERATED START###
decode_stage_next <= GET_RR_SUM;
@ -424,6 +424,7 @@ begin
-- Push Double Word
when 2 =>
sum_latch_next <= endian_swap(endian_flag, dw_latch);
stage_next <= FETCH;
align_offset_next <= align_offset + 8;
-- DONE

7
src/ros2/example_interfaces/AddTwoInts_ros_srv_server.vhd
View File

@ -360,12 +360,12 @@ begin
-- Double Word 2/2
when 1 =>
dw_latch_next((CDR_LONG_LONG_WIDTH/2)-1 downto 0) <= data_in_latch;
stage_next <= FETCH;
cnt_next <= cnt + 1;
-- Push Double Word
when 2 =>
service_info_sig_next.request_id.writer_guid(0) <= get_sub_vector(endian_swap(endian_flag, dw_latch),0,WORD_WIDTH,TRUE);
service_info_sig_next.request_id.writer_guid(1) <= get_sub_vector(endian_swap(endian_flag, dw_latch),1,WORD_WIDTH,TRUE);
stage_next <= FETCH;
align_offset_next <= align_offset + 8;
decode_stage_next <= GET_RID_SN;
cnt_next <= 0;
@ -388,11 +388,11 @@ begin
-- Double Word 2/2
when 1 =>
dw_latch_next((CDR_LONG_LONG_WIDTH/2)-1 downto 0) <= data_in_latch;
stage_next <= FETCH;
cnt_next <= cnt + 1;
-- Push Double Word
when 2 =>
service_info_sig_next.request_id.sequence_number <= to_double_word(unsigned(endian_swap(endian_flag, dw_latch)));
stage_next <= FETCH;
align_offset_next <= align_offset + 8;
-- ###GENERATED START###
decode_stage_next <= GET_RQ_A;
@ -418,11 +418,11 @@ begin
-- Double Word 2/2
when 1 =>
dw_latch_next((CDR_LONG_LONG_WIDTH/2)-1 downto 0) <= data_in_latch;
stage_next <= FETCH;
cnt_next <= cnt + 1;
-- Push Double Word
when 2 =>
a_latch_next <= endian_swap(endian_flag, dw_latch);
stage_next <= FETCH;
align_offset_next <= align_offset + 8;
decode_stage_next <= GET_RQ_B;
cnt_next <= 0;
@ -449,6 +449,7 @@ begin
-- Push Double Word
when 2 =>
b_latch_next <= endian_swap(endian_flag, dw_latch);
stage_next <= FETCH;
align_offset_next <= align_offset + 8;
-- DONE

2
src/ros2/rcl_interfaces/action_msgs/GoalStatusArray_ros_sub.vhd
View File

@ -489,7 +489,6 @@ begin
-- Double Word 2/2
when 1 =>
dw_latch_next <= write_sub_vector(dw_latch_next, endian_swap(endian_flag, data_in_latch), 1, TRUE);
stage_next <= FETCH;
cnt_next <= cnt + 1;
-- Push Double Word
when 2 =>
@ -499,6 +498,7 @@ begin
-- Memory Operation Guard
if (status_list_goal_info_stamp_mem_ready_in = '1') then
stage_next <= FETCH;
align_offset_next <= align_offset + 8;
decode_stage_next <= GET_STATUS_LIST_STATUS;
end if;