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Add documentation to RTPS Reader, Best Efoort RELIABILITY uses less memory

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RELIABILITY_QOS is checked, allowing BEST EFFORT to use less
memory.
This commit is contained in:
Greek 2021-01-29 17:57:06 +01:00
parent d54bf55b46
commit d4795c1838
1 changed files with 590 additions and 410 deletions
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404
src/rtps_endpoint.vhd → src/rtps_reader.vhd
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@ -14,8 +14,9 @@ use work.rtps_config_package.all;
-- TODO: Is mem_addr_base needed? Isn't it a direct mirror of addr_mem_base? mem_addr_base is only used in the same clock cycle as mem_op_done is pulled high. -- TODO: Is mem_addr_base needed? Isn't it a direct mirror of addr_mem_base? mem_addr_base is only used in the same clock cycle as mem_op_done is pulled high.
entity rtps_endpoint is entity rtps_reader is
generic ( generic (
RELIABILTY_QOS : std_logic_vector(CDR_ENUMERATION_WIDTH-1 downto 0) := DEFAULT_RELIABILTY_QOS;
HEARTBEAT_RESPONSE_DELAY : DURATION_TYPE := TODO; HEARTBEAT_RESPONSE_DELAY : DURATION_TYPE := TODO;
HEARTBEAT_SUPPRESSION_DELAY : DURATION_TYPE := TODO; HEARTBEAT_SUPPRESSION_DELAY : DURATION_TYPE := TODO;
LEASE_DURATION : DURATION_TYPE := DEFAULT_LEASE_DURATION; LEASE_DURATION : DURATION_TYPE := DEFAULT_LEASE_DURATION;
@ -51,7 +52,7 @@ entity rtps_endpoint is
); );
end entity; end entity;
architecture arch of rtps_endpoint is architecture arch of rtps_reader is
--*****CONSTANT DECLARATION***** --*****CONSTANT DECLARATION*****
-- *ENDPOINT MEMORY* -- *ENDPOINT MEMORY*
@ -83,18 +84,32 @@ architecture arch of rtps_endpoint is
constant EMF_GUIDPREFIX_OFFSET : natural := 1; constant EMF_GUIDPREFIX_OFFSET : natural := 1;
constant EMF_IPV4_ADDR_OFFSET : natural := 4; constant EMF_IPV4_ADDR_OFFSET : natural := 4;
constant EMF_UDP_PORT_OFFSET : natural := 5; constant EMF_UDP_PORT_OFFSET : natural := 5;
constant EMF_NEXT_SEQ_NR_OFFSET : natural := 6; constant EMF_NEXT_SEQ_NR_OFFSET : natural := 6 when (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) else EMF_GUIDPREFIX_OFFSET + 3;
constant EMF_LEASE_DEADLINE_OFFSET : natural := 8; constant EMF_LEASE_DEADLINE_OFFSET : natural := EMF_NEXT_SEQ_NR_OFFSET + 2;
constant EMF_RES_TIME_OFFSET : natural := 10; constant EMF_RES_TIME_OFFSET : natural := EMF_LEASE_DEADLINE_OFFSET + 2;
--*****TYPE DECLARATION***** --*****TYPE DECLARATION*****
-- FSM states. Explained below in detail -- FSM states. Explained below in detail
type STAGE_TYPE is (IDLE, TODO); type STAGE_TYPE is (IDLE, LATCH_GUIDPREFIX, LATCH_ENTITYID, INITIATE_ENDPOINT_SEARCH, LATCH_ENDPOINT_DATA, METATRAFFIC_OPERATION, LATCH_SRC_ADDR,
-- Memory FSM Opcodes LATCH_EXTRA_DATA, LATCH_HEARTBEAT, PROCESS_HEARTBEAT, LATCH_GAP, PROCESS_GAP, FIND_NEXT_VALID_IN_BITMAP, PROCESS_INLINE_QOS, LATCH_LIFESPAN,
type MEM_OPCODE_TYPE is (NOP, TODO); LATCH_KEY_HASH, LATCH_STATUS_INFO, INITIATE_ADD_CACHE_CHANGE_REQUEST, ADD_CACHE_CHANGE, PUSH_PAYLOAD, FINALIZE_ADD_CACHE_CHANGE_REQUEST,
type MEM_STAGE_TYPE is (IDLE, TODO); ENDPOINT_STALE_CHECK, SEND_HEADER, SEND_ACKNACK, SKIP_PARAMETER, SKIP_PACKET);
-- Record of all Participant Data stored in memory -- Memory FSM states. Explaine below in detail
type MEM_STAGE_TYPE is (IDLE, SEARCH_ENDPOINT, GET_ENDPOINT_DATA, INSERT_ENDPOINT, UPDATE_ENDPOINT, REMOVE_ENDPOINT, FIND_EMPTY_SLOT,
RESET_MAX_POINTER, GET_NEXT_ENDPOINT);
-- *Memory FSM Opcodes*
-- OPCODE DESCRIPTION
-- SEARCH_ENDPOINT Find Endpoint with specified GUID in memory
-- INSERT_ENDPOINT Insert Endpoint to first available empty slot in memory
-- UPDATE_ENDPOINT Update Endpoint pointed by mem_addr_base. (mem_field_flags specifies which Fields to update)
-- REMOVE_ENDPOINT Remove Endpoint pointed by mem_addr_base
-- GET_FIRST_ENDPOINT Get Endpoint Data of first Endpoint stored in Memory. (mem_field_flags specifies which Fields to get)
-- GET_NEXT_ENDPOINT Get Endpoint Data of next Endpoint (from the Endpoint pointed by mem_addr_base) stored in Memory. (mem_field_flags specifies which Fields to get)
-- GET_ENDPOINT Get Endpoint Data from Endpoint currently pointed by mem_addr_base. (mem_field_flags specifies which Fields to get)
type MEM_OPCODE_TYPE is (NOP, SEARCH_ENDPOINT, INSERT_ENDPOINT, UPDATE_ENDPOINT, REMOVE_ENDPOINT, GET_FIRST_ENDPOINT, GET_NEXT_ENDPOINT,
GET_ENDPOINT);
-- Record of Endpoint Data
type ENDPOINT_DATA_TYPE is record type ENDPOINT_DATA_TYPE is record
guid : GUID_TYPE; guid : GUID_TYPE;
addr : std_logic_vector(IPv4_ADDRESS_WIDTH-1 downto 0); addr : std_logic_vector(IPv4_ADDRESS_WIDTH-1 downto 0);
@ -103,6 +118,7 @@ architecture arch of rtps_endpoint is
lease_deadline : TIME_TYPE; lease_deadline : TIME_TYPE;
res_time : TIME_TYPE; res_time : TIME_TYPE;
end record; end record;
-- Zero initialized Endpoint Data
constant ZERO_ENDPOINT_DATA : ENDPOINT_DATA_TYPE := ( constant ZERO_ENDPOINT_DATA : ENDPOINT_DATA_TYPE := (
guid => GUID_UNKNOWN, guid => GUID_UNKNOWN,
addr => IPv4_ADDRESS_INVALID, addr => IPv4_ADDRESS_INVALID,
@ -111,6 +127,7 @@ architecture arch of rtps_endpoint is
lease_deadline => TIME_INVALID, lease_deadline => TIME_INVALID,
res_time => TIME_INVALID res_time => TIME_INVALID
); );
-- Endpoint Data Latch used as temporal cache by Memory Process
type ENDPOINT_LATCH_DATA_TYPE is record type ENDPOINT_LATCH_DATA_TYPE is record
guid : GUID_TYPE; guid : GUID_TYPE;
addr : std_logic_vector(IPv4_ADDRESS_WIDTH-1 downto 0); addr : std_logic_vector(IPv4_ADDRESS_WIDTH-1 downto 0);
@ -119,6 +136,7 @@ architecture arch of rtps_endpoint is
next_seq_nr : SEQUENCENUMBER_TYPE; next_seq_nr : SEQUENCENUMBER_TYPE;
field_flag : std_logic_vector(0 to EMF_FLAG_WIDTH-1); field_flag : std_logic_vector(0 to EMF_FLAG_WIDTH-1);
end record; end record;
-- Zero initialized Endpoint Data Latch
constant ZERO_ENDPOINT_LATCH_DATA : ENDPOINT_LATCH_DATA_TYPE := ( constant ZERO_ENDPOINT_LATCH_DATA : ENDPOINT_LATCH_DATA_TYPE := (
guid => GUID_UNKNOWN, guid => GUID_UNKNOWN,
addr => IPv4_ADDRESS_INVALID, addr => IPv4_ADDRESS_INVALID,
@ -130,69 +148,111 @@ architecture arch of rtps_endpoint is
--*****SIGNAL DECLARATION***** --*****SIGNAL DECLARATION*****
-- *MAIN PROCESS*
-- FSM state -- FSM state
signal stage, stage_next : STAGE_TYPE := IDLE; signal stage, stage_next : STAGE_TYPE := IDLE;
signal meta_opcode, meta_opcode_next : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); -- FSM state latch. Used to transition dynamically to different states from the same state.
signal cnt, cnt_next : natural range TODO := 0; signal return_stage, return_stage_next : STAGE_TYPE := IDLE;
signal guid, guid_next : GUID_TYPE := (others => (others => '0'));
signal mem_op_done : std_logic := '0';
signal mem_opcode : MEM_OPCODE_TYPE := NOP;
signal mem_op_start : std_logic := '0';
signal addr, addr_next : std_logic_vector(IPv4_ADDRESS_WIDTH-1 downto 0) := (others => '0');
signal portn, portn_next : std_logic_vector(UDP_PORT_WIDTH-1 downto 0) := (others => '0');
signal expects_inline_qos, expects_inline_qos_next : std_logic := '0';
signal is_meta, is_meta_next : std_logic := '0';
signal mem_field_flags : std_logic_vector(0 to EMF_FLAG_WIDTH-1) := (others => '0');
signal opcode, opcode_next : std_logic_vector(SUBMESSAGE_ID_WIDTH-1 downto 0) := (others => '0');
signal flags, flags_next : std_logic_vector(SUBMESSAGE_FLAGS_WIDTH-1 downto 0) := (others => '0');
signal seq_nr, seq_nr_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN;
signal next_seq_nr, next_seq_nr_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN;
signal ts, ts_next : TIME_TYPE := TIME_INVALID;
signal deadline : TIME_TYPE := TIME_INVALID;
signal sn_latch_1, sn_latch_1_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN;
signal sn_latch_2, sn_latch_2_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN;
signal sn_latch_3, sn_latch_3_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN;
signal bitmap_cnt, bitmap_cnt_next : unsigned(log2c(MAX_BITMAP_WIDTH/CDR_LONG_WIDTH)-1 downto 0) := (others => '0');
signal bitmap_latch, bitmap_latch_next : BITMAP_TYPE := (others => (others => '0'));
signal cnt2, cnt2_next : natural range 0 to BITMAP_TYPE'length := 0;
signal bitmap_pos, bitmap_pos_next : natural range 0 to MAX_BITMAP_WIDTH-1 := 0;
signal key_hash, key_hash_next : KEY_HASH_TYPE := (others => (others => '0'));
signal key_hash_rcvd, key_hash_rcvd_next : std_logic := '0';
signal status_info, status_info_next : std_logic_vector(STATUS_INFO_WIDTH-1 downto 0) := (others => '0');
signal last_word_in_latch, last_word_in_latch_next : std_logic := '0';
-- Signal used to reset the word counter -- Signal used to reset the word counter
signal reset_read_cnt : std_logic; signal reset_read_cnt : std_logic;
-- Word (4-Byte) counter (Counts words read from input fifo) -- Word (4-Byte) counter (Counts words read from input fifo)
signal read_cnt : unsigned(SUBMESSAGE_LENGTH_WIDTH-3 downto 0) := (others => '0'); signal read_cnt : unsigned(SUBMESSAGE_LENGTH_WIDTH-3 downto 0) := (others => '0');
-- Word aligned End of Parameter -- Word aligned End of Parameter
signal parameter_end, parameter_end_next : unsigned(PARAMETER_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal parameter_end, parameter_end_next : unsigned(PARAMETER_LENGTH_WIDTH-1 downto 0) := (others => '0');
-- General Purpose Counter
signal cnt, cnt_next : natural range TODO := 0;
-- Packet Opcode Latch (RTPS Message ID)
signal opcode, opcode_next : std_logic_vector(SUBMESSAGE_ID_WIDTH-1 downto 0) := (others => '0');
-- Metatraffic Opcode Latch
signal meta_opcode, meta_opcode_next : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
-- Signifies if the received packet is a metatraffic operation
signal is_meta, is_meta_next : std_logic := '0';
-- Source GUID Latch
signal guid, guid_next : GUID_TYPE := (others => (others => '0'));
-- Source IPv4 Address Latch
signal addr, addr_next : std_logic_vector(IPv4_ADDRESS_WIDTH-1 downto 0) := (others => '0');
-- UDP Port Latch
signal portn, portn_next : std_logic_vector(UDP_PORT_WIDTH-1 downto 0) := (others => '0');
-- RTPS Header Flags Latch
signal flags, flags_next : std_logic_vector(SUBMESSAGE_FLAGS_WIDTH-1 downto 0) := (others => '0');
-- Source Timestamp Latch
signal ts, ts_next : TIME_TYPE := TIME_INVALID;
-- Key Hash Latch
signal key_hash, key_hash_next : KEY_HASH_TYPE := (others => (others => '0'));
-- Signifies if a Key Hash was received
signal key_hash_rcvd, key_hash_rcvd_next : std_logic := '0';
-- Status Info Latch
signal status_info, status_info_next : std_logic_vector(STATUS_INFO_WIDTH-1 downto 0) := (others => '0');
-- Lifespan Latch
signal lifespan, lifespan_next : TIME_TYPE := TIME_INVALID;
-- RTPS Sequence Number Latch
signal seq_nr, seq_nr_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN;
-- Signifies the next expected Sequence Number
signal next_seq_nr, next_seq_nr_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN;
-- Generic Sequence Number Latch
signal sn_latch_1, sn_latch_1_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN;
-- Generic Sequence Number Latch
signal sn_latch_2, sn_latch_2_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN;
-- Generic Sequence Number Latch
signal sn_latch_3, sn_latch_3_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN;
-- Toggle latching the "last_word_in" signal until reset
signal last_word_in_latch, last_word_in_latch_next : std_logic := '0';
-- Time until next Stale Endpoint Check
signal check_time, check_time_next : TIME_TYPE := TIME_INVALID;
-- Signifies if a Stale Endpoint Check is in progress
signal stale_check, stale_check_next : std_logic := '0';
-- Signal containing the RTPS ACKNACK Count Field
signal count, count_next : unsigned(COUNT_WIDTH-1 downto 0) := (others => '0');
-- Data in represented in Big Endian
signal data_in_swapped : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); signal data_in_swapped : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
-- Denotes the number of valid Bitmap longs (4-Byte words)
signal bitmap_cnt, bitmap_cnt_next : unsigned(log2c(MAX_BITMAP_WIDTH/CDR_LONG_WIDTH)-1 downto 0) := (others => '0');
-- NumberSet Bitmap Latch
signal bitmap_latch, bitmap_latch_next : BITMAP_TYPE := (others => (others => '0'));
-- Counter used to read out Bitmaps
signal cnt2, cnt2_next : natural range 0 to BITMAP_TYPE'length := 0;
-- Signal used to iterate through Bitmaps
signal bitmap_pos, bitmap_pos_next : natural range 0 to MAX_BITMAP_WIDTH-1 := 0;
-- Signals the start of a Memory Operation
signal mem_op_start : std_logic := '0';
-- Opcode of the Memory Operation (Valid only when mem_op_start is high)
signal mem_opcode : MEM_OPCODE_TYPE := NOP;
-- Signals the end of a Memory Operation
signal mem_op_done : std_logic := '0';
-- Signal containing the relevant Endpoint Memory Format Fields of the Memory Operation
signal mem_field_flags : std_logic_vector(0 to EMF_FLAG_WIDTH-1) := (others => '0');
-- General signal used to pass TIMEs from main to memory process
signal deadline : TIME_TYPE := TIME_INVALID;
-- *MEMORY PROCESS*
-- Memory FSM state
signal mem_stage, mem_stage_next : MEM_STAGE_TYPE := IDLE; signal mem_stage, mem_stage_next : MEM_STAGE_TYPE := IDLE;
-- Pointer to current relevant Endpoint Address
signal mem_addr_base, mem_addr_base_next : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); signal mem_addr_base, mem_addr_base_next : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0');
-- Help signal used to reset the MAX Endpoint Memory Pointer
signal last_addr, last_addr_next : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); signal last_addr, last_addr_next : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0');
-- General Memory Address Latch
signal mem_addr_latch, mem_addr_latch_next : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); signal mem_addr_latch, mem_addr_latch_next : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0');
-- Highest Endpoint Memory Address (Points to first Address of last occupied Endpoint Frame)
signal max_endpoint_addr, max_endpoint_addr_next : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); signal max_endpoint_addr, max_endpoint_addr_next : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0');
-- General Purpose Couter
signal mem_cnt, mem_cnt_next : natural range TODO := 0; signal mem_cnt, mem_cnt_next : natural range TODO := 0;
-- Latch for Endpoint Data from Memory
signal mem_endpoint_data, mem_endpoint_data_next : ENDPOINT_DATA_TYPE := ZERO_ENDPOINT_DATA; signal mem_endpoint_data, mem_endpoint_data_next : ENDPOINT_DATA_TYPE := ZERO_ENDPOINT_DATA;
-- Latch for Endpoint Data from main process
signal mem_endpoint_latch_data, mem_endpoint_latch_data_next : ENDPOINT_LATCH_DATA_TYPE := ZERO_ENDPOINT_LATCH_DATA; signal mem_endpoint_latch_data, mem_endpoint_latch_data_next : ENDPOINT_LATCH_DATA_TYPE := ZERO_ENDPOINT_LATCH_DATA;
-- Position (In Endpoint Memory Frame Granularity) of current relevant Endpoint
signal mem_pos, mem_pos_next : natural range TODO := 0; signal mem_pos, mem_pos_next : natural range TODO := 0;
-- Signifies an abort of the currently initiated read transaction
signal abort_read : std_logic := '0'; signal abort_read : std_logic := '0';
-- *MEMORY CONTROL CONNECTION SIGNALS*
signal mem_addr : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); signal mem_addr : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mem_read_data, mem_write_data : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); signal mem_read_data, mem_write_data : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal mem_ready_in, mem_valid_in : std_logic := '0'; signal mem_ready_in, mem_valid_in : std_logic := '0';
signal mem_ready_out, mem_valid_out : std_logic := '0'; signal mem_ready_out, mem_valid_out : std_logic := '0';
signal mem_read : std_logic := '0'; signal mem_read : std_logic := '0';
signal stale_check, stale_check_next : std_logic := '0';
signal count, count_next : unsigned(COUNT_WIDTH-1 downto 0) := (others => '0');
signal return_stage, return_stage_next : STAGE_TYPE := IDLE;
signal check_time, check_time_next : TIME_TYPE := TIME_INVALID;
signal lifespan, lifespan_next : TIME_TYPE := TIME_INVALID;
--*****ALIAS DECLARATION***** --*****ALIAS DECLARATION*****
-- ENDPOINT FRAME HEADER -- ENDPOINT FRAME HEADER
@ -226,7 +286,8 @@ architecture arch of rtps_endpoint is
alias gap_list_end : SEQUENCENUMBER_TYPE is sn_latch_3; alias gap_list_end : SEQUENCENUMBER_TYPE is sn_latch_3;
alias gap_list_end_next : SEQUENCENUMBER_TYPE is sn_latch_3_next; alias gap_list_end_next : SEQUENCENUMBER_TYPE is sn_latch_3_next;
-- FUNCTION DECLARATION --*****FUNCTION DECLARATION*****
-- Helper function to convert BITMAP_TYPE to std_logic_vector
function to_slv_bitmap (input : BITMAP_TYPE) return std_logic_vector is function to_slv_bitmap (input : BITMAP_TYPE) return std_logic_vector is
variable ret : std_logic_vector(0 to MAX_BITMAP_WIDTH-1) := (others => '0'); variable ret : std_logic_vector(0 to MAX_BITMAP_WIDTH-1) := (others => '0');
begin begin
@ -262,13 +323,41 @@ begin
-- Big Endian Representation -- Big Endian Representation
data_in_swapped <= endian_swap(endian_flag, data_in); data_in_swapped <= endian_swap(endian_flag, data_in);
-- *Main State Machine*
-- STATE DESCRIPTION
-- IDLE Idle State. Initiates Stale Endpoint Checks, Metatraffic Packet Processing, and User Packet Processing, in that priority order.
-- LATCH_GUIDPREFIX Store source GUID Prefix
-- LATCH_ENTITYID Store source Entity ID
-- INITIATE_ENDPOINT_SEARCH Initiate Endpoint Search Memory Operation. This state is used to start the Search operation as soon as the required data is available
-- LATCH_ENDPOINT_DATA Store Remote Endpoint Data
-- METATRAFFIC_OPERATION State handling the Metatraffic Operations
-- LATCH_SRC_ADDR Store source IPv4 Address
-- LATCH_EXTRA_DATA Store source Timestamp, and source Sequence Number
-- LATCH_HEARTBEAT Store RTPS HEARTBEAT Sequence Numbers
-- PROCESS_HEARTBEAT Parse RTPS HEARTBEAT Message. Update stored Sequence Number if necessary. Set HEARTBEAT response time accordingly.
-- LATCH_GAP Store RTPS GAP Sequence Numbers
-- PROCESS_GAP Parse RTPS GAP Submsessage. Initiates search for next valid Sequence Number if currently expected Sequence Number is in GAP
-- FIND_NEXT_VALID_IN_BITMAP Iterate through Bitmap and find the next valid Sequence Number.
-- PROCESS_INLINE_QOS Parse in-line Parameter List QoS
-- LATCH_LIFESPAN Store LIFESPAN_QOS
-- LATCH_KEY_HASH Store KEY_HASH
-- LATCH_STATUS_INFO Store STATUS_INFO
-- INITIATE_ADD_CACHE_CHANGE_REQUEST Initiate an ADD_CACHE_CHANGE Operation
-- ADD_CACHE_CHANGE Send CACHE_CHANGE Data
-- PUSH_PAYLOAD Send CACHE_CHANGE Data (Direct Input Passthrough)
-- FINALIZE_ADD_CACHE_CHANGE_REQUEST Wait for ADD_CACHE_CHANGE Operation Results. Update Endpoint Data if successfull.
-- ENDPOINT_STALE_CHECK Check remote Endpoint Entries for Liveliness Lease Expiration, and Response Timeouts.
-- SEND_HEADER Send Output Data Header and RTPS Message Header
-- SEND_ACKNACK Send ACKNACK Submessage
-- SKIP_PARAMETER Skip rest of Parameter
-- SKIP_PACKET Skip rest of Packet
parse_prc : process(all) parse_prc : process(all)
variable tmp_dw : DOUBLE_WORD_ARRAY := (others => (others => '0')); variable tmp_dw : DOUBLE_WORD_ARRAY := (others => (others => '0'));
-- NOTE: We convert the bitamp to a slv to make operations easier (The tool should handle both cases equally) -- NOTE: We convert the bitamp to a slv to make operations easier (The tool should handle both cases equally)
variable tmp_bitmap : std_logic_vector(0 to MAX_BITMAP_WIDTH-1) := (others => '0'); variable tmp_bitmap : std_logic_vector(0 to MAX_BITMAP_WIDTH-1) := (others => '0');
variable rd_guard : std_logic := '0'; variable rd_guard : std_logic := '0';
begin begin
-- DEFAULT -- DEFAULT Registerd
stage_next <= stage; stage_next <= stage;
meta_opcode_next <= meta_opcode; meta_opcode_next <= meta_opcode;
cnt_next <= cnt; cnt_next <= cnt;
@ -294,19 +383,21 @@ begin
return_stage_next <= return_stage; return_stage_next <= return_stage;
check_time_next <= check_time; check_time_next <= check_time;
lifespan_next <= lifespan; lifespan_next <= lifespan;
-- DEFAULT Unregistered
mem_opcode <= NOP;
dds_opcode <= ADD_CACHE_CHANGE;
deadline <= TIME_INVALID;
meta_rd <= '0'; meta_rd <= '0';
rd <= '0'; rd <= '0';
mem_opcode <= NOP;
mem_op_start <= '0'; mem_op_start <= '0';
rd_guard := '0';
mem_field_flags <= (others => '0');
dds_start <= '0'; dds_start <= '0';
dds_opcode <= ADD_CACHE_CHANGE;
dds_data_in <= (others => '0');
dds_ready_out <= '0'; dds_ready_out <= '0';
dds_valid_in <= '0'; dds_valid_in <= '0';
dds_last_word_in <= '0'; dds_last_word_in <= '0';
deadline <= TIME_INVALID; rd_guard := '0';
mem_field_flags <= (others => '0');
dds_data_in <= (others => '0');
-- Last Word Latch Setter -- Last Word Latch Setter
@ -315,7 +406,6 @@ begin
end if; end if;
case (meta_stage) is case (meta_stage) is
-- OPCODE
when IDLE => when IDLE =>
-- RESET -- RESET
lifespan_next <= TIME_INVALID; lifespan_next <= TIME_INVALID;
@ -325,6 +415,7 @@ begin
key_hash_rcvd_next <= '0'; key_hash_rcvd_next <= '0';
is_meta_next <= '0'; is_meta_next <= '0';
-- Stale Check Timeout
if (time >= check_time) then if (time >= check_time) then
-- Memory Operation Guard -- Memory Operation Guard
if (mem_op_done = '1') then if (mem_op_done = '1') then
@ -431,7 +522,13 @@ begin
mem_op_start <= '1'; mem_op_start <= '1';
mem_opcode <= SEARCH_ENDPOINT; mem_opcode <= SEARCH_ENDPOINT;
mem_field_flags <= (others => '0'); mem_field_flags <= (others => '0');
-- Synthesis Guard
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
stage_next <= LATCH_ENDPOINT_DATA; stage_next <= LATCH_ENDPOINT_DATA;
cnt_next <= 0;
else
stage_next <= METATRAFFIC_OPERATION;
end if;
when OPCODE_ENDPOINT_UNMATCH => when OPCODE_ENDPOINT_UNMATCH =>
mem_op_start <= '1'; mem_op_start <= '1';
mem_opcode <= SEARCH_ENDPOINT; mem_opcode <= SEARCH_ENDPOINT;
@ -476,6 +573,8 @@ begin
end if; end if;
end if; end if;
when LATCH_ENDPOINT_DATA => when LATCH_ENDPOINT_DATA =>
-- Synthesis Guard
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
-- Input FIFO Guard -- Input FIFO Guard
if (meta_empty = '0') then if (meta_empty = '0') then
meta_rd <= '1'; meta_rd <= '1';
@ -494,6 +593,7 @@ begin
null; null;
end case; end case;
end if; end if;
end if;
when METATRAFFIC_OPERATION => when METATRAFFIC_OPERATION =>
-- Memory Operation Guard -- Memory Operation Guard
if (mem_op_done = '1') then if (mem_op_done = '1') then
@ -501,11 +601,14 @@ begin
when OPCODE_ENDPOINT_MATCH => when OPCODE_ENDPOINT_MATCH =>
-- Endpoint already in Memory -- Endpoint already in Memory
if (mem_addr_base /= ENDPOINT_MEMORY_MAX_ADDRESS) then if (mem_addr_base /= ENDPOINT_MEMORY_MAX_ADDRESS) then
-- Synthesis Guard
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
-- Update the Endpoint Data -- Update the Endpoint Data
-- NOTE: The Lease Duration is NOT updated in case of an update. That is the responsibility of the Liveliness Update -- NOTE: The Lease Duration is NOT updated in case of an update. That is the responsibility of the Liveliness Update
mem_op_start <= '1'; mem_op_start <= '1';
mem_opcode <= UDPATE_ENDPOINT; mem_opcode <= UDPATE_ENDPOINT;
mem_field_flags <= EMF_IPV4_ADDR_FLAG or EMF_UDP_PORT_FLAG; mem_field_flags <= EMF_IPV4_ADDR_FLAG or EMF_UDP_PORT_FLAG;
end if;
-- DONE -- DONE
stage_next <= IDLE; stage_next <= IDLE;
else else
@ -1029,7 +1132,7 @@ begin
else else
-- DONE -- DONE
dds_last_word_in <= '1'; dds_last_word_in <= '1';
stage_next <= FINALIZE_HISTORY_CACHE_REQUEST; stage_next <= FINALIZE_ADD_CACHE_CHANGE_REQUEST;
end if; end if;
else else
-- Keep State -- Keep State
@ -1052,12 +1155,12 @@ begin
-- Exit Condition -- Exit Condition
if (last_word_in = '1') then if (last_word_in = '1') then
dds_last_word_in <= '1'; dds_last_word_in <= '1';
stage_next <= FINALIZE_HISTORY_CACHE_REQUEST; stage_next <= FINALIZE_ADD_CACHE_CHANGE_REQUEST;
end if; end if;
end if; end if;
when FINALIZE_HISTORY_CACHE_REQUEST => when FINALIZE_ADD_CACHE_CHANGE_REQUEST =>
-- NOTE: Memory is already in done state from previous state (ADD_CACHE_CHANGE) -- NOTE: Memory is already in done state from previous state (ADD_CACHE_CHANGE)
assert (mem_op_done = '1') report "FINALIZE_HISTORY_CACHE_REQUEST precondition not met. mem_op_done /= '1'" severity FAILURE; assert (mem_op_done = '1') report "FINALIZE_ADD_CACHE_CHANGE_REQUEST precondition not met. mem_op_done /= '1'" severity FAILURE;
-- Wai for History Cache Response -- Wai for History Cache Response
if (dds_res /= UNDEFINED) then if (dds_res /= UNDEFINED) then
-- Operation was Accepted -- Operation was Accepted
@ -1098,8 +1201,8 @@ begin
mem_opcode <= REMOVE_ENDPOINT; mem_opcode <= REMOVE_ENDPOINT;
-- Continue Search -- Continue Search
cnt_next <= 0; cnt_next <= 0;
-- Response Time Reached -- Synthesis Guard/Response Time Reached
elsif (mem_endpoint_data.res_time /= TIME_INVALID and mem_endpoint_data.res_time <= time) then elsif (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS and mem_endpoint_data.res_time /= TIME_INVALID and mem_endpoint_data.res_time <= time) then
-- If Suppression Delay passed, zero the time -- If Suppression Delay passed, zero the time
if(mem_endpoint_data.res_time(1)(0) = '1') then if(mem_endpoint_data.res_time(1)(0) = '1') then
-- Disable Suppression -- Disable Suppression
@ -1117,6 +1220,9 @@ begin
mem_field_flags <= EMF_IPV4_ADDR_FLAG or EMF_UDP_PORT_FLAG or EMF_NEXT_SEQ_NR_FLAG; mem_field_flags <= EMF_IPV4_ADDR_FLAG or EMF_UDP_PORT_FLAG or EMF_NEXT_SEQ_NR_FLAG;
cnt_next <= 2; cnt_next <= 2;
end if; end if;
else
-- Continue Search
cnt_next <= 0;
end if; end if;
-- Set New Timeout (Select the closest next timeout) -- Set New Timeout (Select the closest next timeout)
if (mem_endpoint_data.res_time /= TIME_INVALID and mem_endpoint_data.lease_deadline /= TIME_INVALID and mem_endpoint_data.res_time < mem_endpoint_data.lease_deadline) then if (mem_endpoint_data.res_time /= TIME_INVALID and mem_endpoint_data.lease_deadline /= TIME_INVALID and mem_endpoint_data.res_time < mem_endpoint_data.lease_deadline) then
@ -1130,6 +1236,8 @@ begin
end if; end if;
end if; end if;
when 2 => when 2 =>
-- Synthesis Guard
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
-- Set Heartbeat Suppression Time -- Set Heartbeat Suppression Time
if (HEARTBEAT_SUPPRESSION_DELAY /= DURATION_INFINITE and HEARTBEAT_SUPPRESSION_DELAY /= DURATION_ZERO) then if (HEARTBEAT_SUPPRESSION_DELAY /= DURATION_INFINITE and HEARTBEAT_SUPPRESSION_DELAY /= DURATION_ZERO) then
-- Set Heartbeat Suppression Time -- Set Heartbeat Suppression Time
@ -1150,11 +1258,15 @@ begin
stage_next <= SEND_HEADER; stage_next <= SEND_HEADER;
return_stage_next <= SEND_ACKNACK; return_stage_next <= SEND_ACKNACK;
cnt_next <= 0; cnt_next <= 0;
end if;
when others => when others =>
null; null;
end case; end case;
end if; end if;
when SEND_HEADER => when SEND_HEADER =>
-- Synthesis Guard
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
-- Output FIFO Guard
if (rtps_full = '0') then if (rtps_full = '0') then
wr_sig <= '1'; wr_sig <= '1';
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
@ -1188,7 +1300,11 @@ begin
null; null;
end case; end case;
end if; end if;
end if;
when SEND_ACKNACK => when SEND_ACKNACK =>
-- Synthesis Guard
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
-- Output FIFO Guard
if (rtps_full = '0') then if (rtps_full = '0') then
wr_sig <= '1'; wr_sig <= '1';
cnt_next <= cnt + 1; cnt_next <= cnt + 1;
@ -1236,6 +1352,7 @@ begin
null; null;
end case; end case;
end if; end if;
end if;
when SKIP_PARAMETER => when SKIP_PARAMETER =>
-- Consumed last word of Packet -- Consumed last word of Packet
if (last_word_in_latch = '1' and last_word_in = '0') then if (last_word_in_latch = '1' and last_word_in = '0') then
@ -1312,6 +1429,17 @@ begin
end if; end if;
end process; end process;
-- *Memory State Machine*
-- STATE DESCRIPTION
-- IDLE Idle State. Done Signal is pulled high and Memory FSM accepts new memory operations
-- SEARCH_ENDPOINT See Memory OPCODE Description
-- GET_ENDPOINT_DATA Latch specified Endpoint Data for use by main FSM
-- INSERT_ENDPOINT See Memory OPCODE Description
-- UPDATE_ENDPOINT See Memory OPCODE Description
-- REMOVE_ENDPOINT See Memory OPCODE Description
-- FIND_EMPTY_SLOT Find first empty slot in memory.
-- RESET_MAX_POINTER Reset the max_endpoint_addr pointer to last occupied slot in memory.
-- GET_NEXT_ENDPOINT See Memory OPCODE Description
mem_ctrl_prc : process(all) mem_ctrl_prc : process(all)
begin begin
-- DEFAULT Registered -- DEFAULT Registered
@ -1363,15 +1491,15 @@ begin
mem_cnt_next <= 0; mem_cnt_next <= 0;
when UPDATE_ENDPOINT => when UPDATE_ENDPOINT =>
mem_stage_next <= UPDATE_ENDPOINT; mem_stage_next <= UPDATE_ENDPOINT;
if check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG) then if (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG)) then
mem_cnt_next <= 0; mem_cnt_next <= 0;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG) then elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG)) then
mem_cnt_next <= 1; mem_cnt_next <= 1;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_NEXT_SEQ_NR_FLAG) then elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_NEXT_SEQ_NR_FLAG) then
mem_cnt_next <= 2; mem_cnt_next <= 2;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then
mem_cnt_next <= 4; mem_cnt_next <= 4;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
mem_cnt_next <= 6; mem_cnt_next <= 6;
else else
-- DONE -- DONE
@ -1404,15 +1532,15 @@ begin
mem_cnt_next <= 0; mem_cnt_next <= 0;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_GUIDPREFIX_FLAG) then elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_GUIDPREFIX_FLAG) then
mem_cnt_next <= 1; mem_cnt_next <= 1;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG) then elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG)) then
mem_cnt_next <= 4; mem_cnt_next <= 4;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG) then elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG)) then
mem_cnt_next <= 5; mem_cnt_next <= 5;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_NEXT_SEQ_NR_FLAG) then elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_NEXT_SEQ_NR_FLAG) then
mem_cnt_next <= 6; mem_cnt_next <= 6;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then
mem_cnt_next <= 8; mem_cnt_next <= 8;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
mem_cnt_next <= 10; mem_cnt_next <= 10;
else else
-- DONE -- DONE
@ -1560,15 +1688,15 @@ begin
mem_cnt_next <= 0; mem_cnt_next <= 0;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_GUIDPREFIX_FLAG) then elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_GUIDPREFIX_FLAG) then
mem_cnt_next <= 1; mem_cnt_next <= 1;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG) then elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG)) then
mem_cnt_next <= 4; mem_cnt_next <= 4;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG) then elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG)) then
mem_cnt_next <= 5; mem_cnt_next <= 5;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_NEXT_SEQ_NR_FLAG) then elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_NEXT_SEQ_NR_FLAG) then
mem_cnt_next <= 6; mem_cnt_next <= 6;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then
mem_cnt_next <= 8; mem_cnt_next <= 8;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
mem_cnt_next <= 10; mem_cnt_next <= 10;
else else
-- DONE -- DONE
@ -1592,15 +1720,15 @@ begin
if (mem_ready_in = '1') then if (mem_ready_in = '1') then
if check_mask(mem_endpoint_latch_data.field_flag,EMF_GUIDPREFIX_FLAG) then if check_mask(mem_endpoint_latch_data.field_flag,EMF_GUIDPREFIX_FLAG) then
mem_cnt_next <= 1; mem_cnt_next <= 1;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG) then elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG)) then
mem_cnt_next <= 4; mem_cnt_next <= 4;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG) then elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG)) then
mem_cnt_next <= 5; mem_cnt_next <= 5;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_NEXT_SEQ_NR_FLAG) then elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_NEXT_SEQ_NR_FLAG) then
mem_cnt_next <= 6; mem_cnt_next <= 6;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then
mem_cnt_next <= 8; mem_cnt_next <= 8;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
mem_cnt_next <= 10; mem_cnt_next <= 10;
else else
mem_cnt_next <= 12; mem_cnt_next <= 12;
@ -1631,15 +1759,15 @@ begin
mem_read <= '1'; mem_read <= '1';
-- Memory Flow Control Guard -- Memory Flow Control Guard
if (mem_ready_in = '1') then if (mem_ready_in = '1') then
if check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG) then if (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG)) then
mem_cnt_next <= 4; mem_cnt_next <= 4;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG) then elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG)) then
mem_cnt_next <= 5; mem_cnt_next <= 5;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_NEXT_SEQ_NR_FLAG) then elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_NEXT_SEQ_NR_FLAG) then
mem_cnt_next <= 6; mem_cnt_next <= 6;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then
mem_cnt_next <= 8; mem_cnt_next <= 8;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
mem_cnt_next <= 10; mem_cnt_next <= 10;
else else
if check_mask(mem_endpoint_latch_data.field_flag,EMF_ENTITYID_FLAG) then if check_mask(mem_endpoint_latch_data.field_flag,EMF_ENTITYID_FLAG) then
@ -1651,18 +1779,20 @@ begin
end if; end if;
-- IPv4 Address -- IPv4 Address
when 4 => when 4 =>
-- Synthesis Guard
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
mem_valid_in <= '1'; mem_valid_in <= '1';
mem_addr <= mem_addr_base + EMF_IPV4_ADDR_OFFSET; mem_addr <= mem_addr_base + EMF_IPV4_ADDR_OFFSET;
mem_read <= '1'; mem_read <= '1';
-- Memory Flow Control Guard -- Memory Flow Control Guard
if (mem_ready_in = '1') then if (mem_ready_in = '1') then
if check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG) then if (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG)) then
mem_cnt_next <= 5; mem_cnt_next <= 5;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_NEXT_SEQ_NR_FLAG) then elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_NEXT_SEQ_NR_FLAG) then
mem_cnt_next <= 6; mem_cnt_next <= 6;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then
mem_cnt_next <= 8; mem_cnt_next <= 8;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS) and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
mem_cnt_next <= 10; mem_cnt_next <= 10;
else else
if check_mask(mem_endpoint_latch_data.field_flag,EMF_ENTITYID_FLAG) then if check_mask(mem_endpoint_latch_data.field_flag,EMF_ENTITYID_FLAG) then
@ -1674,8 +1804,11 @@ begin
end if; end if;
end if; end if;
end if; end if;
end if;
-- UDP Port/ Flags -- UDP Port/ Flags
when 5 => when 5 =>
-- Synthesis Guard
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
mem_valid_in <= '1'; mem_valid_in <= '1';
mem_addr <= mem_addr_base + EMF_UDP_PORT_OFFSET; mem_addr <= mem_addr_base + EMF_UDP_PORT_OFFSET;
mem_read <= '1'; mem_read <= '1';
@ -1685,20 +1818,21 @@ begin
mem_cnt_next <= 6; mem_cnt_next <= 6;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then
mem_cnt_next <= 8; mem_cnt_next <= 8;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
mem_cnt_next <= 10; mem_cnt_next <= 10;
else else
if check_mask(mem_endpoint_latch_data.field_flag,EMF_ENTITYID_FLAG) then if check_mask(mem_endpoint_latch_data.field_flag,EMF_ENTITYID_FLAG) then
mem_cnt_next <= 12; mem_cnt_next <= 12;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_GUIDPREFIX_FLAG) then elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_GUIDPREFIX_FLAG) then
mem_cnt_next <= 13; mem_cnt_next <= 13;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG) then elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG)) then
mem_cnt_next <= 16; mem_cnt_next <= 16;
else else
mem_cnt_next <= 17; mem_cnt_next <= 17;
end if; end if;
end if; end if;
end if; end if;
end if;
-- Next Sequence Number 1/2 -- Next Sequence Number 1/2
when 6 => when 6 =>
mem_valid_in <= '1'; mem_valid_in <= '1';
@ -1717,16 +1851,16 @@ begin
if (mem_ready_in = '1') then if (mem_ready_in = '1') then
if check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then if check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then
mem_cnt_next <= 8; mem_cnt_next <= 8;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
mem_cnt_next <= 10; mem_cnt_next <= 10;
else else
if check_mask(mem_endpoint_latch_data.field_flag,EMF_ENTITYID_FLAG) then if check_mask(mem_endpoint_latch_data.field_flag,EMF_ENTITYID_FLAG) then
mem_cnt_next <= 12; mem_cnt_next <= 12;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_GUIDPREFIX_FLAG) then elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_GUIDPREFIX_FLAG) then
mem_cnt_next <= 13; mem_cnt_next <= 13;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG) then elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG)) then
mem_cnt_next <= 16; mem_cnt_next <= 16;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG) then elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG)) then
mem_cnt_next <= 17; mem_cnt_next <= 17;
else else
mem_cnt_next <= 18; mem_cnt_next <= 18;
@ -1749,16 +1883,16 @@ begin
mem_read <= '1'; mem_read <= '1';
-- Memory Flow Control Guard -- Memory Flow Control Guard
if (mem_ready_in = '1') then if (mem_ready_in = '1') then
if check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then if (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
mem_cnt_next <= 10; mem_cnt_next <= 10;
else else
if check_mask(mem_endpoint_latch_data.field_flag,EMF_ENTITYID_FLAG) then if check_mask(mem_endpoint_latch_data.field_flag,EMF_ENTITYID_FLAG) then
mem_cnt_next <= 12; mem_cnt_next <= 12;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_GUIDPREFIX_FLAG) then elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_GUIDPREFIX_FLAG) then
mem_cnt_next <= 13; mem_cnt_next <= 13;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG) then elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG)) then
mem_cnt_next <= 16; mem_cnt_next <= 16;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG) then elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG)) then
mem_cnt_next <= 17; mem_cnt_next <= 17;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_NEXT_SEQ_NR_FLAG) then elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_NEXT_SEQ_NR_FLAG) then
mem_cnt_next <= 18; mem_cnt_next <= 18;
@ -1769,6 +1903,8 @@ begin
end if; end if;
-- Response Time 1/2 -- Response Time 1/2
when 10 => when 10 =>
-- Synthesis Guard
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
mem_valid_in <= '1'; mem_valid_in <= '1';
mem_addr <= mem_addr_base + EMF_RES_TIME_OFFSET; mem_addr <= mem_addr_base + EMF_RES_TIME_OFFSET;
mem_read <= '1'; mem_read <= '1';
@ -1776,8 +1912,11 @@ begin
if (mem_ready_in = '1') then if (mem_ready_in = '1') then
mem_cnt_next <= mem_cnt + 1; mem_cnt_next <= mem_cnt + 1;
end if; end if;
end if;
-- Response Time 2/2 -- Response Time 2/2
when 11 => when 11 =>
-- Synthesis Guard
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
mem_valid_in <= '1'; mem_valid_in <= '1';
mem_addr <= mem_addr_base + EMF_RES_TIME_OFFSET + 1; mem_addr <= mem_addr_base + EMF_RES_TIME_OFFSET + 1;
mem_read <= '1'; mem_read <= '1';
@ -1787,9 +1926,9 @@ begin
mem_cnt_next <= 12; mem_cnt_next <= 12;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_GUIDPREFIX_FLAG) then elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_GUIDPREFIX_FLAG) then
mem_cnt_next <= 13; mem_cnt_next <= 13;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG) then elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG)) then
mem_cnt_next <= 16; mem_cnt_next <= 16;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG) then elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG)) then
mem_cnt_next <= 17; mem_cnt_next <= 17;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_NEXT_SEQ_NR_FLAG) then elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_NEXT_SEQ_NR_FLAG) then
mem_cnt_next <= 18; mem_cnt_next <= 18;
@ -1799,6 +1938,7 @@ begin
mem_cnt_next <= 22; mem_cnt_next <= 22;
end if; end if;
end if; end if;
end if;
-- *READ DATA* -- *READ DATA*
-- Entity ID -- Entity ID
when 12 => when 12 =>
@ -1809,15 +1949,15 @@ begin
if check_mask(mem_endpoint_latch_data.field_flag,EMF_GUIDPREFIX_FLAG) then if check_mask(mem_endpoint_latch_data.field_flag,EMF_GUIDPREFIX_FLAG) then
mem_cnt_next <= 13; mem_cnt_next <= 13;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG) then elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG)) then
mem_cnt_next <= 16; mem_cnt_next <= 16;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG) then elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG)) then
mem_cnt_next <= 17; mem_cnt_next <= 17;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_NEXT_SEQ_NR_FLAG) then elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_NEXT_SEQ_NR_FLAG) then
mem_cnt_next <= 18; mem_cnt_next <= 18;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then
mem_cnt_next <= 20; mem_cnt_next <= 20;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
mem_cnt_next <= 22; mem_cnt_next <= 22;
else else
-- DONE -- DONE
@ -1849,15 +1989,15 @@ begin
if (mem_valid_out = '1') then if (mem_valid_out = '1') then
mem_endpoint_data_next.guid(2) <= mem_read_data; mem_endpoint_data_next.guid(2) <= mem_read_data;
if check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG) then if (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG)) then
mem_cnt_next <= 16; mem_cnt_next <= 16;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG) then elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG)) then
mem_cnt_next <= 17; mem_cnt_next <= 17;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_NEXT_SEQ_NR_FLAG) then elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_NEXT_SEQ_NR_FLAG) then
mem_cnt_next <= 18; mem_cnt_next <= 18;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then
mem_cnt_next <= 20; mem_cnt_next <= 20;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
mem_cnt_next <= 22; mem_cnt_next <= 22;
else else
-- DONE -- DONE
@ -1866,26 +2006,31 @@ begin
end if; end if;
-- IPv4 Address -- IPv4 Address
when 16 => when 16 =>
-- Synthesis Guard
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
mem_ready_out <= '1'; mem_ready_out <= '1';
-- Memory Flow Control Guard -- Memory Flow Control Guard
if (mem_valid_out = '1') then if (mem_valid_out = '1') then
mem_endpoint_data_next.addr <= mem_read_data; mem_endpoint_data_next.addr <= mem_read_data;
if check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG) then if (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG)) then
mem_cnt_next <= 17; mem_cnt_next <= 17;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_NEXT_SEQ_NR_FLAG) then elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_NEXT_SEQ_NR_FLAG) then
mem_cnt_next <= 18; mem_cnt_next <= 18;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then
mem_cnt_next <= 20; mem_cnt_next <= 20;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
mem_cnt_next <= 22; mem_cnt_next <= 22;
else else
-- DONE -- DONE
mem_stage_next <= IDLE; mem_stage_next <= IDLE;
end if; end if;
end if; end if;
end if;
-- UDP Port -- UDP Port
when 17 => when 17 =>
-- Synthesis Guard
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
mem_ready_out <= '1'; mem_ready_out <= '1';
-- Memory Flow Control Guard -- Memory Flow Control Guard
if (mem_valid_out = '1') then if (mem_valid_out = '1') then
@ -1895,13 +2040,14 @@ begin
mem_cnt_next <= 18; mem_cnt_next <= 18;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then
mem_cnt_next <= 20; mem_cnt_next <= 20;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
mem_cnt_next <= 22; mem_cnt_next <= 22;
else else
-- DONE -- DONE
mem_stage_next <= IDLE; mem_stage_next <= IDLE;
end if; end if;
end if; end if;
end if;
-- Next Sequence Number 1/2 -- Next Sequence Number 1/2
when 18 => when 18 =>
mem_ready_out <= '1'; mem_ready_out <= '1';
@ -1920,7 +2066,7 @@ begin
if check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then if check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then
mem_cnt_next <= 20; mem_cnt_next <= 20;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
mem_cnt_next <= 22; mem_cnt_next <= 22;
else else
-- DONE -- DONE
@ -1943,7 +2089,7 @@ begin
if (mem_valid_out = '1') then if (mem_valid_out = '1') then
mem_endpoint_data_next.addr <= mem_read_data; mem_endpoint_data_next.addr <= mem_read_data;
if check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then if (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
mem_cnt_next <= 22; mem_cnt_next <= 22;
else else
-- DONE -- DONE
@ -1952,6 +2098,8 @@ begin
end if; end if;
-- Response Time 1/2 -- Response Time 1/2
when 22 => when 22 =>
-- Synthesis Guard
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
mem_ready_out <= '1'; mem_ready_out <= '1';
-- Memory Flow Control Guard -- Memory Flow Control Guard
if (mem_valid_out = '1') then if (mem_valid_out = '1') then
@ -1959,8 +2107,11 @@ begin
mem_cnt_next <= mem_cnt + 1; mem_cnt_next <= mem_cnt + 1;
end if; end if;
end if;
-- Response Time 2/2 -- Response Time 2/2
when 23 => when 23 =>
-- Synthesis Guard
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
mem_ready_out <= '1'; mem_ready_out <= '1';
-- Memory Flow Control Guard -- Memory Flow Control Guard
if (mem_valid_out = '1') then if (mem_valid_out = '1') then
@ -1969,6 +2120,7 @@ begin
-- DONE -- DONE
mem_stage_next <= IDLE; mem_stage_next <= IDLE;
end if; end if;
end if;
when others => when others =>
null; null;
end case; end case;
@ -2004,24 +2156,30 @@ begin
mem_addr <= mem_addr_base + EMF_GUIDPREFIX_OFFSET + 2; mem_addr <= mem_addr_base + EMF_GUIDPREFIX_OFFSET + 2;
mem_write_data <= mem_endpoint_latch_data.guid(2); mem_write_data <= mem_endpoint_latch_data.guid(2);
if (mem_ready_in = '1') then if (mem_ready_in = '1') then
mem_cnt_next <= mem_cnt + 1; mem_cnt_next <= mem_cnt + 1 when (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) else 6;
end if; end if;
-- IPv4 Address -- IPv4 Address
when 4 => when 4 =>
-- Synthesis Guard
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
mem_valid_in <= '1'; mem_valid_in <= '1';
mem_addr <= mem_addr_base + EMF_IPV4_ADDR_OFFSET; mem_addr <= mem_addr_base + EMF_IPV4_ADDR_OFFSET;
mem_write_data <= mem_endpoint_latch_data.addr; mem_write_data <= mem_endpoint_latch_data.addr;
if (mem_ready_in = '1') then if (mem_ready_in = '1') then
mem_cnt_next <= mem_cnt + 1; mem_cnt_next <= mem_cnt + 1;
end if; end if;
end if;
-- UDPv4 Ports -- UDPv4 Ports
when 5 => when 5 =>
-- Synthesis Guard
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
mem_valid_in <= '1'; mem_valid_in <= '1';
mem_addr <= mem_addr_base + EMF_UDP_PORT_OFFSET; mem_addr <= mem_addr_base + EMF_UDP_PORT_OFFSET;
mem_write_data <= mem_endpoint_latch_data.portn & ((mem_write_data'length-mem_endpoint_latch_data.portn'length-1) downto 0 => '0'); mem_write_data <= mem_endpoint_latch_data.portn & ((mem_write_data'length-mem_endpoint_latch_data.portn'length-1) downto 0 => '0');
if (mem_ready_in = '1') then if (mem_ready_in = '1') then
mem_cnt_next <= mem_cnt + 1; mem_cnt_next <= mem_cnt + 1;
end if; end if;
end if;
-- Next Sequence Number 1/2 -- Next Sequence Number 1/2
when 6 => when 6 =>
mem_valid_in <= '1'; mem_valid_in <= '1';
@ -2053,18 +2211,27 @@ begin
mem_addr <= mem_addr_base + EMF_LEASE_DEADLINE_OFFSET + 1; mem_addr <= mem_addr_base + EMF_LEASE_DEADLINE_OFFSET + 1;
mem_write_data <= std_logic_vector(mem_endpoint_latch_data.deadline(1)); mem_write_data <= std_logic_vector(mem_endpoint_latch_data.deadline(1));
if (mem_ready_in = '1') then if (mem_ready_in = '1') then
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
mem_cnt_next <= mem_cnt + 1; mem_cnt_next <= mem_cnt + 1;
else
-- DONE
mem_stage_next <= IDLE;
end if; end if;
-- Response/Suppression Time 1/2 end if;
-- Response Time 1/2
when 10 => when 10 =>
-- Synthesis Guard
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
mem_valid_in <= '1'; mem_valid_in <= '1';
mem_addr <= mem_addr_base + EMF_RES_TIME_OFFSET; mem_addr <= mem_addr_base + EMF_RES_TIME_OFFSET;
mem_write_data <= (others => '0'); mem_write_data <= (others => '0');
if (mem_ready_in = '1') then if (mem_ready_in = '1') then
mem_cnt_next <= mem_cnt + 1; mem_cnt_next <= mem_cnt + 1;
end if; end if;
-- Response/Suppression Time 2/2 end if;
-- Response Time 2/2
when 11 => when 11 =>
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
mem_valid_in <= '1'; mem_valid_in <= '1';
mem_addr <= mem_addr_base + EMF_RES_TIME_OFFSET + 1; mem_addr <= mem_addr_base + EMF_RES_TIME_OFFSET + 1;
mem_write_data <= (others => '0'); mem_write_data <= (others => '0');
@ -2072,6 +2239,7 @@ begin
-- DONE -- DONE
mem_stage_next <= IDLE; mem_stage_next <= IDLE;
end if; end if;
end if;
when others => when others =>
null; null;
end case; end case;
@ -2079,27 +2247,32 @@ begin
case (mem_cnt) is case (mem_cnt) is
-- IPv4 Address -- IPv4 Address
when 0 => when 0 =>
-- Synthesis Guard
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
mem_valid_in <= '1'; mem_valid_in <= '1';
mem_addr <= mem_addr_base + EMF_IPV4_ADDR_OFFSET; mem_addr <= mem_addr_base + EMF_IPV4_ADDR_OFFSET;
mem_write_data <= mem_endpoint_latch_data.addr; mem_write_data <= mem_endpoint_latch_data.addr;
mem_endpoint_data.addr <= mem_endpoint_latch_data.addr; mem_endpoint_data.addr <= mem_endpoint_latch_data.addr;
-- Memory Flow Control Guard -- Memory Flow Control Guard
if (mem_ready_in = '1') then if (mem_ready_in = '1') then
if check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG) then if (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG)) then
mem_cnt_next <= 1; mem_cnt_next <= 1;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_NEXT_SEQ_NR_FLAG) then elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_NEXT_SEQ_NR_FLAG) then
mem_cnt_next <= 2; mem_cnt_next <= 2;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then
mem_cnt_next <= 4; mem_cnt_next <= 4;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
mem_cnt_next <= 6; mem_cnt_next <= 6;
else else
-- DONE -- DONE
mem_stage_next <= IDLE; mem_stage_next <= IDLE;
end if; end if;
end if; end if;
end if;
-- UDPv4 Ports -- UDPv4 Ports
when 1 => when 1 =>
-- Synthesis Guard
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
mem_valid_in <= '1'; mem_valid_in <= '1';
mem_addr <= mem_addr_base + EMF_UDP_PORT_OFFSET; mem_addr <= mem_addr_base + EMF_UDP_PORT_OFFSET;
mem_write_data <= mem_endpoint_latch_data.portn & ((mem_write_data'length-mem_endpoint_latch_data.portn'length-1) downto 0 => '0'); mem_write_data <= mem_endpoint_latch_data.portn & ((mem_write_data'length-mem_endpoint_latch_data.portn'length-1) downto 0 => '0');
@ -2110,13 +2283,14 @@ begin
mem_cnt_next <= 2; mem_cnt_next <= 2;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then
mem_cnt_next <= 4; mem_cnt_next <= 4;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
mem_cnt_next <= 6; mem_cnt_next <= 6;
else else
-- DONE -- DONE
mem_stage_next <= IDLE; mem_stage_next <= IDLE;
end if; end if;
end if; end if;
end if;
-- Next Sequence Number 1/2 -- Next Sequence Number 1/2
when 2 => when 2 =>
mem_valid_in <= '1'; mem_valid_in <= '1';
@ -2135,7 +2309,7 @@ begin
if (mem_ready_in = '1') then if (mem_ready_in = '1') then
if check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then if check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then
mem_cnt_next <= 4; mem_cnt_next <= 4;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
mem_cnt_next <= 6; mem_cnt_next <= 6;
else else
-- DONE -- DONE
@ -2159,15 +2333,17 @@ begin
mem_endpoint_data.lease_deadline <= mem_endpoint_latch_data.deadline; mem_endpoint_data.lease_deadline <= mem_endpoint_latch_data.deadline;
-- Memory Flow Control Guard -- Memory Flow Control Guard
if (mem_ready_in = '1') then if (mem_ready_in = '1') then
if check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then if (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
mem_cnt_next <= 6; mem_cnt_next <= 6;
else else
-- DONE -- DONE
mem_stage_next <= IDLE; mem_stage_next <= IDLE;
end if; end if;
end if; end if;
-- Response/Suppression Time 1/2 -- Response Time 1/2
when 6 => when 6 =>
-- Synthesis Guard
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
mem_valid_in <= '1'; mem_valid_in <= '1';
mem_addr <= mem_addr_base + EMF_RES_TIME_OFFSET; mem_addr <= mem_addr_base + EMF_RES_TIME_OFFSET;
mem_write_data <= std_logic_vector(mem_endpoint_latch_data.deadline(0)); mem_write_data <= std_logic_vector(mem_endpoint_latch_data.deadline(0));
@ -2175,8 +2351,11 @@ begin
if (mem_ready_in = '1') then if (mem_ready_in = '1') then
mem_cnt_next <= mem_cnt + 1; mem_cnt_next <= mem_cnt + 1;
end if; end if;
-- Response/Suppression Time 2/2 end if;
-- Response Time 2/2
when 7 => when 7 =>
-- Synthesis Guard
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
mem_valid_in <= '1'; mem_valid_in <= '1';
mem_addr <= mem_addr_base + EMF_RES_TIME_OFFSET + 1; mem_addr <= mem_addr_base + EMF_RES_TIME_OFFSET + 1;
mem_write_data <= std_logic_vector(mem_endpoint_latch_data.deadline(1)); mem_write_data <= std_logic_vector(mem_endpoint_latch_data.deadline(1));
@ -2186,6 +2365,7 @@ begin
-- DONE -- DONE
mem_stage_next <= IDLE; mem_stage_next <= IDLE;
end if; end if;
end if;
when others => when others =>
null; null;
end case; end case;
@ -2348,15 +2528,15 @@ begin
mem_cnt_next <= 0; mem_cnt_next <= 0;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_GUIDPREFIX_FLAG) then elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_GUIDPREFIX_FLAG) then
mem_cnt_next <= 1; mem_cnt_next <= 1;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG) then elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG)) then
mem_cnt_next <= 4; mem_cnt_next <= 4;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG) then elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG)) then
mem_cnt_next <= 5; mem_cnt_next <= 5;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_NEXT_SEQ_NR_FLAG) then elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_NEXT_SEQ_NR_FLAG) then
mem_cnt_next <= 6; mem_cnt_next <= 6;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then
mem_cnt_next <= 8; mem_cnt_next <= 8;
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
mem_cnt_next <= 10; mem_cnt_next <= 10;
else else
-- DONE -- DONE