Add documentation to RTPS Reader, Best Efoort RELIABILITY uses less memory
RELIABILITY_QOS is checked, allowing BEST EFFORT to use less memory.
This commit is contained in:
Greek
parent
d54bf55b46
commit
d4795c1838
@ -14,8 +14,9 @@ use work.rtps_config_package.all;
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-- TODO: Is mem_addr_base needed? Isn't it a direct mirror of addr_mem_base? mem_addr_base is only used in the same clock cycle as mem_op_done is pulled high.
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entity rtps_endpoint is
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entity rtps_reader is
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generic (
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RELIABILTY_QOS : std_logic_vector(CDR_ENUMERATION_WIDTH-1 downto 0) := DEFAULT_RELIABILTY_QOS;
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HEARTBEAT_RESPONSE_DELAY : DURATION_TYPE := TODO;
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HEARTBEAT_SUPPRESSION_DELAY : DURATION_TYPE := TODO;
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LEASE_DURATION : DURATION_TYPE := DEFAULT_LEASE_DURATION;
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@ -51,7 +52,7 @@ entity rtps_endpoint is
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);
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end entity;
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architecture arch of rtps_endpoint is
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architecture arch of rtps_reader is
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--*****CONSTANT DECLARATION*****
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-- *ENDPOINT MEMORY*
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@ -83,18 +84,32 @@ architecture arch of rtps_endpoint is
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constant EMF_GUIDPREFIX_OFFSET : natural := 1;
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constant EMF_IPV4_ADDR_OFFSET : natural := 4;
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constant EMF_UDP_PORT_OFFSET : natural := 5;
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constant EMF_NEXT_SEQ_NR_OFFSET : natural := 6;
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constant EMF_LEASE_DEADLINE_OFFSET : natural := 8;
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constant EMF_RES_TIME_OFFSET : natural := 10;
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constant EMF_NEXT_SEQ_NR_OFFSET : natural := 6 when (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) else EMF_GUIDPREFIX_OFFSET + 3;
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constant EMF_LEASE_DEADLINE_OFFSET : natural := EMF_NEXT_SEQ_NR_OFFSET + 2;
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constant EMF_RES_TIME_OFFSET : natural := EMF_LEASE_DEADLINE_OFFSET + 2;
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--*****TYPE DECLARATION*****
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-- FSM states. Explained below in detail
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type STAGE_TYPE is (IDLE, TODO);
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-- Memory FSM Opcodes
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type MEM_OPCODE_TYPE is (NOP, TODO);
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type MEM_STAGE_TYPE is (IDLE, TODO);
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-- Record of all Participant Data stored in memory
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type STAGE_TYPE is (IDLE, LATCH_GUIDPREFIX, LATCH_ENTITYID, INITIATE_ENDPOINT_SEARCH, LATCH_ENDPOINT_DATA, METATRAFFIC_OPERATION, LATCH_SRC_ADDR,
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LATCH_EXTRA_DATA, LATCH_HEARTBEAT, PROCESS_HEARTBEAT, LATCH_GAP, PROCESS_GAP, FIND_NEXT_VALID_IN_BITMAP, PROCESS_INLINE_QOS, LATCH_LIFESPAN,
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LATCH_KEY_HASH, LATCH_STATUS_INFO, INITIATE_ADD_CACHE_CHANGE_REQUEST, ADD_CACHE_CHANGE, PUSH_PAYLOAD, FINALIZE_ADD_CACHE_CHANGE_REQUEST,
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ENDPOINT_STALE_CHECK, SEND_HEADER, SEND_ACKNACK, SKIP_PARAMETER, SKIP_PACKET);
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-- Memory FSM states. Explaine below in detail
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type MEM_STAGE_TYPE is (IDLE, SEARCH_ENDPOINT, GET_ENDPOINT_DATA, INSERT_ENDPOINT, UPDATE_ENDPOINT, REMOVE_ENDPOINT, FIND_EMPTY_SLOT,
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RESET_MAX_POINTER, GET_NEXT_ENDPOINT);
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-- *Memory FSM Opcodes*
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-- OPCODE DESCRIPTION
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-- SEARCH_ENDPOINT Find Endpoint with specified GUID in memory
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-- INSERT_ENDPOINT Insert Endpoint to first available empty slot in memory
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-- UPDATE_ENDPOINT Update Endpoint pointed by mem_addr_base. (mem_field_flags specifies which Fields to update)
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-- REMOVE_ENDPOINT Remove Endpoint pointed by mem_addr_base
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-- GET_FIRST_ENDPOINT Get Endpoint Data of first Endpoint stored in Memory. (mem_field_flags specifies which Fields to get)
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-- GET_NEXT_ENDPOINT Get Endpoint Data of next Endpoint (from the Endpoint pointed by mem_addr_base) stored in Memory. (mem_field_flags specifies which Fields to get)
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-- GET_ENDPOINT Get Endpoint Data from Endpoint currently pointed by mem_addr_base. (mem_field_flags specifies which Fields to get)
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type MEM_OPCODE_TYPE is (NOP, SEARCH_ENDPOINT, INSERT_ENDPOINT, UPDATE_ENDPOINT, REMOVE_ENDPOINT, GET_FIRST_ENDPOINT, GET_NEXT_ENDPOINT,
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GET_ENDPOINT);
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-- Record of Endpoint Data
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type ENDPOINT_DATA_TYPE is record
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guid : GUID_TYPE;
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addr : std_logic_vector(IPv4_ADDRESS_WIDTH-1 downto 0);
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@ -103,6 +118,7 @@ architecture arch of rtps_endpoint is
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lease_deadline : TIME_TYPE;
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res_time : TIME_TYPE;
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end record;
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-- Zero initialized Endpoint Data
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constant ZERO_ENDPOINT_DATA : ENDPOINT_DATA_TYPE := (
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guid => GUID_UNKNOWN,
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addr => IPv4_ADDRESS_INVALID,
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@ -111,6 +127,7 @@ architecture arch of rtps_endpoint is
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lease_deadline => TIME_INVALID,
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res_time => TIME_INVALID
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);
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-- Endpoint Data Latch used as temporal cache by Memory Process
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type ENDPOINT_LATCH_DATA_TYPE is record
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guid : GUID_TYPE;
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addr : std_logic_vector(IPv4_ADDRESS_WIDTH-1 downto 0);
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@ -119,6 +136,7 @@ architecture arch of rtps_endpoint is
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next_seq_nr : SEQUENCENUMBER_TYPE;
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field_flag : std_logic_vector(0 to EMF_FLAG_WIDTH-1);
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end record;
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-- Zero initialized Endpoint Data Latch
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constant ZERO_ENDPOINT_LATCH_DATA : ENDPOINT_LATCH_DATA_TYPE := (
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guid => GUID_UNKNOWN,
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addr => IPv4_ADDRESS_INVALID,
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@ -130,69 +148,111 @@ architecture arch of rtps_endpoint is
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--*****SIGNAL DECLARATION*****
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-- *MAIN PROCESS*
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-- FSM state
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signal stage, stage_next : STAGE_TYPE := IDLE;
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signal meta_opcode, meta_opcode_next : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
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signal cnt, cnt_next : natural range TODO := 0;
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signal guid, guid_next : GUID_TYPE := (others => (others => '0'));
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signal mem_op_done : std_logic := '0';
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signal mem_opcode : MEM_OPCODE_TYPE := NOP;
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signal mem_op_start : std_logic := '0';
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signal addr, addr_next : std_logic_vector(IPv4_ADDRESS_WIDTH-1 downto 0) := (others => '0');
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signal portn, portn_next : std_logic_vector(UDP_PORT_WIDTH-1 downto 0) := (others => '0');
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signal expects_inline_qos, expects_inline_qos_next : std_logic := '0';
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signal is_meta, is_meta_next : std_logic := '0';
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signal mem_field_flags : std_logic_vector(0 to EMF_FLAG_WIDTH-1) := (others => '0');
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signal opcode, opcode_next : std_logic_vector(SUBMESSAGE_ID_WIDTH-1 downto 0) := (others => '0');
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signal flags, flags_next : std_logic_vector(SUBMESSAGE_FLAGS_WIDTH-1 downto 0) := (others => '0');
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signal seq_nr, seq_nr_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN;
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signal next_seq_nr, next_seq_nr_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN;
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signal ts, ts_next : TIME_TYPE := TIME_INVALID;
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signal deadline : TIME_TYPE := TIME_INVALID;
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signal sn_latch_1, sn_latch_1_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN;
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signal sn_latch_2, sn_latch_2_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN;
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signal sn_latch_3, sn_latch_3_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN;
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signal bitmap_cnt, bitmap_cnt_next : unsigned(log2c(MAX_BITMAP_WIDTH/CDR_LONG_WIDTH)-1 downto 0) := (others => '0');
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signal bitmap_latch, bitmap_latch_next : BITMAP_TYPE := (others => (others => '0'));
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signal cnt2, cnt2_next : natural range 0 to BITMAP_TYPE'length := 0;
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signal bitmap_pos, bitmap_pos_next : natural range 0 to MAX_BITMAP_WIDTH-1 := 0;
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signal key_hash, key_hash_next : KEY_HASH_TYPE := (others => (others => '0'));
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signal key_hash_rcvd, key_hash_rcvd_next : std_logic := '0';
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signal status_info, status_info_next : std_logic_vector(STATUS_INFO_WIDTH-1 downto 0) := (others => '0');
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signal last_word_in_latch, last_word_in_latch_next : std_logic := '0';
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-- FSM state latch. Used to transition dynamically to different states from the same state.
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signal return_stage, return_stage_next : STAGE_TYPE := IDLE;
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-- Signal used to reset the word counter
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signal reset_read_cnt : std_logic;
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-- Word (4-Byte) counter (Counts words read from input fifo)
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signal read_cnt : unsigned(SUBMESSAGE_LENGTH_WIDTH-3 downto 0) := (others => '0');
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-- Word aligned End of Parameter
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signal parameter_end, parameter_end_next : unsigned(PARAMETER_LENGTH_WIDTH-1 downto 0) := (others => '0');
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-- General Purpose Counter
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signal cnt, cnt_next : natural range TODO := 0;
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-- Packet Opcode Latch (RTPS Message ID)
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signal opcode, opcode_next : std_logic_vector(SUBMESSAGE_ID_WIDTH-1 downto 0) := (others => '0');
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-- Metatraffic Opcode Latch
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signal meta_opcode, meta_opcode_next : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
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-- Signifies if the received packet is a metatraffic operation
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signal is_meta, is_meta_next : std_logic := '0';
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-- Source GUID Latch
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signal guid, guid_next : GUID_TYPE := (others => (others => '0'));
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-- Source IPv4 Address Latch
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signal addr, addr_next : std_logic_vector(IPv4_ADDRESS_WIDTH-1 downto 0) := (others => '0');
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-- UDP Port Latch
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signal portn, portn_next : std_logic_vector(UDP_PORT_WIDTH-1 downto 0) := (others => '0');
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-- RTPS Header Flags Latch
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signal flags, flags_next : std_logic_vector(SUBMESSAGE_FLAGS_WIDTH-1 downto 0) := (others => '0');
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-- Source Timestamp Latch
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signal ts, ts_next : TIME_TYPE := TIME_INVALID;
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-- Key Hash Latch
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signal key_hash, key_hash_next : KEY_HASH_TYPE := (others => (others => '0'));
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-- Signifies if a Key Hash was received
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signal key_hash_rcvd, key_hash_rcvd_next : std_logic := '0';
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-- Status Info Latch
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signal status_info, status_info_next : std_logic_vector(STATUS_INFO_WIDTH-1 downto 0) := (others => '0');
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-- Lifespan Latch
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signal lifespan, lifespan_next : TIME_TYPE := TIME_INVALID;
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-- RTPS Sequence Number Latch
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signal seq_nr, seq_nr_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN;
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-- Signifies the next expected Sequence Number
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signal next_seq_nr, next_seq_nr_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN;
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-- Generic Sequence Number Latch
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signal sn_latch_1, sn_latch_1_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN;
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-- Generic Sequence Number Latch
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signal sn_latch_2, sn_latch_2_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN;
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-- Generic Sequence Number Latch
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signal sn_latch_3, sn_latch_3_next : SEQUENCENUMBER_TYPE := SEQUENCENUMBER_UNKNOWN;
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-- Toggle latching the "last_word_in" signal until reset
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signal last_word_in_latch, last_word_in_latch_next : std_logic := '0';
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-- Time until next Stale Endpoint Check
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signal check_time, check_time_next : TIME_TYPE := TIME_INVALID;
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-- Signifies if a Stale Endpoint Check is in progress
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signal stale_check, stale_check_next : std_logic := '0';
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-- Signal containing the RTPS ACKNACK Count Field
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signal count, count_next : unsigned(COUNT_WIDTH-1 downto 0) := (others => '0');
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-- Data in represented in Big Endian
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signal data_in_swapped : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
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-- Denotes the number of valid Bitmap longs (4-Byte words)
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signal bitmap_cnt, bitmap_cnt_next : unsigned(log2c(MAX_BITMAP_WIDTH/CDR_LONG_WIDTH)-1 downto 0) := (others => '0');
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-- NumberSet Bitmap Latch
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signal bitmap_latch, bitmap_latch_next : BITMAP_TYPE := (others => (others => '0'));
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-- Counter used to read out Bitmaps
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signal cnt2, cnt2_next : natural range 0 to BITMAP_TYPE'length := 0;
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-- Signal used to iterate through Bitmaps
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signal bitmap_pos, bitmap_pos_next : natural range 0 to MAX_BITMAP_WIDTH-1 := 0;
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-- Signals the start of a Memory Operation
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signal mem_op_start : std_logic := '0';
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-- Opcode of the Memory Operation (Valid only when mem_op_start is high)
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signal mem_opcode : MEM_OPCODE_TYPE := NOP;
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-- Signals the end of a Memory Operation
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signal mem_op_done : std_logic := '0';
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-- Signal containing the relevant Endpoint Memory Format Fields of the Memory Operation
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signal mem_field_flags : std_logic_vector(0 to EMF_FLAG_WIDTH-1) := (others => '0');
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-- General signal used to pass TIMEs from main to memory process
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signal deadline : TIME_TYPE := TIME_INVALID;
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-- *MEMORY PROCESS*
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-- Memory FSM state
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signal mem_stage, mem_stage_next : MEM_STAGE_TYPE := IDLE;
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-- Pointer to current relevant Endpoint Address
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signal mem_addr_base, mem_addr_base_next : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0');
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-- Help signal used to reset the MAX Endpoint Memory Pointer
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signal last_addr, last_addr_next : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0');
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-- General Memory Address Latch
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signal mem_addr_latch, mem_addr_latch_next : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0');
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-- Highest Endpoint Memory Address (Points to first Address of last occupied Endpoint Frame)
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signal max_endpoint_addr, max_endpoint_addr_next : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0');
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-- General Purpose Couter
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signal mem_cnt, mem_cnt_next : natural range TODO := 0;
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-- Latch for Endpoint Data from Memory
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signal mem_endpoint_data, mem_endpoint_data_next : ENDPOINT_DATA_TYPE := ZERO_ENDPOINT_DATA;
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-- Latch for Endpoint Data from main process
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signal mem_endpoint_latch_data, mem_endpoint_latch_data_next : ENDPOINT_LATCH_DATA_TYPE := ZERO_ENDPOINT_LATCH_DATA;
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-- Position (In Endpoint Memory Frame Granularity) of current relevant Endpoint
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signal mem_pos, mem_pos_next : natural range TODO := 0;
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-- Signifies an abort of the currently initiated read transaction
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signal abort_read : std_logic := '0';
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-- *MEMORY CONTROL CONNECTION SIGNALS*
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signal mem_addr : unsigned(ENDPOINT_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0');
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signal mem_read_data, mem_write_data : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
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signal mem_ready_in, mem_valid_in : std_logic := '0';
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signal mem_ready_out, mem_valid_out : std_logic := '0';
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signal mem_read : std_logic := '0';
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signal stale_check, stale_check_next : std_logic := '0';
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signal count, count_next : unsigned(COUNT_WIDTH-1 downto 0) := (others => '0');
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signal return_stage, return_stage_next : STAGE_TYPE := IDLE;
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signal check_time, check_time_next : TIME_TYPE := TIME_INVALID;
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signal lifespan, lifespan_next : TIME_TYPE := TIME_INVALID;
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--*****ALIAS DECLARATION*****
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-- ENDPOINT FRAME HEADER
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@ -226,7 +286,8 @@ architecture arch of rtps_endpoint is
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alias gap_list_end : SEQUENCENUMBER_TYPE is sn_latch_3;
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alias gap_list_end_next : SEQUENCENUMBER_TYPE is sn_latch_3_next;
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-- FUNCTION DECLARATION
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--*****FUNCTION DECLARATION*****
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-- Helper function to convert BITMAP_TYPE to std_logic_vector
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function to_slv_bitmap (input : BITMAP_TYPE) return std_logic_vector is
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variable ret : std_logic_vector(0 to MAX_BITMAP_WIDTH-1) := (others => '0');
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begin
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@ -262,13 +323,41 @@ begin
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-- Big Endian Representation
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data_in_swapped <= endian_swap(endian_flag, data_in);
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-- *Main State Machine*
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-- STATE DESCRIPTION
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-- IDLE Idle State. Initiates Stale Endpoint Checks, Metatraffic Packet Processing, and User Packet Processing, in that priority order.
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-- LATCH_GUIDPREFIX Store source GUID Prefix
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-- LATCH_ENTITYID Store source Entity ID
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-- INITIATE_ENDPOINT_SEARCH Initiate Endpoint Search Memory Operation. This state is used to start the Search operation as soon as the required data is available
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-- LATCH_ENDPOINT_DATA Store Remote Endpoint Data
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-- METATRAFFIC_OPERATION State handling the Metatraffic Operations
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-- LATCH_SRC_ADDR Store source IPv4 Address
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-- LATCH_EXTRA_DATA Store source Timestamp, and source Sequence Number
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-- LATCH_HEARTBEAT Store RTPS HEARTBEAT Sequence Numbers
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-- PROCESS_HEARTBEAT Parse RTPS HEARTBEAT Message. Update stored Sequence Number if necessary. Set HEARTBEAT response time accordingly.
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-- LATCH_GAP Store RTPS GAP Sequence Numbers
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-- PROCESS_GAP Parse RTPS GAP Submsessage. Initiates search for next valid Sequence Number if currently expected Sequence Number is in GAP
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-- FIND_NEXT_VALID_IN_BITMAP Iterate through Bitmap and find the next valid Sequence Number.
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-- PROCESS_INLINE_QOS Parse in-line Parameter List QoS
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-- LATCH_LIFESPAN Store LIFESPAN_QOS
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-- LATCH_KEY_HASH Store KEY_HASH
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-- LATCH_STATUS_INFO Store STATUS_INFO
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-- INITIATE_ADD_CACHE_CHANGE_REQUEST Initiate an ADD_CACHE_CHANGE Operation
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-- ADD_CACHE_CHANGE Send CACHE_CHANGE Data
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-- PUSH_PAYLOAD Send CACHE_CHANGE Data (Direct Input Passthrough)
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-- FINALIZE_ADD_CACHE_CHANGE_REQUEST Wait for ADD_CACHE_CHANGE Operation Results. Update Endpoint Data if successfull.
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-- ENDPOINT_STALE_CHECK Check remote Endpoint Entries for Liveliness Lease Expiration, and Response Timeouts.
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-- SEND_HEADER Send Output Data Header and RTPS Message Header
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-- SEND_ACKNACK Send ACKNACK Submessage
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-- SKIP_PARAMETER Skip rest of Parameter
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-- SKIP_PACKET Skip rest of Packet
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parse_prc : process(all)
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variable tmp_dw : DOUBLE_WORD_ARRAY := (others => (others => '0'));
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-- NOTE: We convert the bitamp to a slv to make operations easier (The tool should handle both cases equally)
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variable tmp_bitmap : std_logic_vector(0 to MAX_BITMAP_WIDTH-1) := (others => '0');
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variable rd_guard : std_logic := '0';
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begin
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-- DEFAULT
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-- DEFAULT Registerd
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stage_next <= stage;
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meta_opcode_next <= meta_opcode;
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cnt_next <= cnt;
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@ -294,19 +383,21 @@ begin
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return_stage_next <= return_stage;
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check_time_next <= check_time;
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lifespan_next <= lifespan;
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-- DEFAULT Unregistered
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mem_opcode <= NOP;
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dds_opcode <= ADD_CACHE_CHANGE;
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deadline <= TIME_INVALID;
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meta_rd <= '0';
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rd <= '0';
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mem_opcode <= NOP;
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mem_op_start <= '0';
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rd_guard := '0';
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mem_field_flags <= (others => '0');
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dds_start <= '0';
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dds_opcode <= ADD_CACHE_CHANGE;
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dds_data_in <= (others => '0');
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dds_ready_out <= '0';
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dds_valid_in <= '0';
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dds_last_word_in <= '0';
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deadline <= TIME_INVALID;
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rd_guard := '0';
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mem_field_flags <= (others => '0');
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dds_data_in <= (others => '0');
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-- Last Word Latch Setter
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@ -315,7 +406,6 @@ begin
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end if;
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case (meta_stage) is
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-- OPCODE
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when IDLE =>
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-- RESET
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lifespan_next <= TIME_INVALID;
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@ -325,6 +415,7 @@ begin
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key_hash_rcvd_next <= '0';
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is_meta_next <= '0';
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|
||||
-- Stale Check Timeout
|
||||
if (time >= check_time) then
|
||||
-- Memory Operation Guard
|
||||
if (mem_op_done = '1') then
|
||||
@ -431,7 +522,13 @@ begin
|
||||
mem_op_start <= '1';
|
||||
mem_opcode <= SEARCH_ENDPOINT;
|
||||
mem_field_flags <= (others => '0');
|
||||
-- Synthesis Guard
|
||||
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
|
||||
stage_next <= LATCH_ENDPOINT_DATA;
|
||||
cnt_next <= 0;
|
||||
else
|
||||
stage_next <= METATRAFFIC_OPERATION;
|
||||
end if;
|
||||
when OPCODE_ENDPOINT_UNMATCH =>
|
||||
mem_op_start <= '1';
|
||||
mem_opcode <= SEARCH_ENDPOINT;
|
||||
@ -476,6 +573,8 @@ begin
|
||||
end if;
|
||||
end if;
|
||||
when LATCH_ENDPOINT_DATA =>
|
||||
-- Synthesis Guard
|
||||
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
|
||||
-- Input FIFO Guard
|
||||
if (meta_empty = '0') then
|
||||
meta_rd <= '1';
|
||||
@ -494,6 +593,7 @@ begin
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
when METATRAFFIC_OPERATION =>
|
||||
-- Memory Operation Guard
|
||||
if (mem_op_done = '1') then
|
||||
@ -501,11 +601,14 @@ begin
|
||||
when OPCODE_ENDPOINT_MATCH =>
|
||||
-- Endpoint already in Memory
|
||||
if (mem_addr_base /= ENDPOINT_MEMORY_MAX_ADDRESS) then
|
||||
-- Synthesis Guard
|
||||
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
|
||||
-- Update the Endpoint Data
|
||||
-- NOTE: The Lease Duration is NOT updated in case of an update. That is the responsibility of the Liveliness Update
|
||||
mem_op_start <= '1';
|
||||
mem_opcode <= UDPATE_ENDPOINT;
|
||||
mem_field_flags <= EMF_IPV4_ADDR_FLAG or EMF_UDP_PORT_FLAG;
|
||||
end if;
|
||||
-- DONE
|
||||
stage_next <= IDLE;
|
||||
else
|
||||
@ -1029,7 +1132,7 @@ begin
|
||||
else
|
||||
-- DONE
|
||||
dds_last_word_in <= '1';
|
||||
stage_next <= FINALIZE_HISTORY_CACHE_REQUEST;
|
||||
stage_next <= FINALIZE_ADD_CACHE_CHANGE_REQUEST;
|
||||
end if;
|
||||
else
|
||||
-- Keep State
|
||||
@ -1052,12 +1155,12 @@ begin
|
||||
-- Exit Condition
|
||||
if (last_word_in = '1') then
|
||||
dds_last_word_in <= '1';
|
||||
stage_next <= FINALIZE_HISTORY_CACHE_REQUEST;
|
||||
stage_next <= FINALIZE_ADD_CACHE_CHANGE_REQUEST;
|
||||
end if;
|
||||
end if;
|
||||
when FINALIZE_HISTORY_CACHE_REQUEST =>
|
||||
when FINALIZE_ADD_CACHE_CHANGE_REQUEST =>
|
||||
-- NOTE: Memory is already in done state from previous state (ADD_CACHE_CHANGE)
|
||||
assert (mem_op_done = '1') report "FINALIZE_HISTORY_CACHE_REQUEST precondition not met. mem_op_done /= '1'" severity FAILURE;
|
||||
assert (mem_op_done = '1') report "FINALIZE_ADD_CACHE_CHANGE_REQUEST precondition not met. mem_op_done /= '1'" severity FAILURE;
|
||||
-- Wai for History Cache Response
|
||||
if (dds_res /= UNDEFINED) then
|
||||
-- Operation was Accepted
|
||||
@ -1098,8 +1201,8 @@ begin
|
||||
mem_opcode <= REMOVE_ENDPOINT;
|
||||
-- Continue Search
|
||||
cnt_next <= 0;
|
||||
-- Response Time Reached
|
||||
elsif (mem_endpoint_data.res_time /= TIME_INVALID and mem_endpoint_data.res_time <= time) then
|
||||
-- Synthesis Guard/Response Time Reached
|
||||
elsif (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS and mem_endpoint_data.res_time /= TIME_INVALID and mem_endpoint_data.res_time <= time) then
|
||||
-- If Suppression Delay passed, zero the time
|
||||
if(mem_endpoint_data.res_time(1)(0) = '1') then
|
||||
-- Disable Suppression
|
||||
@ -1117,6 +1220,9 @@ begin
|
||||
mem_field_flags <= EMF_IPV4_ADDR_FLAG or EMF_UDP_PORT_FLAG or EMF_NEXT_SEQ_NR_FLAG;
|
||||
cnt_next <= 2;
|
||||
end if;
|
||||
else
|
||||
-- Continue Search
|
||||
cnt_next <= 0;
|
||||
end if;
|
||||
-- Set New Timeout (Select the closest next timeout)
|
||||
if (mem_endpoint_data.res_time /= TIME_INVALID and mem_endpoint_data.lease_deadline /= TIME_INVALID and mem_endpoint_data.res_time < mem_endpoint_data.lease_deadline) then
|
||||
@ -1130,6 +1236,8 @@ begin
|
||||
end if;
|
||||
end if;
|
||||
when 2 =>
|
||||
-- Synthesis Guard
|
||||
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
|
||||
-- Set Heartbeat Suppression Time
|
||||
if (HEARTBEAT_SUPPRESSION_DELAY /= DURATION_INFINITE and HEARTBEAT_SUPPRESSION_DELAY /= DURATION_ZERO) then
|
||||
-- Set Heartbeat Suppression Time
|
||||
@ -1150,11 +1258,15 @@ begin
|
||||
stage_next <= SEND_HEADER;
|
||||
return_stage_next <= SEND_ACKNACK;
|
||||
cnt_next <= 0;
|
||||
end if;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
when SEND_HEADER =>
|
||||
-- Synthesis Guard
|
||||
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
|
||||
-- Output FIFO Guard
|
||||
if (rtps_full = '0') then
|
||||
wr_sig <= '1';
|
||||
cnt_next <= cnt + 1;
|
||||
@ -1188,7 +1300,11 @@ begin
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
when SEND_ACKNACK =>
|
||||
-- Synthesis Guard
|
||||
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
|
||||
-- Output FIFO Guard
|
||||
if (rtps_full = '0') then
|
||||
wr_sig <= '1';
|
||||
cnt_next <= cnt + 1;
|
||||
@ -1236,6 +1352,7 @@ begin
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
when SKIP_PARAMETER =>
|
||||
-- Consumed last word of Packet
|
||||
if (last_word_in_latch = '1' and last_word_in = '0') then
|
||||
@ -1312,6 +1429,17 @@ begin
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- *Memory State Machine*
|
||||
-- STATE DESCRIPTION
|
||||
-- IDLE Idle State. Done Signal is pulled high and Memory FSM accepts new memory operations
|
||||
-- SEARCH_ENDPOINT See Memory OPCODE Description
|
||||
-- GET_ENDPOINT_DATA Latch specified Endpoint Data for use by main FSM
|
||||
-- INSERT_ENDPOINT See Memory OPCODE Description
|
||||
-- UPDATE_ENDPOINT See Memory OPCODE Description
|
||||
-- REMOVE_ENDPOINT See Memory OPCODE Description
|
||||
-- FIND_EMPTY_SLOT Find first empty slot in memory.
|
||||
-- RESET_MAX_POINTER Reset the max_endpoint_addr pointer to last occupied slot in memory.
|
||||
-- GET_NEXT_ENDPOINT See Memory OPCODE Description
|
||||
mem_ctrl_prc : process(all)
|
||||
begin
|
||||
-- DEFAULT Registered
|
||||
@ -1363,15 +1491,15 @@ begin
|
||||
mem_cnt_next <= 0;
|
||||
when UPDATE_ENDPOINT =>
|
||||
mem_stage_next <= UPDATE_ENDPOINT;
|
||||
if check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG) then
|
||||
if (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG)) then
|
||||
mem_cnt_next <= 0;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG) then
|
||||
elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG)) then
|
||||
mem_cnt_next <= 1;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_NEXT_SEQ_NR_FLAG) then
|
||||
mem_cnt_next <= 2;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then
|
||||
mem_cnt_next <= 4;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then
|
||||
elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
|
||||
mem_cnt_next <= 6;
|
||||
else
|
||||
-- DONE
|
||||
@ -1404,15 +1532,15 @@ begin
|
||||
mem_cnt_next <= 0;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_GUIDPREFIX_FLAG) then
|
||||
mem_cnt_next <= 1;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG) then
|
||||
elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG)) then
|
||||
mem_cnt_next <= 4;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG) then
|
||||
elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG)) then
|
||||
mem_cnt_next <= 5;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_NEXT_SEQ_NR_FLAG) then
|
||||
mem_cnt_next <= 6;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then
|
||||
mem_cnt_next <= 8;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then
|
||||
elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
|
||||
mem_cnt_next <= 10;
|
||||
else
|
||||
-- DONE
|
||||
@ -1560,15 +1688,15 @@ begin
|
||||
mem_cnt_next <= 0;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_GUIDPREFIX_FLAG) then
|
||||
mem_cnt_next <= 1;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG) then
|
||||
elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG)) then
|
||||
mem_cnt_next <= 4;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG) then
|
||||
elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG)) then
|
||||
mem_cnt_next <= 5;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_NEXT_SEQ_NR_FLAG) then
|
||||
mem_cnt_next <= 6;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then
|
||||
mem_cnt_next <= 8;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then
|
||||
elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
|
||||
mem_cnt_next <= 10;
|
||||
else
|
||||
-- DONE
|
||||
@ -1592,15 +1720,15 @@ begin
|
||||
if (mem_ready_in = '1') then
|
||||
if check_mask(mem_endpoint_latch_data.field_flag,EMF_GUIDPREFIX_FLAG) then
|
||||
mem_cnt_next <= 1;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG) then
|
||||
elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG)) then
|
||||
mem_cnt_next <= 4;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG) then
|
||||
elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG)) then
|
||||
mem_cnt_next <= 5;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_NEXT_SEQ_NR_FLAG) then
|
||||
mem_cnt_next <= 6;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then
|
||||
mem_cnt_next <= 8;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then
|
||||
elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
|
||||
mem_cnt_next <= 10;
|
||||
else
|
||||
mem_cnt_next <= 12;
|
||||
@ -1631,15 +1759,15 @@ begin
|
||||
mem_read <= '1';
|
||||
-- Memory Flow Control Guard
|
||||
if (mem_ready_in = '1') then
|
||||
if check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG) then
|
||||
if (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG)) then
|
||||
mem_cnt_next <= 4;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG) then
|
||||
elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG)) then
|
||||
mem_cnt_next <= 5;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_NEXT_SEQ_NR_FLAG) then
|
||||
mem_cnt_next <= 6;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then
|
||||
mem_cnt_next <= 8;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then
|
||||
elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
|
||||
mem_cnt_next <= 10;
|
||||
else
|
||||
if check_mask(mem_endpoint_latch_data.field_flag,EMF_ENTITYID_FLAG) then
|
||||
@ -1651,18 +1779,20 @@ begin
|
||||
end if;
|
||||
-- IPv4 Address
|
||||
when 4 =>
|
||||
-- Synthesis Guard
|
||||
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
|
||||
mem_valid_in <= '1';
|
||||
mem_addr <= mem_addr_base + EMF_IPV4_ADDR_OFFSET;
|
||||
mem_read <= '1';
|
||||
-- Memory Flow Control Guard
|
||||
if (mem_ready_in = '1') then
|
||||
if check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG) then
|
||||
if (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG)) then
|
||||
mem_cnt_next <= 5;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_NEXT_SEQ_NR_FLAG) then
|
||||
mem_cnt_next <= 6;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then
|
||||
mem_cnt_next <= 8;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then
|
||||
elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS) and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
|
||||
mem_cnt_next <= 10;
|
||||
else
|
||||
if check_mask(mem_endpoint_latch_data.field_flag,EMF_ENTITYID_FLAG) then
|
||||
@ -1674,8 +1804,11 @@ begin
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
-- UDP Port/ Flags
|
||||
when 5 =>
|
||||
-- Synthesis Guard
|
||||
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
|
||||
mem_valid_in <= '1';
|
||||
mem_addr <= mem_addr_base + EMF_UDP_PORT_OFFSET;
|
||||
mem_read <= '1';
|
||||
@ -1685,20 +1818,21 @@ begin
|
||||
mem_cnt_next <= 6;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then
|
||||
mem_cnt_next <= 8;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then
|
||||
elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
|
||||
mem_cnt_next <= 10;
|
||||
else
|
||||
if check_mask(mem_endpoint_latch_data.field_flag,EMF_ENTITYID_FLAG) then
|
||||
mem_cnt_next <= 12;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_GUIDPREFIX_FLAG) then
|
||||
mem_cnt_next <= 13;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG) then
|
||||
elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG)) then
|
||||
mem_cnt_next <= 16;
|
||||
else
|
||||
mem_cnt_next <= 17;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
-- Next Sequence Number 1/2
|
||||
when 6 =>
|
||||
mem_valid_in <= '1';
|
||||
@ -1717,16 +1851,16 @@ begin
|
||||
if (mem_ready_in = '1') then
|
||||
if check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then
|
||||
mem_cnt_next <= 8;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then
|
||||
elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
|
||||
mem_cnt_next <= 10;
|
||||
else
|
||||
if check_mask(mem_endpoint_latch_data.field_flag,EMF_ENTITYID_FLAG) then
|
||||
mem_cnt_next <= 12;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_GUIDPREFIX_FLAG) then
|
||||
mem_cnt_next <= 13;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG) then
|
||||
elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG)) then
|
||||
mem_cnt_next <= 16;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG) then
|
||||
elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG)) then
|
||||
mem_cnt_next <= 17;
|
||||
else
|
||||
mem_cnt_next <= 18;
|
||||
@ -1749,16 +1883,16 @@ begin
|
||||
mem_read <= '1';
|
||||
-- Memory Flow Control Guard
|
||||
if (mem_ready_in = '1') then
|
||||
if check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then
|
||||
if (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
|
||||
mem_cnt_next <= 10;
|
||||
else
|
||||
if check_mask(mem_endpoint_latch_data.field_flag,EMF_ENTITYID_FLAG) then
|
||||
mem_cnt_next <= 12;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_GUIDPREFIX_FLAG) then
|
||||
mem_cnt_next <= 13;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG) then
|
||||
elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG)) then
|
||||
mem_cnt_next <= 16;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG) then
|
||||
elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG)) then
|
||||
mem_cnt_next <= 17;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_NEXT_SEQ_NR_FLAG) then
|
||||
mem_cnt_next <= 18;
|
||||
@ -1769,6 +1903,8 @@ begin
|
||||
end if;
|
||||
-- Response Time 1/2
|
||||
when 10 =>
|
||||
-- Synthesis Guard
|
||||
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
|
||||
mem_valid_in <= '1';
|
||||
mem_addr <= mem_addr_base + EMF_RES_TIME_OFFSET;
|
||||
mem_read <= '1';
|
||||
@ -1776,8 +1912,11 @@ begin
|
||||
if (mem_ready_in = '1') then
|
||||
mem_cnt_next <= mem_cnt + 1;
|
||||
end if;
|
||||
end if;
|
||||
-- Response Time 2/2
|
||||
when 11 =>
|
||||
-- Synthesis Guard
|
||||
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
|
||||
mem_valid_in <= '1';
|
||||
mem_addr <= mem_addr_base + EMF_RES_TIME_OFFSET + 1;
|
||||
mem_read <= '1';
|
||||
@ -1787,9 +1926,9 @@ begin
|
||||
mem_cnt_next <= 12;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_GUIDPREFIX_FLAG) then
|
||||
mem_cnt_next <= 13;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG) then
|
||||
elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG)) then
|
||||
mem_cnt_next <= 16;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG) then
|
||||
elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG)) then
|
||||
mem_cnt_next <= 17;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_NEXT_SEQ_NR_FLAG) then
|
||||
mem_cnt_next <= 18;
|
||||
@ -1799,6 +1938,7 @@ begin
|
||||
mem_cnt_next <= 22;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
-- *READ DATA*
|
||||
-- Entity ID
|
||||
when 12 =>
|
||||
@ -1809,15 +1949,15 @@ begin
|
||||
|
||||
if check_mask(mem_endpoint_latch_data.field_flag,EMF_GUIDPREFIX_FLAG) then
|
||||
mem_cnt_next <= 13;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG) then
|
||||
elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG)) then
|
||||
mem_cnt_next <= 16;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG) then
|
||||
elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG)) then
|
||||
mem_cnt_next <= 17;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_NEXT_SEQ_NR_FLAG) then
|
||||
mem_cnt_next <= 18;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then
|
||||
mem_cnt_next <= 20;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then
|
||||
elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
|
||||
mem_cnt_next <= 22;
|
||||
else
|
||||
-- DONE
|
||||
@ -1849,15 +1989,15 @@ begin
|
||||
if (mem_valid_out = '1') then
|
||||
mem_endpoint_data_next.guid(2) <= mem_read_data;
|
||||
|
||||
if check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG) then
|
||||
if (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG)) then
|
||||
mem_cnt_next <= 16;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG) then
|
||||
elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG)) then
|
||||
mem_cnt_next <= 17;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_NEXT_SEQ_NR_FLAG) then
|
||||
mem_cnt_next <= 18;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then
|
||||
mem_cnt_next <= 20;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then
|
||||
elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
|
||||
mem_cnt_next <= 22;
|
||||
else
|
||||
-- DONE
|
||||
@ -1866,26 +2006,31 @@ begin
|
||||
end if;
|
||||
-- IPv4 Address
|
||||
when 16 =>
|
||||
-- Synthesis Guard
|
||||
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
|
||||
mem_ready_out <= '1';
|
||||
-- Memory Flow Control Guard
|
||||
if (mem_valid_out = '1') then
|
||||
mem_endpoint_data_next.addr <= mem_read_data;
|
||||
|
||||
if check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG) then
|
||||
if (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG)) then
|
||||
mem_cnt_next <= 17;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_NEXT_SEQ_NR_FLAG) then
|
||||
mem_cnt_next <= 18;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then
|
||||
mem_cnt_next <= 20;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then
|
||||
elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
|
||||
mem_cnt_next <= 22;
|
||||
else
|
||||
-- DONE
|
||||
mem_stage_next <= IDLE;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
-- UDP Port
|
||||
when 17 =>
|
||||
-- Synthesis Guard
|
||||
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
|
||||
mem_ready_out <= '1';
|
||||
-- Memory Flow Control Guard
|
||||
if (mem_valid_out = '1') then
|
||||
@ -1895,13 +2040,14 @@ begin
|
||||
mem_cnt_next <= 18;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then
|
||||
mem_cnt_next <= 20;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then
|
||||
elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
|
||||
mem_cnt_next <= 22;
|
||||
else
|
||||
-- DONE
|
||||
mem_stage_next <= IDLE;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
-- Next Sequence Number 1/2
|
||||
when 18 =>
|
||||
mem_ready_out <= '1';
|
||||
@ -1920,7 +2066,7 @@ begin
|
||||
|
||||
if check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then
|
||||
mem_cnt_next <= 20;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then
|
||||
elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
|
||||
mem_cnt_next <= 22;
|
||||
else
|
||||
-- DONE
|
||||
@ -1943,7 +2089,7 @@ begin
|
||||
if (mem_valid_out = '1') then
|
||||
mem_endpoint_data_next.addr <= mem_read_data;
|
||||
|
||||
if check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then
|
||||
if (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
|
||||
mem_cnt_next <= 22;
|
||||
else
|
||||
-- DONE
|
||||
@ -1952,6 +2098,8 @@ begin
|
||||
end if;
|
||||
-- Response Time 1/2
|
||||
when 22 =>
|
||||
-- Synthesis Guard
|
||||
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
|
||||
mem_ready_out <= '1';
|
||||
-- Memory Flow Control Guard
|
||||
if (mem_valid_out = '1') then
|
||||
@ -1959,8 +2107,11 @@ begin
|
||||
|
||||
mem_cnt_next <= mem_cnt + 1;
|
||||
end if;
|
||||
end if;
|
||||
-- Response Time 2/2
|
||||
when 23 =>
|
||||
-- Synthesis Guard
|
||||
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
|
||||
mem_ready_out <= '1';
|
||||
-- Memory Flow Control Guard
|
||||
if (mem_valid_out = '1') then
|
||||
@ -1969,6 +2120,7 @@ begin
|
||||
-- DONE
|
||||
mem_stage_next <= IDLE;
|
||||
end if;
|
||||
end if;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
@ -2004,24 +2156,30 @@ begin
|
||||
mem_addr <= mem_addr_base + EMF_GUIDPREFIX_OFFSET + 2;
|
||||
mem_write_data <= mem_endpoint_latch_data.guid(2);
|
||||
if (mem_ready_in = '1') then
|
||||
mem_cnt_next <= mem_cnt + 1;
|
||||
mem_cnt_next <= mem_cnt + 1 when (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) else 6;
|
||||
end if;
|
||||
-- IPv4 Address
|
||||
when 4 =>
|
||||
-- Synthesis Guard
|
||||
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
|
||||
mem_valid_in <= '1';
|
||||
mem_addr <= mem_addr_base + EMF_IPV4_ADDR_OFFSET;
|
||||
mem_write_data <= mem_endpoint_latch_data.addr;
|
||||
if (mem_ready_in = '1') then
|
||||
mem_cnt_next <= mem_cnt + 1;
|
||||
end if;
|
||||
end if;
|
||||
-- UDPv4 Ports
|
||||
when 5 =>
|
||||
-- Synthesis Guard
|
||||
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
|
||||
mem_valid_in <= '1';
|
||||
mem_addr <= mem_addr_base + EMF_UDP_PORT_OFFSET;
|
||||
mem_write_data <= mem_endpoint_latch_data.portn & ((mem_write_data'length-mem_endpoint_latch_data.portn'length-1) downto 0 => '0');
|
||||
if (mem_ready_in = '1') then
|
||||
mem_cnt_next <= mem_cnt + 1;
|
||||
end if;
|
||||
end if;
|
||||
-- Next Sequence Number 1/2
|
||||
when 6 =>
|
||||
mem_valid_in <= '1';
|
||||
@ -2053,18 +2211,27 @@ begin
|
||||
mem_addr <= mem_addr_base + EMF_LEASE_DEADLINE_OFFSET + 1;
|
||||
mem_write_data <= std_logic_vector(mem_endpoint_latch_data.deadline(1));
|
||||
if (mem_ready_in = '1') then
|
||||
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
|
||||
mem_cnt_next <= mem_cnt + 1;
|
||||
else
|
||||
-- DONE
|
||||
mem_stage_next <= IDLE;
|
||||
end if;
|
||||
-- Response/Suppression Time 1/2
|
||||
end if;
|
||||
-- Response Time 1/2
|
||||
when 10 =>
|
||||
-- Synthesis Guard
|
||||
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
|
||||
mem_valid_in <= '1';
|
||||
mem_addr <= mem_addr_base + EMF_RES_TIME_OFFSET;
|
||||
mem_write_data <= (others => '0');
|
||||
if (mem_ready_in = '1') then
|
||||
mem_cnt_next <= mem_cnt + 1;
|
||||
end if;
|
||||
-- Response/Suppression Time 2/2
|
||||
end if;
|
||||
-- Response Time 2/2
|
||||
when 11 =>
|
||||
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
|
||||
mem_valid_in <= '1';
|
||||
mem_addr <= mem_addr_base + EMF_RES_TIME_OFFSET + 1;
|
||||
mem_write_data <= (others => '0');
|
||||
@ -2072,6 +2239,7 @@ begin
|
||||
-- DONE
|
||||
mem_stage_next <= IDLE;
|
||||
end if;
|
||||
end if;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
@ -2079,27 +2247,32 @@ begin
|
||||
case (mem_cnt) is
|
||||
-- IPv4 Address
|
||||
when 0 =>
|
||||
-- Synthesis Guard
|
||||
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
|
||||
mem_valid_in <= '1';
|
||||
mem_addr <= mem_addr_base + EMF_IPV4_ADDR_OFFSET;
|
||||
mem_write_data <= mem_endpoint_latch_data.addr;
|
||||
mem_endpoint_data.addr <= mem_endpoint_latch_data.addr;
|
||||
-- Memory Flow Control Guard
|
||||
if (mem_ready_in = '1') then
|
||||
if check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG) then
|
||||
if (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG)) then
|
||||
mem_cnt_next <= 1;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_NEXT_SEQ_NR_FLAG) then
|
||||
mem_cnt_next <= 2;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then
|
||||
mem_cnt_next <= 4;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then
|
||||
elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
|
||||
mem_cnt_next <= 6;
|
||||
else
|
||||
-- DONE
|
||||
mem_stage_next <= IDLE;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
-- UDPv4 Ports
|
||||
when 1 =>
|
||||
-- Synthesis Guard
|
||||
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
|
||||
mem_valid_in <= '1';
|
||||
mem_addr <= mem_addr_base + EMF_UDP_PORT_OFFSET;
|
||||
mem_write_data <= mem_endpoint_latch_data.portn & ((mem_write_data'length-mem_endpoint_latch_data.portn'length-1) downto 0 => '0');
|
||||
@ -2110,13 +2283,14 @@ begin
|
||||
mem_cnt_next <= 2;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then
|
||||
mem_cnt_next <= 4;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then
|
||||
elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
|
||||
mem_cnt_next <= 6;
|
||||
else
|
||||
-- DONE
|
||||
mem_stage_next <= IDLE;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
-- Next Sequence Number 1/2
|
||||
when 2 =>
|
||||
mem_valid_in <= '1';
|
||||
@ -2135,7 +2309,7 @@ begin
|
||||
if (mem_ready_in = '1') then
|
||||
if check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then
|
||||
mem_cnt_next <= 4;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then
|
||||
elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
|
||||
mem_cnt_next <= 6;
|
||||
else
|
||||
-- DONE
|
||||
@ -2159,15 +2333,17 @@ begin
|
||||
mem_endpoint_data.lease_deadline <= mem_endpoint_latch_data.deadline;
|
||||
-- Memory Flow Control Guard
|
||||
if (mem_ready_in = '1') then
|
||||
if check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then
|
||||
if (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
|
||||
mem_cnt_next <= 6;
|
||||
else
|
||||
-- DONE
|
||||
mem_stage_next <= IDLE;
|
||||
end if;
|
||||
end if;
|
||||
-- Response/Suppression Time 1/2
|
||||
-- Response Time 1/2
|
||||
when 6 =>
|
||||
-- Synthesis Guard
|
||||
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
|
||||
mem_valid_in <= '1';
|
||||
mem_addr <= mem_addr_base + EMF_RES_TIME_OFFSET;
|
||||
mem_write_data <= std_logic_vector(mem_endpoint_latch_data.deadline(0));
|
||||
@ -2175,8 +2351,11 @@ begin
|
||||
if (mem_ready_in = '1') then
|
||||
mem_cnt_next <= mem_cnt + 1;
|
||||
end if;
|
||||
-- Response/Suppression Time 2/2
|
||||
end if;
|
||||
-- Response Time 2/2
|
||||
when 7 =>
|
||||
-- Synthesis Guard
|
||||
if (RELIABILTY_QOS = RELIABLE_RELIABILITY_QOS) then
|
||||
mem_valid_in <= '1';
|
||||
mem_addr <= mem_addr_base + EMF_RES_TIME_OFFSET + 1;
|
||||
mem_write_data <= std_logic_vector(mem_endpoint_latch_data.deadline(1));
|
||||
@ -2186,6 +2365,7 @@ begin
|
||||
-- DONE
|
||||
mem_stage_next <= IDLE;
|
||||
end if;
|
||||
end if;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
@ -2348,15 +2528,15 @@ begin
|
||||
mem_cnt_next <= 0;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_GUIDPREFIX_FLAG) then
|
||||
mem_cnt_next <= 1;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG) then
|
||||
elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_IPV4_ADDR_FLAG)) then
|
||||
mem_cnt_next <= 4;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG) then
|
||||
elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_UDP_PORT_FLAG)) then
|
||||
mem_cnt_next <= 5;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_NEXT_SEQ_NR_FLAG) then
|
||||
mem_cnt_next <= 6;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_LEASE_DEADLINE_FLAG) then
|
||||
mem_cnt_next <= 8;
|
||||
elsif check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG) then
|
||||
elsif (RELIABILTY_QOS /= RELIABLE_RELIABILITY_QOS and check_mask(mem_endpoint_latch_data.field_flag,EMF_RES_TIME_FLAG)) then
|
||||
mem_cnt_next <= 10;
|
||||
else
|
||||
-- DONE
|
||||
Loading…
Reference in New Issue
Block a user