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Add Level 1 Test 1 for Type2 Reader and Writer Wrapper

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By connecting the output of the writer_wrapper to the input of the
reader_wrapper we can effectively test the encoding/decoding.
Since the writer_wrapper only uses Big Endian we cannot test Little
Endian handling.
This commit is contained in:
Greek 2021-11-05 13:39:48 +01:00
parent 2b3e3ae23b
commit eef62e17ce
6 changed files with 646 additions and 95 deletions
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55
sim/L1_Type2_wrapper.do Normal file
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onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider SYSTEM
add wave -noupdate /l1_type2_wrapper_test1/clk
add wave -noupdate /l1_type2_wrapper_test1/reset
add wave -noupdate -divider WRITER_WRAPPER
add wave -noupdate /l1_type2_wrapper_test1/uut_w/start_user
add wave -noupdate /l1_type2_wrapper_test1/uut_w/opcode_user
add wave -noupdate /l1_type2_wrapper_test1/uut_w/ack_dds
add wave -noupdate /l1_type2_wrapper_test1/uut_w/stage
add wave -noupdate /l1_type2_wrapper_test1/uut_w/stage_next
add wave -noupdate /l1_type2_wrapper_test1/uut_w/encode_stage
add wave -noupdate /l1_type2_wrapper_test1/uut_w/encode_stage_next
add wave -noupdate /l1_type2_wrapper_test1/uut_w/cnt
add wave -noupdate -radix hexadecimal /l1_type2_wrapper_test1/uut_w/data_out_latch
add wave -noupdate /l1_type2_wrapper_test1/uut_w/align_offset
add wave -noupdate /l1_type2_wrapper_test1/uut_w/encode_done
add wave -noupdate -divider INTERCONNECT
add wave -noupdate /l1_type2_wrapper_test1/ready
add wave -noupdate /l1_type2_wrapper_test1/valid
add wave -noupdate -radix hexadecimal /l1_type2_wrapper_test1/data
add wave -noupdate /l1_type2_wrapper_test1/last_word
add wave -noupdate -divider READER_WRAPPER
add wave -noupdate /l1_type2_wrapper_test1/uut_r/si_valid_data_dds
add wave -noupdate /l1_type2_wrapper_test1/uut_r/si_valid_dds
add wave -noupdate /l1_type2_wrapper_test1/uut_r/si_ack_user
add wave -noupdate /l1_type2_wrapper_test1/uut_r/get_data_user
add wave -noupdate /l1_type2_wrapper_test1/uut_r/stage
add wave -noupdate /l1_type2_wrapper_test1/uut_r/stage_next
add wave -noupdate /l1_type2_wrapper_test1/uut_r/decode_stage
add wave -noupdate /l1_type2_wrapper_test1/uut_r/decode_stage_next
add wave -noupdate /l1_type2_wrapper_test1/uut_r/cnt
add wave -noupdate /l1_type2_wrapper_test1/uut_r/align_offset
add wave -noupdate /l1_type2_wrapper_test1/uut_r/optional
add wave -noupdate /l1_type2_wrapper_test1/uut_r/decode_error
add wave -noupdate /l1_type2_wrapper_test1/uut_r/valid
add wave -noupdate -divider MISC
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {5853656 ps} 0}
quietly wave cursor active 1
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {5683200 ps} {6707200 ps}

477
src/Tests/Level_1/L1_Type2_wrapper_test1.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library osvvm; -- Utility Library
context osvvm.OsvvmContext;
use work.rtps_package.all;
use work.user_config.all;
use work.rtps_config_package.all;
use work.rtps_test_package.all;
use work.Type2_package.all;
entity L1_Type2_wrapper_test1 is
end entity;
architecture testbench of L1_Type2_wrapper_test1 is
signal clk, reset : std_logic := '0';
signal ready, valid, last_word : std_logic := '0';
signal data : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal start_w, get_data_r, decode_error, valid_r, encode_done : std_logic := '0';
signal id_in, id_out : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_len_in, TestSequence_len_out, TestSequence_addr_in, TestSequence_addr_out : std_logic_vector(TESTSEQUENCE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_ready_in, TestSequence_ready_out, TestSequence_ren_in, TestSequence_ren_out, TestSequence_wen_in, TestSequence_valid_in, TestSequence_valid_out, TestSequence_ack_in, TestSequence_ack_out : std_logic := '0';
signal TestSequence_TestArray_addr_in, TestSequence_TestArray_addr_out : std_logic_vector(TESTSEQUENCE_TESTARRAY_ADDR_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_TestArray_ready_in, TestSequence_TestArray_ready_out, TestSequence_TestArray_ren_in, TestSequence_TestArray_ren_out, TestSequence_TestArray_wen_in, TestSequence_TestArray_valid_in, TestSequence_TestArray_valid_out, TestSequence_TestArray_ack_in, TestSequence_TestArray_ack_out : std_logic := '0';
signal TestSequence_TestArray_r_in, TestSequence_TestArray_w_in, TestSequence_TestArray_out : std_logic_vector(CDR_OCTET_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_TestChar_r_in, TestSequence_TestChar_w_in, TestSequence_TestChar_out : std_logic_vector(CDR_CHAR_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_TestWChar_r_in, TestSequence_TestWChar_w_in, TestSequence_TestWChar_out : std_logic_vector(CDR_WCHAR_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_TestLongLong_r_in, TestSequence_TestLongLong_w_in, TestSequence_TestLongLong_out : std_logic_vector(CDR_LONG_LONG_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_TestLongDouble_r_in, TestSequence_TestLongDouble_w_in, TestSequence_TestLongDouble_out : std_logic_vector(CDR_LONG_DOUBLE_WIDTH-1 downto 0) := (others => '0');
signal TestSequence_TestLongDouble_valid_r_in, TestSequence_TestLongDouble_valid_w_in, TestSequence_TestLongDouble_valid_out : std_logic := '0';
signal TestMap_len_in, TestMap_len_out, TestMap_addr_in, TestMap_addr_out : std_logic_vector(TESTMAP_ADDR_WIDTH-1 downto 0) := (others => '0');
signal TestMap_ready_in, TestMap_ready_out, TestMap_ren_in, TestMap_ren_out, TestMap_wen_in, TestMap_valid_in, TestMap_valid_out, TestMap_ack_in, TestMap_ack_out : std_logic := '0';
signal TestMap_key_r_in, TestMap_key_w_in, TestMap_key_out : std_logic_vector(CDR_OCTET_WIDTH-1 downto 0) := (others => '0');
signal TestMap_value_r_in, TestMap_value_w_in, TestMap_value_out : std_logic_vector(CDR_SHORT_WIDTH-1 downto 0) := (others => '0');
signal TestEnum_in, TestEnum_out : std_logic_vector(TESTENUM_WIDTH-1 downto 0) := (others => '0');
signal TestUnion_valid_in, TestUnion_valid_out : std_logic := '0';
signal TestUnion_d_in, TestUnion_d_out : std_logic_vector(CDR_CHAR_WIDTH-1 downto 0) := (others => '0');
signal TestUnion_LongU_in, TestUnion_LongU_out : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0');
signal TestUnion_OctetU_in, TestUnion_OctetU_out : std_logic_vector(CDR_OCTET_WIDTH-1 downto 0) := (others => '0');
signal TestBitmask_in, TestBitmask_out : std_logic_vector(TESTBITMASK_WIDTH-1 downto 0) := (others => '0');
signal TestString_len_in, TestString_len_out, TestString_addr_in, TestString_addr_out : std_logic_vector(TESTSTRING_ADDR_WIDTH-1 downto 0) := (others => '0');
signal TestString_ready_in, TestString_ready_out, TestString_ren_in, TestString_ren_out, TestString_wen_in, TestString_valid_in, TestString_valid_out, TestString_ack_in, TestString_ack_out : std_logic := '0';
signal TestString_r_in, TestString_w_in, TestString_out : std_logic_vector(CDR_CHAR_WIDTH-1 downto 0) := (others => '0');
begin
uut_w : entity work.Type2_writer_wrapper(arch)
port map (
clk => clk,
reset => reset,
start_dds => open,
ack_dds => '1',
opcode_dds => open,
instance_handle_dds => open,
source_ts_dds => open,
max_wait_dds => open,
done_dds => '1',
return_code_dds => RETCODE_OK,
ready_out_dds => ready,
valid_out_dds => valid,
data_out_dds => data,
last_word_out_dds => last_word,
ready_in_dds => open,
valid_in_dds => '0',
data_in_dds => (others => '0'),
last_word_in_dds => '0',
status_dds => (others => '0'),
start_user => start_w,
ack_user => open,
opcode_user => WRITE,
instance_handle_user => HANDLE_NIL,
source_ts_user => TIME_ZERO,
max_wait_user => TIME_INFINITE,
done_user => open,
return_code_user => open,
ready_out_user => '1',
valid_out_user => open,
data_out_user => open,
last_word_out_user => open,
status_user => open,
encode_done => encode_done,
id => id_in,
TestSequence_len => TestSequence_len_in,
TestSequence_addr => TestSequence_addr_in,
TestSequence_ready => TestSequence_ready_in,
TestSequence_ren => TestSequence_ren_in,
TestSequence_wen => TestSequence_wen_in,
TestSequence_valid => TestSequence_valid_in,
TestSequence_ack => TestSequence_ack_in,
TestSequence_TestArray_addr => TestSequence_TestArray_addr_in,
TestSequence_TestArray_ready => TestSequence_TestArray_ready_in,
TestSequence_TestArray_ren => TestSequence_TestArray_ren_in,
TestSequence_TestArray_wen => TestSequence_TestArray_wen_in,
TestSequence_TestArray_valid => TestSequence_TestArray_valid_in,
TestSequence_TestArray_ack => TestSequence_TestArray_ack_in,
TestSequence_TestArray_r => TestSequence_TestArray_r_in,
TestSequence_TestArray_w => TestSequence_TestArray_w_in,
TestSequence_TestChar_r => TestSequence_TestChar_r_in,
TestSequence_TestChar_w => TestSequence_TestChar_w_in,
TestSequence_TestWChar_r => TestSequence_TestWChar_r_in,
TestSequence_TestWChar_w => TestSequence_TestWChar_w_in,
TestSequence_TestLongLong_r => TestSequence_TestLongLong_r_in,
TestSequence_TestLongLong_w => TestSequence_TestLongLong_w_in,
TestSequence_TestLongDouble_r => TestSequence_TestLongDouble_r_in,
TestSequence_TestLongDouble_w => TestSequence_TestLongDouble_w_in,
TestSequence_TestLongDouble_valid_r => TestSequence_TestLongDouble_valid_r_in,
TestSequence_TestLongDouble_valid_w => TestSequence_TestLongDouble_valid_w_in,
TestMap_len => TestMap_len_in,
TestMap_addr => TestMap_addr_in,
TestMap_ready => TestMap_ready_in,
TestMap_ren => TestMap_ren_in,
TestMap_wen => TestMap_wen_in,
TestMap_valid => TestMap_valid_in,
TestMap_ack => TestMap_ack_in,
TestMap_key_r => TestMap_key_r_in,
TestMap_key_w => TestMap_key_w_in,
TestMap_value_r => TestMap_value_r_in,
TestMap_value_w => TestMap_value_w_in,
TestEnum => TestEnum_in,
TestUnion_valid => TestUnion_valid_in,
TestUnion_d => TestUnion_d_in,
TestUnion_LongU => TestUnion_LongU_in,
TestUnion_OctetU => TestUnion_OctetU_in,
TestBitmask => TestBitmask_in,
TestString_len => TestString_len_in,
TestString_addr => TestString_addr_in,
TestString_ready => TestString_ready_in,
TestString_ren => TestString_ren_in,
TestString_wen => TestString_wen_in,
TestString_valid => TestString_valid_in,
TestString_ack => TestString_ack_in,
TestString_r => TestString_r_in,
TestString_w => TestString_w_in
);
uut_r : entity work.Type2_reader_wrapper(arch)
port map (
clk => clk,
reset => reset,
start_dds => open,
ack_dds => '1',
opcode_dds => open,
instance_state_dds => open,
view_state_dds => open,
sample_state_dds => open,
instance_handle_dds => open,
max_samples_dds => open,
get_data_dds => open,
done_dds => '1',
return_code_dds => RETCODE_OK,
ready_in_dds => ready,
valid_in_dds => valid,
data_in_dds => data,
last_word_in_dds => last_word,
si_sample_state_dds => (others => '0'),
si_view_state_dds => (others => '0'),
si_instance_state_dds => (others => '0'),
si_source_timestamp_dds => TIME_ZERO,
si_instance_handle_dds => HANDLE_NIL,
si_publication_handle_dds => GUID_UNKNOWN,
si_disposed_generation_count_dds => (others => '0'),
si_no_writers_generation_count_dds => (others => '0'),
si_sample_rank_dds => (others => '0'),
si_generation_rank_dds => (others => '0'),
si_absolute_generation_rank_dds => (others => '0'),
si_valid_data_dds => '1',
si_valid_dds => '1',
si_ack_dds => open,
eoc_dds => '1',
status_dds => (others => '0'),
start_user => '0',
ack_user => open,
opcode_user => NOP,
instance_state_user => (others => '0'),
view_state_user => (others => '0'),
sample_state_user => (others => '0'),
instance_handle_user => HANDLE_NIL,
max_samples_user => (others => '0'),
get_data_user => get_data_r,
done_user => open,
return_code_user => open,
si_sample_state_user => open,
si_view_state_user => open,
si_instance_state_user => open,
si_source_timestamp_user => open,
si_instance_handle_user => open,
si_publication_handle_user => open,
si_disposed_generation_count_user => open,
si_no_writers_generation_count_user => open,
si_sample_rank_user => open,
si_generation_rank_user => open,
si_absolute_generation_rank_user => open,
si_valid_data_user => open,
si_valid_user => open,
si_ack_user => '1',
eoc_user => open,
status_user => open,
decode_error => decode_error,
id => id_out,
TestSequence_len => TestSequence_len_out,
TestSequence_addr => TestSequence_addr_out,
TestSequence_ready => TestSequence_ready_out,
TestSequence_ren => TestSequence_ren_out,
TestSequence_valid => TestSequence_valid_out,
TestSequence_ack => TestSequence_ack_out,
TestSequence_TestArray_addr => TestSequence_TestArray_addr_out,
TestSequence_TestArray_ready => TestSequence_TestArray_ready_out,
TestSequence_TestArray_ren => TestSequence_TestArray_ren_out,
TestSequence_TestArray_valid => TestSequence_TestArray_valid_out,
TestSequence_TestArray_ack => TestSequence_TestArray_ack_out,
TestSequence_TestArray => TestSequence_TestArray_out,
TestSequence_TestChar => TestSequence_TestChar_out,
TestSequence_TestWChar => TestSequence_TestWChar_out,
TestSequence_TestLongLong => TestSequence_TestLongLong_out,
TestSequence_TestLongDouble => TestSequence_TestLongDouble_out,
TestSequence_TestLongDouble_valid => TestSequence_TestLongDouble_valid_out,
TestMap_len => TestMap_len_out,
TestMap_addr => TestMap_addr_out,
TestMap_ready => TestMap_ready_out,
TestMap_ren => TestMap_ren_out,
TestMap_valid => TestMap_valid_out,
TestMap_ack => TestMap_ack_out,
TestMap_key => TestMap_key_out,
TestMap_value => TestMap_value_out,
TestEnum => TestEnum_out,
TestUnion_valid => TestUnion_valid_out,
TestUnion_d => TestUnion_d_out,
TestUnion_LongU => TestUnion_LongU_out,
TestUnion_OctetU => TestUnion_OctetU_out,
TestBitmask => TestBitmask_out,
TestString_len => TestString_len_out,
TestString_addr => TestString_addr_out,
TestString_ready => TestString_ready_out,
TestString_ren => TestString_ren_out,
TestString_valid => TestString_valid_out,
TestString_ack => TestString_ack_out,
TestString => TestString_out,
valid => valid_r
);
stimulus_prc : process
variable RV : RandomPType;
variable ID, TS_TA, TS_TC, TS_TWC, TS_TLL, TS_TLD, TM, TE, TU, TB, TS : AlertLogIDType;
procedure wait_on_sig(signal sig : std_logic) is
begin
if (sig /= '1') then
wait on sig until sig = '1';
end if;
end procedure;
begin
SetAlertLogName("Type2_wrapper - Level 1");
SetAlertEnable(FAILURE, TRUE);
SetAlertEnable(ERROR, TRUE);
SetAlertEnable(WARNING, TRUE);
SetLogEnable(DEBUG, FALSE);
SetLogEnable(PASSED, FALSE);
SetLogEnable(INFO, TRUE);
RV.InitSeed(RV'instance_name);
ID := GetAlertLogID("ID", ALERTLOG_BASE_ID);
TS_TA := GetAlertLogID("TestSequence_TestArray", ALERTLOG_BASE_ID);
TS_TC := GetAlertLogID("TestSequence_TestChar", ALERTLOG_BASE_ID);
TS_TWC := GetAlertLogID("TestSequence_TestWChar", ALERTLOG_BASE_ID);
TS_TLL := GetAlertLogID("TestSequence_TestLongLong", ALERTLOG_BASE_ID);
TS_TLD := GetAlertLogID("TestSequence_TestLongDouble", ALERTLOG_BASE_ID);
TM := GetAlertLogID("TestMap", ALERTLOG_BASE_ID);
TE := GetAlertLogID("TestEnum", ALERTLOG_BASE_ID);
TU := GetAlertLogID("TestUnion", ALERTLOG_BASE_ID);
TB := GetAlertLogID("TestBitmask", ALERTLOG_BASE_ID);
TS := GetAlertLogID("TestString", ALERTLOG_BASE_ID);
Log("Setting Data in Writer Side", INFO);
start_w <= '0';
get_data_r <= '0';
-- Static
id_in <= RV.RandSlv(id_in'length);
TestEnum_in <= RV.RandSlv(TestEnum_in'length);
TestUnion_valid_in <= '1';
TestUnion_d_in <= (others => '0');
TestUnion_LongU_in <= RV.RandSlv(TestUnion_LongU_in'length);
TestUnion_OctetU_in <= RV.RandSlv(TestUnion_OctetU_in'length);
TestBitmask_in <= RV.RandSlv(TestBitmask_in'length);
-- Memory
for i in 0 to 1 loop
TestSequence_len_in <= int(2,TestSequence_len_in'length);
TestSequence_addr_in <= int(i,TestSequence_addr_in'length);
TestSequence_TestChar_w_in <= RV.RandSlv(TestSequence_TestChar_w_in'length);
TestSequence_TestWChar_w_in <= RV.RandSlv(TestSequence_TestWChar_w_in'length);
TestSequence_TestLongLong_w_in <= RV.RandSlv(TestSequence_TestLongLong_w_in'length);
TestSequence_TestLongDouble_w_in <= RV.RandSlv(TestSequence_TestLongDouble_w_in'length);
TestSequence_TestLongDouble_valid_w_in <= RV.RandSlv(1)(1);
for j in 0 to 4 loop
TestSequence_TestArray_addr_in <= int(j,TestSequence_TestArray_addr_in'length);
TestSequence_TestArray_w_in <= RV.RandSlv(TestSequence_TestArray_w_in'length);
wait_on_sig(TestSequence_TestArray_ready_in);
TestSequence_TestArray_wen_in <= '1';
wait for TEST_CLOCK_PERIOD;
TestSequence_TestArray_wen_in <= '0';
end loop;
wait_on_sig(TestSequence_ready_in);
TestSequence_wen_in <= '1';
wait for TEST_CLOCK_PERIOD;
TestSequence_wen_in <= '0';
end loop;
for i in 0 to 0 loop
TestMap_len_in <= int(1,TestMap_len_in'length);
TestMap_addr_in <= int(i,TestMap_addr_in'length);
TestMap_key_w_in <= RV.RandSlv(TestMap_key_w_in'length);
TestMap_value_w_in <= RV.RandSlv(TestMap_value_w_in'length);
wait_on_sig(TestMap_ready_in);
TestMap_wen_in <= '1';
wait for TEST_CLOCK_PERIOD;
TestMap_wen_in <= '0';
end loop;
for i in 0 to 9 loop
TestString_len_in <= int(10,TestString_len_in'length);
TestString_addr_in <= int(i,TestString_addr_in'length);
TestString_w_in <= RV.RandSlv(TestString_w_in'length);
wait_on_sig(TestString_ready_in);
TestString_wen_in <= '1';
wait for TEST_CLOCK_PERIOD;
TestString_wen_in <= '0';
end loop;
Log("Initiate Writer->Reader Transfer", INFO);
start_w <= '1';
get_data_r <= '1';
wait for TEST_CLOCK_PERIOD;
start_w <= '0';
get_data_r <= '0';
Log("Wait until Transfer done", INFO);
wait_on_sig(encode_done);
wait_on_sig(valid_r);
Log("Compare Writer and Reader Side", INFO);
AffirmIfEqual(ID, id_out, id_in);
AffirmIfEqual(TE, TestEnum_out,TestEnum_in);
AffirmIfEqual(TU, TestUnion_valid_out, TestUnion_valid_in);
if (TestUnion_valid_in = '1') then
AffirmIfEqual(TU, TestUnion_d_out, TestUnion_d_in);
--AffirmIfEqual(TU, TestUnion_LongU_out, TestUnion_LongU_in);
AffirmIfEqual(TU, TestUnion_OctetU_out, TestUnion_OctetU_in);
end if;
AffirmIfEqual(TB, TestBitmask_out, TestBitmask_in);
AffirmIfEqual(TestSequence_len_out,TestSequence_len_in);
for i in 0 to to_integer(unsigned(TestSequence_len_in)) loop
TestSequence_addr_out <= int(i,TestSequence_addr_out'length);
TestSequence_addr_in <= int(i,TestSequence_addr_in'length);
wait_on_sig(TestSequence_ready_out);
wait_on_sig(TestSequence_ready_in);
TestSequence_ren_out <= '1';
TestSequence_ren_in <= '1';
wait for TEST_CLOCK_PERIOD;
TestSequence_ren_out <= '0';
TestSequence_ren_in <= '0';
wait_on_sig(TestSequence_valid_out);
wait_on_sig(TestSequence_valid_in);
AffirmIfEqual(TS_TC, TestSequence_TestChar_out, TestSequence_TestChar_r_in);
AffirmIfEqual(TS_TWC, TestSequence_TestWChar_out, TestSequence_TestWChar_r_in);
AffirmIfEqual(TS_TLL, TestSequence_TestLongLong_out, TestSequence_TestLongLong_r_in);
AffirmIfEqual(TS_TLD, TestSequence_TestLongDouble_valid_out, TestSequence_TestLongDouble_valid_r_in);
if (TestSequence_TestLongDouble_valid_r_in = '1') then
AffirmIfEqual(TS_TLD, TestSequence_TestLongDouble_out, TestSequence_TestLongDouble_r_in);
end if;
for j in 0 to 4 loop
TestSequence_TestArray_addr_out <= int(j,TestSequence_TestArray_addr_out'length);
TestSequence_TestArray_addr_in <= int(j,TestSequence_TestArray_addr_in'length);
wait_on_sig(TestSequence_TestArray_ready_out);
wait_on_sig(TestSequence_TestArray_ready_in);
TestSequence_TestArray_ren_out <= '1';
TestSequence_TestArray_ren_in <= '1';
wait for TEST_CLOCK_PERIOD;
TestSequence_TestArray_ren_out <= '0';
TestSequence_TestArray_ren_in <= '0';
wait_on_sig(TestSequence_TestArray_valid_out);
wait_on_sig(TestSequence_TestArray_valid_in);
AffirmIfEqual(TS_TA, TestSequence_TestArray_out, TestSequence_TestArray_r_in);
TestSequence_TestArray_ack_out <= '1';
TestSequence_TestArray_ack_in <= '1';
wait for TEST_CLOCK_PERIOD;
TestSequence_TestArray_ack_out <= '0';
TestSequence_TestArray_ack_in <= '0';
end loop;
TestSequence_ack_out <= '1';
TestSequence_ack_in <= '1';
wait for TEST_CLOCK_PERIOD;
TestSequence_ack_out <= '0';
TestSequence_ack_in <= '0';
end loop;
AffirmIfEqual(TestMap_len_out, TestMap_len_in);
for i in 0 to to_integer(unsigned(TestMap_len_in)) loop
TestMap_addr_out <= int(i,TestMap_addr_out'length);
TestMap_addr_in <= int(i,TestMap_addr_in'length);
wait_on_sig(TestMap_ready_out);
wait_on_sig(TestMap_ready_in);
TestMap_ren_out <= '1';
TestMap_ren_in <= '1';
wait for TEST_CLOCK_PERIOD;
TestMap_ren_out <= '0';
TestMap_ren_in <= '0';
wait_on_sig(TestMap_valid_out);
wait_on_sig(TestMap_valid_in);
AffirmIfEqual(TM, TestMap_key_out, TestMap_key_r_in);
AffirmIfEqual(TM, TestMap_value_out, TestMap_value_r_in);
TestMap_ack_out <= '1';
TestMap_ack_in <= '1';
wait for TEST_CLOCK_PERIOD;
TestMap_ack_out <= '0';
TestMap_ack_in <= '0';
end loop;
AffirmIfEqual(TestString_len_out, TestString_len_in);
for i in 0 to to_integer(unsigned(TestString_len_in)) loop
TestString_addr_out <= int(i,TestString_addr_out'length);
TestString_addr_in <= int(i,TestString_addr_in'length);
wait_on_sig(TestString_ready_out);
wait_on_sig(TestString_ready_in);
TestString_ren_out <= '1';
TestString_ren_in <= '1';
wait for TEST_CLOCK_PERIOD;
TestString_ren_out <= '0';
TestString_ren_in <= '0';
wait_on_sig(TestString_valid_out);
wait_on_sig(TestString_valid_in);
AffirmIfEqual(TS, TestString_out, TestString_r_in);
TestString_ack_out <= '1';
TestString_ack_in <= '1';
wait for TEST_CLOCK_PERIOD;
TestString_ack_out <= '0';
TestString_ack_in <= '0';
end loop;
TranscriptOpen(RESULTS_FILE, APPEND_MODE);
SetTranscriptMirror;
ReportAlerts;
TranscriptClose;
std.env.stop;
wait;
end process;
clock_prc : process
begin
clk <= '0';
wait for TEST_CLOCK_PERIOD/2;
clk <= '1';
wait for TEST_CLOCK_PERIOD/2;
end process;
alert_prc : process(all)
begin
if rising_edge(clk) then
alertif(decode_error = '1', "The Reader signals a DECODE Error", ERROR);
end if;
end process;
watchdog : process
begin
wait for 1 ms;
Alert("Test timeout", FAILURE);
std.env.stop;
end process;
end architecture;

106
src/Tests/Type2_reader_wrapper.vhd
View File

@ -85,10 +85,12 @@ entity Type2_reader_wrapper is
TestSequence_ready : out std_logic;
TestSequence_ren : in std_logic;
TestSequence_valid : out std_logic;
TestSequence_ack : in std_logic;
TestSequence_TestArray_addr : in std_logic_vector(TESTSEQUENCE_TESTARRAY_ADDR_WIDTH-1 downto 0);
TestSequence_TestArray_ready : out std_logic;
TestSequence_TestArray_ren : in std_logic;
TestSequence_TestArray_valid : out std_logic;
TestSequence_TestArray_ack : in std_logic;
TestSequence_TestArray : out std_logic_vector(CDR_OCTET_WIDTH-1 downto 0);
TestSequence_TestChar : out std_logic_vector(CDR_CHAR_WIDTH-1 downto 0);
TestSequence_TestWChar : out std_logic_vector(CDR_WCHAR_WIDTH-1 downto 0);
@ -100,6 +102,7 @@ entity Type2_reader_wrapper is
TestMap_ready : out std_logic;
TestMap_ren : in std_logic;
TestMap_valid : out std_logic;
TestMap_ack : in std_logic;
TestMap_key : out std_logic_vector(CDR_OCTET_WIDTH-1 downto 0);
TestMap_value : out std_logic_vector(CDR_SHORT_WIDTH-1 downto 0);
TestEnum : out std_logic_vector(TESTENUM_WIDTH-1 downto 0);
@ -113,6 +116,7 @@ entity Type2_reader_wrapper is
TestString_ready : out std_logic;
TestString_ren : in std_logic;
TestString_valid : out std_logic;
TestString_ack : in std_logic;
TestString : out std_logic_vector(CDR_CHAR_WIDTH-1 downto 0);
valid : out std_logic
);
@ -189,7 +193,7 @@ architecture arch of Type2_reader_wrapper is
signal TestMap_mem_read, TestMap_mem_ready_in, TestMap_mem_ready_out, TestMap_mem_valid_in, TestMap_mem_valid_out : std_logic := '0';
signal TestMap_mem_data_in, TestMap_mem_data_out : std_logic_vector(CDR_OCTET_WIDTH+CDR_SHORT_WIDTH-1 downto 0) := (others => '0');
-- TestString_mem SIGNALS
signal TestString_mem_addr : std_logic_vector(TESTMAP_ADDR_WIDTH-1 downto 0) := (others => '0');
signal TestString_mem_addr : std_logic_vector(TESTSTRING_ADDR_WIDTH-1 downto 0) := (others => '0');
signal TestString_mem_read, TestString_mem_ready_in, TestString_mem_ready_out, TestString_mem_valid_in, TestString_mem_valid_out : std_logic := '0';
signal TestString_mem_data_in, TestString_mem_data_out : std_logic_vector(CDR_CHAR_WIDTH-1 downto 0) := (others => '0');
-- ###GENERATED END###
@ -197,8 +201,8 @@ architecture arch of Type2_reader_wrapper is
--*****ALIAS DECLARATION*****
alias representation_id : std_logic_vector(PAYLOAD_REPRESENTATION_ID_WIDTH-1 downto 0) is data_in_dds(WORD_WIDTH-1 downto WORD_WIDTH-PAYLOAD_REPRESENTATION_ID_WIDTH);
alias representation_options : std_logic_vector(PAYLOAD_REPRESENTATION_ID_WIDTH-1 downto 0) is data_in_dds(PAYLOAD_REPRESENTATION_OPTIONS_WIDTH-1 downto 0);
alias parameter_id : std_logic_vector(PARAMETER_ID_WIDTH-1 downto 0) is data_in_dds(WORD_WIDTH-1 downto WORD_WIDTH-PARAMETER_ID_WIDTH);
alias parameter_length : std_logic_vector(PARAMETER_LENGTH_WIDTH-1 downto 0) is data_in_dds(PARAMETER_LENGTH_WIDTH-1 downto 0);
alias parameter_id : std_logic_vector(PARAMETER_ID_WIDTH-1 downto 0) is data_in_latch(WORD_WIDTH-1 downto WORD_WIDTH-PARAMETER_ID_WIDTH);
alias parameter_length : std_logic_vector(PARAMETER_LENGTH_WIDTH-1 downto 0) is data_in_latch(PARAMETER_LENGTH_WIDTH-1 downto 0);
begin
@ -507,24 +511,24 @@ begin
TestSequence_TestChar_mem_addr <= TestSequence_addr;
TestSequence_TestChar_mem_read <= TestSequence_ren;
TestSequence_TestChar_mem_valid_in <= TestSequence_ren;
TestSequence_TestChar_mem_ready_out <= TestSequence_ren;
TestSequence_TestChar_mem_ready_out <= TestSequence_ack;
TestSequence_TestWChar_mem_addr <= TestSequence_addr;
TestSequence_TestWChar_mem_read <= TestSequence_ren;
TestSequence_TestWChar_mem_valid_in <= TestSequence_ren;
TestSequence_TestWChar_mem_ready_out <= TestSequence_ren;
TestSequence_TestWChar_mem_ready_out <= TestSequence_ack;
TestSequence_TestLongLong_mem_addr <= TestSequence_addr;
TestSequence_TestLongLong_mem_read <= TestSequence_ren;
TestSequence_TestLongLong_mem_valid_in <= TestSequence_ren;
TestSequence_TestLongLong_mem_ready_out <= TestSequence_ren;
TestSequence_TestLongLong_mem_ready_out <= TestSequence_ack;
TestSequence_TestLongDouble_mem_addr <= TestSequence_addr;
TestSequence_TestLongDouble_mem_read <= TestSequence_ren;
TestSequence_TestLongDouble_mem_valid_in <= TestSequence_ren;
TestSequence_TestLongDouble_mem_ready_out <= TestSequence_ren;
TestSequence_TestLongDouble_mem_ready_out <= TestSequence_ack;
TestSequence_TestArray_ready <= TestSequence_TestArray_mem_ready_in(to_integer(unsigned(TestSequence_addr)));
TestSequence_TestArray_mem_addr(to_integer(unsigned(TestSequence_addr))) <= TestSequence_TestArray_addr;
TestSequence_TestArray_mem_read(to_integer(unsigned(TestSequence_addr))) <= TestSequence_TestArray_ren;
TestSequence_TestArray_mem_valid_in(to_integer(unsigned(TestSequence_addr))) <= TestSequence_TestArray_ren;
TestSequence_TestArray_mem_ready_out <= (others => TestSequence_TestArray_ren);
TestSequence_TestArray_mem_ready_out <= (others => TestSequence_TestArray_ack);
-- Latch Address for output
if (TestSequence_TestArray_ren = '1') then
TestSequence_addr_latch_next <= TestSequence_addr;
@ -533,12 +537,12 @@ begin
TestMap_mem_addr <= TestMap_addr;
TestMap_mem_read <= TestMap_ren;
TestMap_mem_valid_in <= TestMap_ren;
TestMap_mem_ready_out <= TestMap_ren;
TestMap_mem_ready_out <= TestMap_ack;
TestString_ready <= TestString_mem_ready_in;
TestString_mem_addr <= TestString_addr;
TestString_mem_read <= TestString_ren;
TestString_mem_valid_in <= TestString_ren;
TestString_mem_ready_out <= TestString_ren;
TestString_mem_ready_out <= TestString_ack;
end if;
when GET_PAYLOAD_HEADER =>
-- TODO: Latch Offset from Options Field?
@ -550,7 +554,7 @@ begin
when CDR_BE =>
endian_flag_next <= '0';
stage_next <= FETCH;
decode_stage_next <= GET_ID;
decode_stage_next <= GET_ID;
-- Alignment Reset
align_offset_next <= (others => '0');
-- Initial Fetch
@ -601,7 +605,7 @@ begin
stage_next <= IDLE;
-- If no Decode Error, mark output as valid
if (decode_error_latch /= '0') then
if (decode_error_latch = '0') then
valid_latch_next <= '1';
end if;
@ -656,12 +660,13 @@ begin
TestSequence_TestArray_mem_valid_in(TestSequence_cnt) <= '1';
-- Memory Operation Guard
if (TestSequence_TestArray_mem_ready_in(TestSequence_cnt) = '1') then
align_offset_next <= align_offset + 1;
TestSequence_TestArray_cnt_next <= TestSequence_TestArray_cnt + 1;
align_offset_next <= align_offset + 1;
-- All Elements processed
if (TestSequence_TestArray_cnt = TESTSEQUENCE_TESTARRAY_MAX_DEPTH-1) then
decode_stage_next <= GET_TESTSEQUENCE_TESTCHAR;
else
TestSequence_TestArray_cnt_next <= TestSequence_TestArray_cnt + 1;
end if;
-- DES: Needed for ALIGN_1
@ -872,10 +877,10 @@ begin
-- All Elements processed
if (TestMap_cnt = TestMap_len_latch-1) then
-- Next Member
decode_stage_next <= GET_TESTENUM;
decode_stage_next <= GET_TESTENUM;
else
TestMap_cnt_next <= TestMap_cnt + 1;
decode_stage_next <= GET_TESTMAP_KEY;
decode_stage_next <= GET_TESTMAP_KEY;
end if;
when GET_TESTENUM =>
-- ALIGN GUARD
@ -998,7 +1003,6 @@ begin
-- Memory Operation Guard
if (TestString_mem_ready_in = '1') then
align_offset_next <= align_offset + 1;
TestString_cnt_next <= TestString_cnt + 1;
-- Need to fetch next Word
if(align_offset(1 downto 0) = "11") then
@ -1009,18 +1013,45 @@ begin
if (TestString_cnt = TestString_len_latch-1) then
-- DONE
stage_next <= SKIP_PAYLOAD;
else
TestString_cnt_next <= TestString_cnt + 1;
end if;
end if;
end if;
when GET_OPTIONAL_HEADER =>
case (cnt) is
-- Optional Member Header
when 0 =>
-- Extended Parameter Header
if (endian_swap(endian_flag,parameter_id) = PID_EXTENDED) then
-- ALIGN GUARD
if (not check_align(align_offset, ALIGN_4)) then
target_align_next <= ALIGN_4;
stage_next <= ALIGN_STREAM;
else
case (cnt) is
-- Optional Member Header
when 0 =>
-- Extended Parameter Header
if (endian_swap(endian_flag,parameter_id) = PID_EXTENDED) then
cnt_next <= cnt + 1;
stage_next <= FETCH;
else
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
if(endian_swap(endian_flag,parameter_length) = (parameter_length'reverse_range => '0')) then
optional_next <= '0';
else
optional_next <= '1';
end if;
end if;
-- eMemberHeader
when 1 =>
-- Ignore Parameter ID
cnt_next <= cnt + 1;
stage_next <= FETCH;
else
-- Llength
when 2 =>
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
@ -1028,34 +1059,15 @@ begin
align_offset_next <= (others => '0');
-- Optional omitted
if(endian_swap(endian_flag,parameter_length) = (parameter_length'reverse_range => '0')) then
if(endian_swap(endian_flag, data_in_dds) = (data_in_dds'reverse_range => '0')) then
optional_next <= '0';
else
optional_next <= '1';
end if;
end if;
-- eMemberHeader
when 1 =>
-- Ignore Parameter ID
cnt_next <= cnt + 1;
stage_next <= FETCH;
-- Llength
when 2 =>
stage_next <= FETCH;
decode_stage_next <= return_stage;
cnt_next <= 0;
-- Alignment Reset
align_offset_next <= (others => '0');
-- Optional omitted
if(endian_swap(endian_flag, data_in_dds) = (data_in_dds'reverse_range => '0')) then
optional_next <= '0';
else
optional_next <= '1';
end if;
when others =>
null;
end case;
when others =>
null;
end case;
end if;
when others =>
null;
end case;

94
src/Tests/Type2_writer_wrapper.vhd
View File

@ -56,11 +56,13 @@ entity Type2_writer_wrapper is
TestSequence_ren : in std_logic;
TestSequence_wen : in std_logic;
TestSequence_valid : out std_logic;
TestSequence_ack : in std_logic;
TestSequence_TestArray_addr : in std_logic_vector(TESTSEQUENCE_TESTARRAY_ADDR_WIDTH-1 downto 0);
TestSequence_TestArray_ready : out std_logic;
TestSequence_TestArray_ren : in std_logic;
TestSequence_TestArray_wen : in std_logic;
TestSequence_TestArray_valid : out std_logic;
TestSequence_TestArray_ack : in std_logic;
TestSequence_TestArray_r : out std_logic_vector(CDR_OCTET_WIDTH-1 downto 0);
TestSequence_TestArray_w : in std_logic_vector(CDR_OCTET_WIDTH-1 downto 0);
TestSequence_TestChar_r : out std_logic_vector(CDR_CHAR_WIDTH-1 downto 0);
@ -79,6 +81,7 @@ entity Type2_writer_wrapper is
TestMap_ren : in std_logic;
TestMap_wen : in std_logic;
TestMap_valid : out std_logic;
TestMap_ack : in std_logic;
TestMap_key_r : out std_logic_vector(CDR_OCTET_WIDTH-1 downto 0);
TestMap_key_w : in std_logic_vector(CDR_OCTET_WIDTH-1 downto 0);
TestMap_value_r : out std_logic_vector(CDR_SHORT_WIDTH-1 downto 0);
@ -95,6 +98,7 @@ entity Type2_writer_wrapper is
TestString_ren : in std_logic;
TestString_wen : in std_logic;
TestString_valid : out std_logic;
TestString_ack : in std_logic;
TestString_r : out std_logic_vector(CDR_CHAR_WIDTH-1 downto 0);
TestString_w : in std_logic_vector(CDR_CHAR_WIDTH-1 downto 0)
);
@ -152,17 +156,11 @@ architecture arch of Type2_writer_wrapper is
signal TestMap_mem_read, TestMap_mem_ready_in, TestMap_mem_ready_out, TestMap_mem_valid_in, TestMap_mem_valid_out : std_logic := '0';
signal TestMap_mem_data_in, TestMap_mem_data_out : std_logic_vector(CDR_OCTET_WIDTH+CDR_SHORT_WIDTH-1 downto 0) := (others => '0');
-- TestString_mem SIGNALS
signal TestString_mem_addr : std_logic_vector(TESTMAP_ADDR_WIDTH-1 downto 0) := (others => '0');
signal TestString_mem_addr : std_logic_vector(TESTSTRING_ADDR_WIDTH-1 downto 0) := (others => '0');
signal TestString_mem_read, TestString_mem_ready_in, TestString_mem_ready_out, TestString_mem_valid_in, TestString_mem_valid_out : std_logic := '0';
signal TestString_mem_data_in, TestString_mem_data_out : std_logic_vector(CDR_CHAR_WIDTH-1 downto 0) := (others => '0');
-- ###GENERATED END###
--*****ALIAS DECLARATION*****
alias representation_id : std_logic_vector(PAYLOAD_REPRESENTATION_ID_WIDTH-1 downto 0) is data_in_dds(WORD_WIDTH-1 downto WORD_WIDTH-PAYLOAD_REPRESENTATION_ID_WIDTH);
alias representation_options : std_logic_vector(PAYLOAD_REPRESENTATION_ID_WIDTH-1 downto 0) is data_in_dds(PAYLOAD_REPRESENTATION_OPTIONS_WIDTH-1 downto 0);
alias parameter_id : std_logic_vector(PARAMETER_ID_WIDTH-1 downto 0) is data_in_dds(WORD_WIDTH-1 downto WORD_WIDTH-PARAMETER_ID_WIDTH);
alias parameter_length : std_logic_vector(PARAMETER_LENGTH_WIDTH-1 downto 0) is data_in_dds(PARAMETER_LENGTH_WIDTH-1 downto 0);
begin
@ -441,24 +439,24 @@ begin
TestSequence_TestChar_mem_addr <= TestSequence_addr;
TestSequence_TestChar_mem_read <= TestSequence_ren;
TestSequence_TestChar_mem_valid_in <= TestSequence_ren or TestSequence_wen;
TestSequence_TestChar_mem_ready_out <= TestSequence_ren;
TestSequence_TestChar_mem_ready_out <= TestSequence_ack;
TestSequence_TestWChar_mem_addr <= TestSequence_addr;
TestSequence_TestWChar_mem_read <= TestSequence_ren;
TestSequence_TestWChar_mem_valid_in <= TestSequence_ren or TestSequence_wen;
TestSequence_TestWChar_mem_ready_out <= TestSequence_ren;
TestSequence_TestWChar_mem_ready_out <= TestSequence_ack;
TestSequence_TestLongLong_mem_addr <= TestSequence_addr;
TestSequence_TestLongLong_mem_read <= TestSequence_ren;
TestSequence_TestLongLong_mem_valid_in <= TestSequence_ren or TestSequence_wen;
TestSequence_TestLongLong_mem_ready_out <= TestSequence_ren;
TestSequence_TestLongLong_mem_ready_out <= TestSequence_ack;
TestSequence_TestLongDouble_mem_addr <= TestSequence_addr;
TestSequence_TestLongDouble_mem_read <= TestSequence_ren;
TestSequence_TestLongDouble_mem_valid_in <= TestSequence_ren or TestSequence_wen;
TestSequence_TestLongDouble_mem_ready_out <= TestSequence_ren;
TestSequence_TestLongDouble_mem_ready_out <= TestSequence_ack;
TestSequence_TestArray_ready <= TestSequence_TestArray_mem_ready_in(to_integer(unsigned(TestSequence_addr)));
TestSequence_TestArray_mem_addr(to_integer(unsigned(TestSequence_addr))) <= TestSequence_TestArray_addr;
TestSequence_TestArray_mem_read(to_integer(unsigned(TestSequence_addr))) <= TestSequence_TestArray_ren;
TestSequence_TestArray_mem_valid_in(to_integer(unsigned(TestSequence_addr))) <= TestSequence_TestArray_ren or TestSequence_TestArray_wen;
TestSequence_TestArray_mem_ready_out <= (others => TestSequence_TestArray_ren);
TestSequence_TestArray_mem_ready_out <= (others => TestSequence_TestArray_ack);
-- Latch Address for output
if (TestSequence_TestArray_ren = '1') then
TestSequence_addr_latch_next <= TestSequence_addr;
@ -467,12 +465,12 @@ begin
TestMap_mem_addr <= TestMap_addr;
TestMap_mem_read <= TestMap_ren;
TestMap_mem_valid_in <= TestMap_ren or TestMap_wen;
TestMap_mem_ready_out <= TestMap_ren;
TestMap_mem_ready_out <= TestMap_ack;
TestString_ready <= TestString_mem_ready_in;
TestString_mem_addr <= TestString_addr;
TestString_mem_read <= TestString_ren;
TestString_mem_valid_in <= TestString_ren or TestString_wen;
TestString_mem_ready_out <= TestString_ren;
TestString_mem_ready_out <= TestString_ack;
end if;
when WRITE_PAYLOAD_HEADER =>
data_out_latch_next <= CDR_BE & x"0000";
@ -504,7 +502,7 @@ begin
end if;
when ALIGN_STREAM =>
-- Target Stream Alignment reached
if (check_align(align_offset, target_align) = TRUE) then
if (check_align(align_offset, target_align)) then
-- DONE
stage_next <= ENCODE_PAYLOAD;
else
@ -520,7 +518,7 @@ begin
case (encode_stage) is
when WRITE_ID =>
-- ALIGN GUARD
if (check_align(align_offset, ALIGN_4) = FALSE) then
if (not check_align(align_offset, ALIGN_4)) then
target_align_next <= ALIGN_4;
stage_next <= ALIGN_STREAM;
else
@ -532,11 +530,11 @@ begin
end if;
when WRITE_TESTSEQUENCE_LENGTH =>
-- ALIGN GUARD
if (check_align(align_offset, ALIGN_4) = FALSE) then
if (not check_align(align_offset, ALIGN_4)) then
target_align_next <= ALIGN_4;
stage_next <= ALIGN_STREAM;
else
data_out_latch_next <= TestSequence_len;
data_out_latch_next <= std_logic_vector(resize(unsigned(TestSequence_len),WORD_WIDTH));
align_offset_next <= align_offset + 4;
stage_next <= PUSH;
@ -545,7 +543,7 @@ begin
-- Next Member
encode_stage_next <= WRITE_TESTMAP_LENGTH;
else
encode_stage_next <= WRITE_TESTSEQUENCE_TESTARRAY;
encode_stage_next <= WRITE_TESTSEQUENCE_TESTARRAY;
cnt_next <= 0;
TestSequence_cnt_next <= 0;
-- DES: For array types the _cnt has to be initialized in the previous member stage
@ -554,7 +552,7 @@ begin
end if;
when WRITE_TESTSEQUENCE_TESTARRAY =>
-- ALIGN GUARD
if (check_align(align_offset, ALIGN_1) = FALSE) then
if (not check_align(align_offset, ALIGN_1)) then
target_align_next <= ALIGN_1;
stage_next <= ALIGN_STREAM;
else
@ -574,14 +572,15 @@ begin
-- Memory Operation Guard
if (TestSequence_TestArray_mem_valid_out(TestSequence_cnt) = '1') then
data_out_latch_next <= write_sub_vector(data_out_latch, TestSequence_TestArray_mem_data_out(TestSequence_cnt), to_integer(align_offset(1 downto 0)), TRUE);
align_offset_next <= align_offset + 1;
TestSequence_TestArray_cnt_next <= TestSequence_TestArray_cnt + 1;
cnt_next <= 0;
align_offset_next <= align_offset + 1;
cnt_next <= 0;
-- All Elements processed
if (TestSequence_TestArray_cnt = TESTSEQUENCE_TESTARRAY_MAX_DEPTH-1) then
encode_stage_next <= WRITE_TESTSEQUENCE_TESTCHAR;
cnt_next <= 0;
else
TestSequence_TestArray_cnt_next <= TestSequence_TestArray_cnt + 1;
end if;
-- DES: Needed for ALIGN_1
@ -595,7 +594,7 @@ begin
end if;
when WRITE_TESTSEQUENCE_TESTCHAR =>
-- ALIGN GUARD
if (check_align(align_offset, ALIGN_1) = FALSE) then
if (not check_align(align_offset, ALIGN_1)) then
target_align_next <= ALIGN_1;
stage_next <= ALIGN_STREAM;
else
@ -631,7 +630,7 @@ begin
end if;
when WRITE_TESTSEQUENCE_TESTWCHAR =>
-- ALIGN GUARD
if (check_align(align_offset, ALIGN_2) = FALSE) then
if (not check_align(align_offset, ALIGN_2)) then
target_align_next <= ALIGN_2;
stage_next <= ALIGN_STREAM;
else
@ -667,7 +666,7 @@ begin
end if;
when WRITE_TESTSEQUENCE_TESTLONGLONG =>
-- ALIGN GUARD
if (check_align(align_offset, ALIGN_8) = FALSE) then
if (not check_align(align_offset, ALIGN_8)) then
target_align_next <= ALIGN_8;
stage_next <= ALIGN_STREAM;
else
@ -705,7 +704,7 @@ begin
end if;
when WRITE_TESTSEQUENCE_TESTLONGDOUBLE =>
-- ALIGN GUARD
if (check_align(align_offset, ALIGN_4) = FALSE) then
if (not check_align(align_offset, ALIGN_4)) then
target_align_next <= ALIGN_4;
stage_next <= ALIGN_STREAM;
else
@ -745,7 +744,7 @@ begin
when 2 =>
-- Memory Operation Guard
if (TestSequence_TestLongDouble_mem_valid_out = '1') then
data_out_latch_next <= get_sub_vector(TestSequence_TestLongDouble_mem_data_out, 0, WORD_WIDTH, TRUE);
data_out_latch_next <= get_sub_vector(TestSequence_TestLongDouble_mem_data_out(CDR_LONG_DOUBLE_WIDTH-1 downto 0), 0, WORD_WIDTH, TRUE);
stage_next <= PUSH;
cnt_next <= cnt + 1;
end if;
@ -753,7 +752,7 @@ begin
when 3 =>
-- Memory Operation Guard
if (TestSequence_TestLongDouble_mem_valid_out = '1') then
data_out_latch_next <= get_sub_vector(TestSequence_TestLongDouble_mem_data_out, 1, WORD_WIDTH, TRUE);
data_out_latch_next <= get_sub_vector(TestSequence_TestLongDouble_mem_data_out(CDR_LONG_DOUBLE_WIDTH-1 downto 0), 1, WORD_WIDTH, TRUE);
stage_next <= PUSH;
cnt_next <= cnt + 1;
end if;
@ -761,7 +760,7 @@ begin
when 4 =>
-- Memory Operation Guard
if (TestSequence_TestLongDouble_mem_valid_out = '1') then
data_out_latch_next <= get_sub_vector(TestSequence_TestLongDouble_mem_data_out, 2, WORD_WIDTH, TRUE);
data_out_latch_next <= get_sub_vector(TestSequence_TestLongDouble_mem_data_out(CDR_LONG_DOUBLE_WIDTH-1 downto 0), 2, WORD_WIDTH, TRUE);
stage_next <= PUSH;
cnt_next <= cnt + 1;
end if;
@ -770,10 +769,10 @@ begin
TestSequence_TestLongDouble_mem_ready_out <= '1';
-- Memory Operation Guard
if (TestSequence_TestLongDouble_mem_valid_out = '1') then
data_out_latch_next <= get_sub_vector(TestSequence_TestLongDouble_mem_data_out, 3, WORD_WIDTH, TRUE);
data_out_latch_next <= get_sub_vector(TestSequence_TestLongDouble_mem_data_out(CDR_LONG_DOUBLE_WIDTH-1 downto 0), 3, WORD_WIDTH, TRUE);
stage_next <= PUSH;
align_offset_next <= align_offset + 16;
encode_stage_next <= TESTSEQUENCE_MEMBER_END;
encode_stage_next <= TESTSEQUENCE_MEMBER_END;
cnt_next <= 0;
end if;
when others =>
@ -793,11 +792,11 @@ begin
end if;
when WRITE_TESTMAP_LENGTH =>
-- ALIGN GUARD
if (check_align(align_offset, ALIGN_4) = FALSE) then
if (not check_align(align_offset, ALIGN_4)) then
target_align_next <= ALIGN_4;
stage_next <= ALIGN_STREAM;
else
data_out_latch_next <= TestMap_len;
data_out_latch_next <= std_logic_vector(resize(unsigned(TestMap_len),WORD_WIDTH));
align_offset_next <= align_offset + 4;
stage_next <= PUSH;
@ -813,7 +812,7 @@ begin
end if;
when WRITE_TESTMAP_KEY =>
-- ALIGN GUARD
if (check_align(align_offset, ALIGN_1) = FALSE) then
if (not check_align(align_offset, ALIGN_1)) then
target_align_next <= ALIGN_1;
stage_next <= ALIGN_STREAM;
else
@ -847,7 +846,7 @@ begin
end if;
when WRITE_TESTMAP_VALUE =>
-- ALIGN GUARD
if (check_align(align_offset, ALIGN_2) = FALSE) then
if (not check_align(align_offset, ALIGN_2)) then
target_align_next <= ALIGN_2;
stage_next <= ALIGN_STREAM;
else
@ -878,7 +877,7 @@ begin
end if;
when WRITE_TESTENUM =>
-- ALIGN GUARD
if (check_align(align_offset, ALIGN_1) = FALSE) then
if (not check_align(align_offset, ALIGN_1)) then
target_align_next <= ALIGN_1;
stage_next <= ALIGN_STREAM;
else
@ -896,8 +895,8 @@ begin
end if;
when WRITE_TESTUNION_D =>
-- ALIGN GUARD
if (check_align(align_offset, ALIGN_1) = FALSE) then
target_align_next <= ALIGN_1;
if (not check_align(align_offset, ALIGN_4)) then
target_align_next <= ALIGN_4;
stage_next <= ALIGN_STREAM;
else
case (cnt) is
@ -925,7 +924,7 @@ begin
align_offset_next <= (others => '0');
stage_next <= PUSH;
-- WRITE Discriminator
when 2 =>
when 1 =>
data_out_latch_next <= write_sub_vector(data_out_latch, TestUnion_d, to_integer(align_offset(1 downto 0)), TRUE);
align_offset_next <= align_offset + 1;
@ -946,7 +945,7 @@ begin
end if;
when WRITE_TESTUNION_LONGU =>
-- ALIGN GUARD
if (check_align(align_offset, ALIGN_4) = FALSE) then
if (not check_align(align_offset, ALIGN_4)) then
target_align_next <= ALIGN_4;
stage_next <= ALIGN_STREAM;
else
@ -959,7 +958,7 @@ begin
end if;
when WRITE_TESTUNION_OCTETU =>
-- ALIGN GUARD
if (check_align(align_offset, ALIGN_1) = FALSE) then
if (not check_align(align_offset, ALIGN_1)) then
target_align_next <= ALIGN_1;
stage_next <= ALIGN_STREAM;
else
@ -976,7 +975,7 @@ begin
end if;
when WRITE_TESTBITMASK =>
-- ALIGN GUARD
if (check_align(align_offset, ALIGN_2) = FALSE) then
if (not check_align(align_offset, ALIGN_2)) then
target_align_next <= ALIGN_2;
stage_next <= ALIGN_STREAM;
else
@ -993,11 +992,11 @@ begin
end if;
when WRITE_TESTSTRING_LENGTH =>
-- ALIGN GUARD
if (check_align(align_offset, ALIGN_4) = FALSE) then
if (not check_align(align_offset, ALIGN_4)) then
target_align_next <= ALIGN_4;
stage_next <= ALIGN_STREAM;
else
data_out_latch_next <= TestString_len;
data_out_latch_next <= std_logic_vector(resize(unsigned(TestString_len),WORD_WIDTH));
align_offset_next <= align_offset + 4;
stage_next <= PUSH;
@ -1014,7 +1013,7 @@ begin
end if;
when WRITE_TESTSTRING =>
-- ALIGN GUARD
if (check_align(align_offset, ALIGN_1) = FALSE) then
if (not check_align(align_offset, ALIGN_1)) then
target_align_next <= ALIGN_1;
stage_next <= ALIGN_STREAM;
else
@ -1035,7 +1034,6 @@ begin
if (TestString_mem_valid_out = '1') then
data_out_latch_next <= write_sub_vector(data_out_latch, TestString_mem_data_out, to_integer(align_offset(1 downto 0)), TRUE);
align_offset_next <= align_offset + 1;
TestString_cnt_next <= TestString_cnt + 1;
cnt_next <= 0;
-- All Elements processed
@ -1044,6 +1042,8 @@ begin
stage_next <= PUSH;
finalize_payload_next <= '1';
encode_done <= '1';
else
TestString_cnt_next <= TestString_cnt + 1;
end if;
-- Need to fetch next Word

7
src/Tests/testbench.pro
View File

@ -81,6 +81,10 @@ analyze Level_0/L0_dds_reader_test4_arznriu.vhd
analyze Level_0/L0_dds_reader_test5_arzkriu.vhd
analyze Level_0/L0_dds_reader_test6_arzkriu.vhd
analyze Level_0/L0_dds_reader_test7_arzkriu.vhd
analyze Type2_package.vhd
analyze Type2_reader_wrapper.vhd
analyze Type2_writer_wrapper.vhd
analyze Level_1/L1_Type2_wrapper_test1.vhd
simulate L0_rtps_handler_test1
simulate L0_rtps_handler_test2
@ -142,4 +146,5 @@ simulate L0_dds_reader_test4_arzkriu
simulate L0_dds_reader_test4_arznriu
simulate L0_dds_reader_test5_arzkriu
simulate L0_dds_reader_test6_arzkriu
simulate L0_dds_reader_test7_arzkriu
simulate L0_dds_reader_test7_arzkriu
simulate L1_Type2_wrapper_test1

2
src/rtps_test_package.vhd
View File

@ -12,6 +12,8 @@ use work.rtps_config_package.all;
package rtps_test_package is
constant TEST_CLOCK_PERIOD : time := 50 ns;
-- File were the Test Results are stored
constant RESULTS_FILE : string := "./Test_Results.txt";