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Change Sample Memory Format

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The Sample Memory was changed to contain only the Instance Memory
Address instead of the whole Key Hash. This simplifies the B process and
reduces memory footprint.
The instance memory process was also updated to handle the conditional
fields defined in the previous commit.
This commit is contained in:
Greek 2021-01-17 21:01:15 +01:00
parent 7e84a15d54
commit f2826ddd20
3 changed files with 292 additions and 177 deletions
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36
src/REF.txt
View File

@ -343,30 +343,24 @@ READER
00| STATUS_INFO | {A/B} 00| STATUS_INFO | {A/B}
+-------------------------------------------------------------+ +-------------------------------------------------------------+
01| | 01| |
+ + + TIMESTAMP + {A}
02| | 02| |
+ KEY_HASH + {A} +-------------------------------------------------------------+
03| | 03| |
+ + + LIFESPAN_DEADLINE + {A}
04| | 04| |
+-------------------------------------------------------------+ +-------------------------------------------------------------+
05| | 05| PAYLOAD_ADDRESS | {A}
+ TIMESTAMP + {A}
06| |
+-------------------------------------------------------------+ +-------------------------------------------------------------+
07| | 06| INSTANCE_ADDRESS | {A}
+ LIFESPAN_DEADLINE + {A}
08| |
+-------------------------------------------------------------+ +-------------------------------------------------------------+
09| PAYLOAD_ADDRESS | {A} 07| DISPOSED_GENERATION_COUNT | {A} [only GENERATION_COUNTERS]
+-------------------------------------------------------------+ +-------------------------------------------------------------+
10| DISPOSED_GENERATION_COUNT | {A} [only GENERATION_COUNTERS] 08| NO_WRITERS_GENERATION_COUNT | {A} [only GENERATION_COUNTERS]
+-------------------------------------------------------------+ +-------------------------------------------------------------+
11| NO_WRITERS_GENERATION_COUNT | {A} [only GENERATION_COUNTERS] 09| PREV_ADDRESS | {A}
+-------------------------------------------------------------+ +-------------------------------------------------------------+
12| PREV_ADDRESS | {A} 10| NEXT_ADDRESS | {A/B}
+-------------------------------------------------------------+
13| NEXT_ADDRESS | {A/B}
+-------------------------------------------------------------+ +-------------------------------------------------------------+
@ -406,19 +400,19 @@ HISTORY CACHE INPUT
00| STATUS_INFO | 00| STATUS_INFO |
+-------------------------------------------------------------+ +-------------------------------------------------------------+
01| | 01| |
+ + + TIMESTAMP +
02| | 02| |
+ KEY_HASH + +-------------------------------------------------------------+
03| | 03| |
+ + + LIFESPAN_DEADLINE +
04| | 04| |
+-------------------------------------------------------------+ +-------------------------------------------------------------+
05| | 05| |
+ TIMESTAMP + + +
06| | 06| |
+-------------------------------------------------------------+ + KEY_HASH + [only if K Flag set]
07| | 07| |
+ LIFESPAN_DEADLINE + + +
08| | 08| |
+-------------------------------------------------------------+ +-------------------------------------------------------------+
09| ENDPOINT_POSITION | 09| ENDPOINT_POSITION |

397
src/history_cache.vhd
View File

@ -74,13 +74,13 @@ architecture arch of history_cache is
-- *SAMPLE MEMORY FRAME FORMAT* -- *SAMPLE MEMORY FRAME FORMAT*
constant SMF_STATUS_INFO_OFFSET : natural := 0; constant SMF_STATUS_INFO_OFFSET : natural := 0;
constant SMF_KEY_HASH_OFFSET : natural := 1; constant SMF_TIMESTAMP_OFFSET : natural := 1;
constant SMF_TIMESTAMP_OFFSET : natural := 5; constant SMF_LIFESPAN_DEADLINE_OFFSET : natural := 3;
constant SMF_LIFESPAN_DEADLINE_OFFSET : natural := 7; constant SMF_PAYLOAD_ADDR_OFFSET : natural := 5;
constant SMF_PAYLOAD_ADDR_OFFSET : natural := 9; constant SMF_INSTANCE_ADDR_OFFSET : natural := 6;
constant SMF_DISPOSED_GEN_CNT_OFFSET : natural := 10; constant SMF_DISPOSED_GEN_CNT_OFFSET : natural := 7;
constant SMF_NO_WRITERS_GEN_CNT_OFFSET : natural := 11; constant SMF_NO_WRITERS_GEN_CNT_OFFSET : natural := 8;
constant SMF_PREV_ADDR_OFFSET : natural := SMF_NO_WRITERS_GEN_CNT_OFFSET+1 when GENERATION_COUNTERS else SMF_NO_WRITERS_GEN_CNT_OFFSET+1; constant SMF_PREV_ADDR_OFFSET : natural := SMF_NO_WRITERS_GEN_CNT_OFFSET+1 when GENERATION_COUNTERS else SMF_INSTANCE_ADDR_OFFSET+1;
constant SMF_NEXT_ADDR_OFFSET : natural := SMF_PREV_ADDR_OFFSET+1; constant SMF_NEXT_ADDR_OFFSET : natural := SMF_PREV_ADDR_OFFSET+1;
-- *PAYLOAD MEMORY FRAME FORMAT* -- *PAYLOAD MEMORY FRAME FORMAT*
constant PMF_NEXT_ADDR_OFFSET : natural := 0; constant PMF_NEXT_ADDR_OFFSET : natural := 0;
@ -139,12 +139,6 @@ architecture arch of history_cache is
); );
--*****SIGNAL DECLARATION --*****SIGNAL DECLARATION
signal stage_a, stage_a_next : STAGE_TYPE := IDLE;
signal cnt_a, cnt_a_next : natural range TODO := 0;
signal empty_sample_slot, empty_sample_slot_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0');
signal empty_payload_slot, empty_payload_slot_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0');
signal next_sample, next_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sample_addr_a, sample_addr_a_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sample_addr_a, sample_addr_a_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sample_addr_b, sample_addr_b_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sample_addr_b, sample_addr_b_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sample_wen_a, sample_wen_b : std_logic := '0'; signal sample_wen_a, sample_wen_b : std_logic := '0';
@ -159,6 +153,18 @@ architecture arch of history_cache is
signal payload_read_data_a, payload_read_data_b : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); signal payload_read_data_a, payload_read_data_b : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal payload_write_data_a, payload_write_data_b : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); signal payload_write_data_a, payload_write_data_b : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal inst_addr_a, inst_addr_a_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0');
signal inst_addr_b, inst_addr_b_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0');
signal inst_wen_a, inst_wen_b : std_logic := '0';
signal inst_ren_a, inst_ren_b : std_logic := '0';
signal inst_read_data_a, inst_read_data_b : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal inst_write_data_a, inst_write_data_b : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal khg_valid_in, khg_ready_in, khg_last_word_in, khg_valid_out, khg_ready_out, khg_last_word_out : std_logic := '0';
signal khg_data_in, khg_data_out : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal stage_a, stage_a_next : STAGE_TYPE := IDLE;
signal cnt_a, cnt_a_next : natural range TODO := 0;
signal empty_sample_list_head, empty_sample_list_head_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); signal empty_sample_list_head, empty_sample_list_head_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0');
signal empty_sample_list_tail, empty_sample_list_tail_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); signal empty_sample_list_tail, empty_sample_list_tail_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0');
signal empty_payload_list_head, empty_payload_list_head_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); signal empty_payload_list_head, empty_payload_list_head_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0');
@ -172,19 +178,21 @@ architecture arch of history_cache is
signal sample_addr_latch_2, sample_addr_latch_2_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sample_addr_latch_2, sample_addr_latch_2_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ts_latch, ts_latch_next : TIME_TYPE := TIME_INVALID; signal ts_latch, ts_latch_next : TIME_TYPE := TIME_INVALID;
signal long_latch, long_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0'); signal long_latch, long_latch_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0');
signal khg_valid_in, khg_ready_in, khg_last_word_in, khg_valid_out, khg_ready_out, khg_last_word_out : std_logic := '0';
signal khg_data_in, khg_data_out : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal payload_mem_full, payload_mem_full_next : std_logic := '0'; signal payload_mem_full, payload_mem_full_next : std_logic := '0';
signal sample_mem_full, sample_mem_full_next : std_logic := '0'; signal sample_mem_full, sample_mem_full_next : std_logic := '0';
signal writer_pos, writer_pos_next : natural range TODO := 0;
signal writer_bitmap : ENDPOINT_BITMAP_ARRAY_TYPE;
signal instance_state : INSTANCE_STATE_TYPE := ALIVE;
signal key_hash, key_hash_next : KEY_HASH_TYPE := (others => (others => '0'));
signal od_instance_sample_removal : std_logic := '0';
signal od_oldest_sample_removal : std_logic := '0';
signal od_sample_removal_done : std_logic := '0';
signal sample_status_info, sample_status_info_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0');
signal gen_cnt : unsigned(CDR_LONG_WIDTH-1 downto 0) := (others => '0');
signal deadline : TIME_TYPE := TIME_INVALID;
signal release_inst_lock : std_logic := '0';
signal inst_addr_a, inst_addr_a_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0');
signal inst_addr_b, inst_addr_b_next : unsigned(PAYLOAD_MEMORY_ADDR_WIDTH-1 downto 0) := (others => '0');
signal inst_wen_a, inst_wen_b : std_logic := '0';
signal inst_ren_a, inst_ren_b : std_logic := '0';
signal inst_read_data_a, inst_read_data_b : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal inst_write_data_a, inst_write_data_b : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
signal inst_op_start_a : std_logic := '0'; signal inst_op_start_a : std_logic := '0';
signal inst_op_done_a : std_logic := '0'; signal inst_op_done_a : std_logic := '0';
@ -204,18 +212,6 @@ architecture arch of history_cache is
signal inst_atomic_lock_a : std_logic := '0'; signal inst_atomic_lock_a : std_logic := '0';
signal inst_long_latch_a, inst_long_latch_a_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0'); signal inst_long_latch_a, inst_long_latch_a_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0');
signal writer_pos, writer_pos_next : natural range TODO := 0;
signal writer_bitmap : ENDPOINT_BITMAP_ARRAY_TYPE;
signal instance_state : INSTANCE_STATE_TYPE := ALIVE;
signal key_hash, key_hash_next : KEY_HASH_TYPE := (others => (others => '0'));
signal od_instance_sample_removal : std_logic := '0';
signal od_oldest_sample_removal : std_logic := '0';
signal od_sample_removal_done : std_logic := '0';
signal sample_status_info, sample_status_info_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0) := (others => '0');
signal gen_cnt : unsigned(CDR_LONG_WIDTH-1 downto 0) := (others => '0');
signal deadline : TIME_TYPE := TIME_INVALID;
signal release_inst_lock : std_logic := '0';
--*****ALIAS DECLARATION***** --*****ALIAS DECLARATION*****
alias prev_sample : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_1; alias prev_sample : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_1;
alias prev_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_1_next; alias prev_sample_next : unsigned(SAMPLE_MEMORY_ADDR_WIDTH-1 downto 0) is sample_addr_latch_1_next;
@ -305,7 +301,6 @@ begin
); );
parse_a_prc : process (all) parse_a_prc : process (all)
variable tmp_opcode : HISTORY_CACHE_OPCODE_TYPE := NOP;
variable tmp_dw : DOUBLE_WORD_ARRAY := (others => (others => '0')); variable tmp_dw : DOUBLE_WORD_ARRAY := (others => (others => '0'));
variable tmp_bitmap : std_logic_vector(0 to ENDPOINT_BITMAP_WIDTH-1) := (others => '0'); variable tmp_bitmap : std_logic_vector(0 to ENDPOINT_BITMAP_WIDTH-1) := (others => '0');
variable tmp_update : std_logic_vector(0 to UPDATE_INSTANCE_FLAG_WIDTH-1) := (others => '0'); variable tmp_update : std_logic_vector(0 to UPDATE_INSTANCE_FLAG_WIDTH-1) := (others => '0');
@ -420,27 +415,44 @@ begin
-- Latch Status Info -- Latch Status Info
sample_status_info_next <= data_in_a; sample_status_info_next <= data_in_a;
sample_status_info_next(READ_FLAG) <= '0'; sample_status_info_next(READ_FLAG) <= '0';
-- Latch Key Hash
-- Key Hash 1/4
when 1 =>
key_hash_next(0) <= data_in_a;
-- Key Hash 2/4
when 2 =>
key_hash_next(1) <= data_in_a;
-- Key Hash 3/4
when 3 =>
key_hash_next(2) <= data_in_a;
-- Key Hash 4/4
when 4 =>
key_hash_next(3) <= data_in_a;
-- Latch Timestamp for ordering -- Latch Timestamp for ordering
-- Timestamp 1/2 -- Timestamp 1/2
when 5 => when 1 =>
ts_latch_next(0) <= data_in_a; ts_latch_next(0) <= data_in_a;
-- Timestamp 2/2 -- Timestamp 2/2
when 6 => when 2 =>
ts_latch_next(1) <= data_in_a; ts_latch_next(1) <= data_in_a;
-- Lifespan Deadline 2/2 -- Lifespna Deadline 2/2
when 4 =>
-- Skip Key Hash, if not available
if (has_key_hash = '0') then
cnt_a_next <= 9;
end if;
-- Latch Key Hash
-- Key Hash 1/4
when 5 =>
-- Latch Input, but do not pass to Memory
sample_wen_a <= '0';
sample_addr_a_next <= sample_addr_a;
key_hash_next(0) <= data_in_a;
-- Key Hash 2/4
when 6 =>
-- Latch Input, but do not pass to Memory
sample_wen_a <= '0';
sample_addr_a_next <= sample_addr_a;
key_hash_next(1) <= data_in_a;
-- Key Hash 3/4
when 7 =>
-- Latch Input, but do not pass to Memory
sample_wen_a <= '0';
sample_addr_a_next <= sample_addr_a;
key_hash_next(2) <= data_in_a;
-- Key Hash 4/4
when 8 =>
-- Latch Input, but do not pass to Memory
sample_wen_a <= '0';
sample_addr_a_next <= sample_addr_a;
key_hash_next(3) <= data_in_a;
when 9 => when 9 =>
-- Latch Input, but do not pass to Memory -- Latch Input, but do not pass to Memory
writer_pos_next <= to_integer(unsigned(data_in_a)); writer_pos_next <= to_integer(unsigned(data_in_a));
@ -454,6 +466,8 @@ begin
when ADD_PAYLOAD_ADDRESS => when ADD_PAYLOAD_ADDRESS =>
-- Precondition: sample_addr_a (Payload Address) -- Precondition: sample_addr_a (Payload Address)
sample_addr_a_next <= sample_addr_a + 1; -- Instance Address
if (has_data = '1') then if (has_data = '1') then
-- Store Payload Address -- Store Payload Address
sample_wen_a <= '1'; sample_wen_a <= '1';
@ -511,7 +525,6 @@ begin
if (last_word_in_a = '1') then if (last_word_in_a = '1') then
if (has_key_hash = '0') then if (has_key_hash = '0') then
khg_last_word_in <= '1'; khg_last_word_in <= '1';
sample_addr_a_next <= empty_sample_list_head + SMF_KEY_HASH_OFFSET;
stage_a_next <= GET_KEY_HASH; stage_a_next <= GET_KEY_HASH;
cnt_a_next <= 0; cnt_a_next <= 0;
else else
@ -547,16 +560,12 @@ begin
null; null;
end case; end case;
when GET_KEY_HASH => when GET_KEY_HASH =>
-- Precondition: sample_addr_a (KeyHash 1/4 of current sample)
khg_ready_out <= '1'; khg_ready_out <= '1';
if (khg_valid_out = '1') then if (khg_valid_out = '1') then
cnt_a_next <= cnt_a + 1; cnt_a_next <= cnt_a + 1;
sample_addr_a_next <= sample_addr_a + 1;
sample_wen_a <= '1';
sample_write_data_a <= khg_data_out;
-- Latch Key Hash -- Latch Key Hash
key_hash_next(cnt_a) <= khg_data_out; key_hash_next(cnt_a) <= khg_data_out;
@ -581,12 +590,18 @@ begin
end if; end if;
end if; end if;
when FILTER_STAGE => when FILTER_STAGE =>
-- Precondition: prev_sample set (empty_sample_list_tail) -- Precondition: sample_addr_a (Instance Address of New Sample)
-- Wait for Instance Search to finish -- Wait for Instance Search to finish
if (inst_op_done_a = '1') then if (inst_op_done_a = '1') then
sample_addr_a_next <= sample_addr_a + 1; -- Disposed Gen Counter (Prev Address if GENERATION_COUNTERS=FALSE)
-- Instance Found -- Instance Found
if (inst_addr_base_a /= INSTANCE_MEMORY_MAX_ADDRESS) then if (inst_addr_base_a /= INSTANCE_MEMORY_MAX_ADDRESS) then
-- Store Instance Address
sample_write_data_a <= inst_addr_base_a;
sample_wen_a <= '1';
-- TIME_BASED_FILTER QOS -- TIME_BASED_FILTER QOS
if (TIME_BASED_FILTER_QOS /= DURATION_ZERO and time < inst_data.ignore_deadline) then if (TIME_BASED_FILTER_QOS /= DURATION_ZERO and time < inst_data.ignore_deadline) then
-- Reject Change -- Reject Change
@ -613,6 +628,10 @@ begin
stage_a_next <= UPDATE_INSTANCE; stage_a_next <= UPDATE_INSTANCE;
end if; end if;
else else
-- Store Instance Address
sample_write_data_a <= inst_empty_head;
sample_wen_a <= '1';
-- MAX_INSTANCES Reached (Instance Memory Full) -- MAX_INSTANCES Reached (Instance Memory Full)
if (inst_mem_full = '1') then if (inst_mem_full = '1') then
-- Reject Change -- Reject Change
@ -635,7 +654,6 @@ begin
cnt_a_next <= 0; cnt_a_next <= 0;
else else
stage_a_next <= SAMPLE_PRE_FINISH; stage_a_next <= SAMPLE_PRE_FINISH;
sample_addr_a_next <= SMF_DISPOSED_GEN_CNT_OFFSET;
cnt_a_next <= 0 when GENERATION_COUNTERS else 2; cnt_a_next <= 0 when GENERATION_COUNTERS else 2;
end if; end if;
else else
@ -737,7 +755,6 @@ begin
cnt_a_next <= 0; cnt_a_next <= 0;
else else
stage_a_next <= SAMPLE_PRE_FINISH; stage_a_next <= SAMPLE_PRE_FINISH;
sample_addr_a_next <= SMF_DISPOSED_GEN_CNT_OFFSET;
cnt_a_next <= 0 when GENERATION_COUNTERS else 2; cnt_a_next <= 0 when GENERATION_COUNTERS else 2;
end if; end if;
end if; end if;
@ -765,7 +782,6 @@ begin
payload_wen_a <= '1'; payload_wen_a <= '1';
stage_a_next <= SAMPLE_PRE_FINISH; stage_a_next <= SAMPLE_PRE_FINISH;
sample_addr_a_next <= SMF_DISPOSED_GEN_CNT_OFFSET;
cnt_a_next <= 0 when GENERATION_COUNTERS else 2; cnt_a_next <= 0 when GENERATION_COUNTERS else 2;
when others => when others =>
null; null;
@ -1027,6 +1043,28 @@ begin
end case; end case;
end process; end process;
signal stage_b, stage_b_next : STAGE_TYPE := IDLE;
parse_b_prc : process (all)
begin
-- DEFAULT
stage_b_next <= stage_b;
case (stage_b) is
when IDLE =>
if (start_b = '1') then
case (opcode_b) is
when others =>
null;
end case;
end if;
when others =>
null;
end case;
end process;
inst_ctrl_prc : process(all) inst_ctrl_prc : process(all)
begin begin
-- DEFAULT Registered -- DEFAULT Registered
@ -1115,24 +1153,28 @@ begin
inst_addr_base_a_next <= inst_addr_base_a; inst_addr_base_a_next <= inst_addr_base_a;
if ((update_inst_flags_a and STATUS_FLAG) = STATUS_FLAG) then if ((update_inst_flags_a and STATUS_FLAG) = STATUS_FLAG) then
inst_stage_a_next <= UPDATE_INSTANCE; inst_stage_a_next <= UPDATE_INSTANCE;
inst_addr_a_next <= inst_addr_base_a + 5; inst_addr_a_next <= inst_addr_base_a + IMF_STATUS_INFO_OFFSET;
inst_cnt_a_next <= 0; inst_cnt_a_next <= 0;
elsif ((update_inst_flags_a and SAMPLE_CNT_FLAG) = SAMPLE_CNT_FLAG) then elsif (MAX_SAMPLES_PER_INSTANCE /= LENGTH_UNLIMITED and (update_inst_flags_a and SAMPLE_CNT_FLAG) = SAMPLE_CNT_FLAG) then
inst_stage_a_next <= UPDATE_INSTANCE; inst_stage_a_next <= UPDATE_INSTANCE;
inst_addr_a_next <= inst_addr_base_a + 6; inst_addr_a_next <= inst_addr_base_a + IMF_SAMPLE_CNT_OFFSET;
inst_cnt_a_next <= 3; inst_cnt_a_next <= 3;
elsif ((update_inst_flags_a and DISPOSED_CNT_FLAG) = DISPOSED_CNT_FLAG) then elsif (GENERATION_COUNTERS and (update_inst_flags_a and DISPOSED_CNT_FLAG) = DISPOSED_CNT_FLAG) then
inst_stage_a_next <= UPDATE_INSTANCE; inst_stage_a_next <= UPDATE_INSTANCE;
inst_addr_a_next <= inst_addr_base_a + 7; inst_addr_a_next <= inst_addr_base_a + IMF_DISPOSED_GEN_CNT_OFFSET;
inst_cnt_a_next <= 6; inst_cnt_a_next <= 6;
elsif ((update_inst_flags_a and NO_WRITERS_CNT_FLAG) = NO_WRITERS_CNT_FLAG) then elsif (GENERATION_COUNTERS and (update_inst_flags_a and NO_WRITERS_CNT_FLAG) = NO_WRITERS_CNT_FLAG) then
inst_stage_a_next <= UPDATE_INSTANCE; inst_stage_a_next <= UPDATE_INSTANCE;
inst_addr_a_next <= inst_addr_base_a + 8; inst_addr_a_next <= inst_addr_base_a + IMF_NO_WRITERS_GEN_CNT_OFFSET;
inst_cnt_a_next <= 7; inst_cnt_a_next <= 7;
elsif ((update_inst_flags_a and IGNORE_DEADLINE_FLAG) = IGNORE_DEADLINE_FLAG) then elsif (TIME_BASED_FILTER_QOS /= DURATION_ZERO and (update_inst_flags_a and IGNORE_DEADLINE_FLAG) = IGNORE_DEADLINE_FLAG) then
inst_stage_a_next <= UPDATE_INSTANCE; inst_stage_a_next <= UPDATE_INSTANCE;
inst_addr_a_next <= inst_addr_base_a + 9; inst_addr_a_next <= inst_addr_base_a + IMF_IGNORE_DEADLINE_OFFSET;
inst_cnt_a_next <= 8; inst_cnt_a_next <= 8;
elsif ((update_inst_flags_a and WRITER_BITMAP_FLAG) = WRITER_BITMAP_FLAG) then
inst_stage_a_next <= SET_WRITER_BITMAP;
inst_addr_a_next <= inst_addr_base_a + IMF_WRITER_BITMAP_OFFSET;
inst_cnt_a_next <= 0;
end if; end if;
when GET_FIRST_INSTANCE => when GET_FIRST_INSTANCE =>
-- NOTE: This process gets the lock implicitly when the SEARCH_INSTANCE, or GET_FIRST_INSTANCE operation is called, and has to be released explicitly -- NOTE: This process gets the lock implicitly when the SEARCH_INSTANCE, or GET_FIRST_INSTANCE operation is called, and has to be released explicitly
@ -1399,24 +1441,61 @@ begin
-- Status Info -- Status Info
when 5 => when 5 =>
inst_write_data_a <= inst_latch_data.status_info; inst_write_data_a <= inst_latch_data.status_info;
if (MAX_SAMPLES_PER_INSTANCE /= LENGTH_UNLIMITED) then
null;
elsif (GENERATION_COUNTERS) then
inst_cnt_a <= 7;
elsif (TIME_BASED_FILTER_QOS /= DURATION_ZERO) then
inst_cnt_a <= 9;
else
inst_stage_a_next <= SET_WRITER_BITMAP;
inst_cnt_a_next <= 0;
end if;
-- Sample Count -- Sample Count
when 6 => when 6 =>
inst_write_data_a <= std_logic_vector(to_unsigned(1, WORD_WIDTH)); if (MAX_SAMPLES_PER_INSTANCE /= LENGTH_UNLIMITED) then
inst_write_data_a <= std_logic_vector(to_unsigned(1, WORD_WIDTH));
if (GENERATION_COUNTERS) then
inst_cnt_a <= 7;
elsif (TIME_BASED_FILTER_QOS /= DURATION_ZERO) then
inst_cnt_a <= 9;
else
inst_stage_a_next <= SET_WRITER_BITMAP;
inst_cnt_a_next <= 0;
end if;
end if;
-- Disposed Generation Count -- Disposed Generation Count
when 7 => when 7 =>
inst_write_data_a <= (others => '0'); if (GENERATION_COUNTERS) then
inst_write_data_a <= (others => '0');
end if;
-- No Writers Generation Count -- No Writers Generation Count
when 8 => when 8 =>
inst_write_data_a <= (others => '0'); if (GENERATION_COUNTERS) then
inst_write_data_a <= (others => '0');
if (TIME_BASED_FILTER_QOS /= DURATION_ZERO) then
inst_cnt_a <= 9;
else
inst_stage_a_next <= SET_WRITER_BITMAP;
inst_cnt_a_next <= 0;
end if;
end if;
-- Ignore Deadline 1/2 -- Ignore Deadline 1/2
when 9 => when 9 =>
inst_write_data_a <= inst_latch_data.deadline(0); if (TIME_BASED_FILTER_QOS /= DURATION_ZERO) then
inst_write_data_a <= inst_latch_data.deadline(0);
end if;
-- Ignore Deadline 1/2 -- Ignore Deadline 1/2
when 10 => when 10 =>
inst_write_data_a <= inst_latch_data.deadline(0); if (TIME_BASED_FILTER_QOS /= DURATION_ZERO) then
inst_write_data_a <= inst_latch_data.deadline(1);
inst_stage_a_next <= SET_WRITER_BITMAP;
inst_cnt_a_next <= 0; inst_stage_a_next <= SET_WRITER_BITMAP;
inst_cnt_a_next <= 0;
end if;
when others => when others =>
null; null;
end case; end case;
@ -1439,14 +1518,8 @@ begin
-- *Status Info Begin* -- *Status Info Begin*
-- Preload -- Preload
when 0 => when 0 =>
if ((inst_latch_data.update_flags and STATUS_FLAG) = STATUS_FLAG) then inst_atomic_lock_a <= '1';
inst_ren_a <= '1'; inst_ren_a <= '1';
inst_atomic_lock_a <= '1';
else
-- Skip
inst_addr_a_next <= inst_addr_a + 1;
inst_cnt_a_next <= 3;
end if;
-- Read -- Read
when 1 => when 1 =>
-- Latch Contents -- Latch Contents
@ -1454,6 +1527,8 @@ begin
inst_long_latch_a_next <= inst_read_data_a; inst_long_latch_a_next <= inst_read_data_a;
-- Write -- Write
when 2 => when 2 =>
inst_atomic_lock_a <= '1';
inst_wen_a <= '1';
inst_write_data_a <= inst_long_latch_a; inst_write_data_a <= inst_long_latch_a;
case (inst_latch_data.instance_state) is case (inst_latch_data.instance_state) is
when ALIVE => when ALIVE =>
@ -1469,85 +1544,127 @@ begin
inst_write_data_a(NOT_ALIVE_NO_WRITERS_FLAG) <= '1'; inst_write_data_a(NOT_ALIVE_NO_WRITERS_FLAG) <= '1';
inst_write_data_a(LIVELINESS_FLAG) <= '1'; inst_write_data_a(LIVELINESS_FLAG) <= '1';
end case; end case;
inst_addr_a_next <= inst_addr_a + 1;
inst_wen_a <= '1';
inst_atomic_lock_a <= '1';
-- If nothing else to update if (MAX_SAMPLES_PER_INSTANCE /= LENGTH_UNLIMITED and (inst_latch_data.update_flags and SAMPLE_CNT_FLAG) = SAMPLE_CNT_FLAG) then
if ((inst_latch_data.update_flags and (SAMPLE_CNT_FLAG or DISPOSED_CNT_FLAG or NO_WRITERS_CNT_FLAG or IGNORE_DEADLINE_FLAG or WRITER_BITMAP_FLAG)) = (inst_latch_data.update_flags'range => '0')) then inst_addr_a_next <= inst_addr_base_a + IMF_SAMPLE_CNT_OFFSET;
inst_cnt_a_next <= 3;
elsif (GENERATION_COUNTERS and (inst_latch_data.update_flags and DISPOSED_CNT_FLAG) = DISPOSED_CNT_FLAG) then
inst_addr_a_next <= inst_addr_base_a + IMF_DISPOSED_GEN_CNT_OFFSET;
inst_cnt_a_next <= 6;
elsif (GENERATION_COUNTERS and (inst_latch_data.update_flags and NO_WRITERS_CNT_FLAG) = NO_WRITERS_CNT_FLAG) then
inst_addr_a_next <= inst_addr_base_a + IMF_NO_WRITERS_GEN_CNT_OFFSET;
inst_cnt_a_next <= 7;
elsif (TIME_BASED_FILTER_QOS /= DURATION_ZERO and (inst_latch_data.update_flags and IGNORE_DEADLINE_FLAG) = IGNORE_DEADLINE_FLAG) then
inst_addr_a_next <= inst_addr_base_a + IMF_IGNORE_DEADLINE_OFFSET;
inst_cnt_a_next <= 8;
elsif ((inst_latch_data.update_flags and WRITER_BITMAP_FLAG) = WRITER_BITMAP_FLAG) then
inst_addr_a_next <= inst_addr_base_a + IMF_WRITER_BITMAP_OFFSET;
inst_stage_a_next <= SET_WRITER_BITMAP;
inst_cnt_a_next <= 0;
else
-- DONE -- DONE
inst_stage_a_next <= IDLE; inst_stage_a_next <= IDLE;
end if; end if;
-- *Status Info End* -- *Status Info End*
-- *Sample Count Begin* -- *Sample Count Begin*
-- Preload -- Preload
when 3 => when 3 =>
if ((inst_latch_data.update_flags and SAMPLE_CNT_FLAG) = SAMPLE_CNT_FLAG) then if (MAX_SAMPLES_PER_INSTANCE /= LENGTH_UNLIMITED) then
inst_ren_a <= '1'; inst_ren_a <= '1';
inst_atomic_lock_a <= '1'; inst_atomic_lock_a <= '1';
else
-- Skip
inst_addr_a_next <= inst_addr_a + 1;
inst_cnt_a_next <= 6;
end if; end if;
-- Read -- Read
when 4 => when 4 =>
-- Latch Contents if (MAX_SAMPLES_PER_INSTANCE /= LENGTH_UNLIMITED) then
inst_atomic_lock_a <= '1'; -- Latch Contents
inst_long_latch_a_next <= inst_read_data_a; inst_atomic_lock_a <= '1';
inst_long_latch_a_next <= inst_read_data_a;
end if;
when 5 => when 5 =>
-- Increment Sample Count if (MAX_SAMPLES_PER_INSTANCE /= LENGTH_UNLIMITED) then
inst_write_data_a <= std_logic_vector(unsigned(inst_long_latch_a) + 1); -- Increment Sample Count
inst_wen_a <= '1'; inst_atomic_lock_a <= '1';
inst_atomic_lock_a <= '1'; inst_wen_a <= '1';
inst_write_data_a <= std_logic_vector(unsigned(inst_long_latch_a) + 1);
-- If nothing else to update
if ((inst_latch_data.update_flags and (DISPOSED_CNT_FLAG or NO_WRITERS_CNT_FLAG or IGNORE_DEADLINE_FLAG or WRITER_BITMAP_FLAG)) = (inst_latch_data.update_flags'range => '0')) then if (GENERATION_COUNTERS and (inst_latch_data.update_flags and DISPOSED_CNT_FLAG) = DISPOSED_CNT_FLAG) then
-- DONE inst_addr_a_next <= inst_addr_base_a + IMF_DISPOSED_GEN_CNT_OFFSET;
inst_stage_a_next <= IDLE; inst_cnt_a_next <= 6;
elsif (GENERATION_COUNTERS and (inst_latch_data.update_flags and NO_WRITERS_CNT_FLAG) = NO_WRITERS_CNT_FLAG) then
inst_addr_a_next <= inst_addr_base_a + IMF_NO_WRITERS_GEN_CNT_OFFSET;
inst_cnt_a_next <= 7;
elsif (TIME_BASED_FILTER_QOS /= DURATION_ZERO and (inst_latch_data.update_flags and IGNORE_DEADLINE_FLAG) = IGNORE_DEADLINE_FLAG) then
inst_addr_a_next <= inst_addr_base_a + IMF_IGNORE_DEADLINE_OFFSET;
inst_cnt_a_next <= 8;
elsif ((inst_latch_data.update_flags and WRITER_BITMAP_FLAG) = WRITER_BITMAP_FLAG) then
inst_addr_a_next <= inst_addr_base_a + IMF_WRITER_BITMAP_OFFSET;
inst_stage_a_next <= SET_WRITER_BITMAP;
inst_cnt_a_next <= 0;
else
-- DONE
inst_stage_a_next <= IDLE;
end if;
end if; end if;
-- *Sample Count End* -- *Sample Count End*
-- Disposed Generation Count -- Disposed Generation Count
when 6 => when 6 =>
inst_write_data_a <= inst_latch_data.gen_cnt; if (GENERATION_COUNTERS) then
if ((inst_latch_data.update_flags and DISPOSED_CNT_FLAG) = DISPOSED_CNT_FLAG) then inst_wen_a <= '1';
inst_wen_a <= '1'; inst_write_data_a <= inst_latch_data.gen_cnt;
end if;
-- If nothing else to update if (GENERATION_COUNTERS and (inst_latch_data.update_flags and NO_WRITERS_CNT_FLAG) = NO_WRITERS_CNT_FLAG) then
if ((inst_latch_data.update_flags and (NO_WRITERS_CNT_FLAG or IGNORE_DEADLINE_FLAG or WRITER_BITMAP_FLAG)) = (inst_latch_data.update_flags'range => '0')) then inst_addr_a_next <= inst_addr_base_a + IMF_NO_WRITERS_GEN_CNT_OFFSET;
-- DONE inst_cnt_a_next <= 7;
inst_stage_a_next <= IDLE; elsif (TIME_BASED_FILTER_QOS /= DURATION_ZERO and (inst_latch_data.update_flags and IGNORE_DEADLINE_FLAG) = IGNORE_DEADLINE_FLAG) then
inst_addr_a_next <= inst_addr_base_a + IMF_IGNORE_DEADLINE_OFFSET;
inst_cnt_a_next <= 8;
elsif ((inst_latch_data.update_flags and WRITER_BITMAP_FLAG) = WRITER_BITMAP_FLAG) then
inst_addr_a_next <= inst_addr_base_a + IMF_WRITER_BITMAP_OFFSET;
inst_stage_a_next <= SET_WRITER_BITMAP;
inst_cnt_a_next <= 0;
else
-- DONE
inst_stage_a_next <= IDLE;
end if;
end if; end if;
-- No Writers Generation Count -- No Writers Generation Count
when 7 => when 7 =>
inst_write_data_a <= inst_latch_data.gen_cnt; if (GENERATION_COUNTERS) then
if ((inst_latch_data.update_flags and NO_WRITERS_CNT_FLAG) = NO_WRITERS_CNT_FLAG) then inst_wen_a <= '1';
inst_wen_a <= '1'; inst_write_data_a <= inst_latch_data.gen_cnt;
end if;
-- If nothing else to update if (TIME_BASED_FILTER_QOS /= DURATION_ZERO and (inst_latch_data.update_flags and IGNORE_DEADLINE_FLAG) = IGNORE_DEADLINE_FLAG) then
if ((inst_latch_data.update_flags and (IGNORE_DEADLINE_FLAG or WRITER_BITMAP_FLAG)) = (inst_latch_data.update_flags'range => '0')) then inst_addr_a_next <= inst_addr_base_a + IMF_IGNORE_DEADLINE_OFFSET;
-- DONE inst_cnt_a_next <= 8;
inst_stage_a_next <= IDLE; elsif ((inst_latch_data.update_flags and WRITER_BITMAP_FLAG) = WRITER_BITMAP_FLAG) then
inst_addr_a_next <= inst_addr_base_a + IMF_WRITER_BITMAP_OFFSET;
inst_stage_a_next <= SET_WRITER_BITMAP;
inst_cnt_a_next <= 0;
else
-- DONE
inst_stage_a_next <= IDLE;
end if;
end if; end if;
-- Ignore Deadline 1/2 -- Ignore Deadline 1/2
when 8 => when 8 =>
inst_write_data_a <= std_logic_vector(inst_latch_data.ignore_deadline(0)); if (TIME_BASED_FILTER_QOS /= DURATION_ZERO) then
if ((inst_latch_data.update_flags and IGNORE_DEADLINE_FLAG) = IGNORE_DEADLINE_FLAG) then inst_wen_a <= '1';
inst_wen_a <= '1'; inst_write_data_a <= std_logic_vector(inst_latch_data.ignore_deadline(0));
end if; end if;
-- Ignore Deadline 2/2 -- Ignore Deadline 2/2
when 9 => when 9 =>
inst_write_data_a <= std_logic_vector(inst_latch_data.ignore_deadline(1)); if (TIME_BASED_FILTER_QOS /= DURATION_ZERO) then
if ((inst_latch_data.update_flags and IGNORE_DEADLINE_FLAG) = IGNORE_DEADLINE_FLAG) then inst_wen_a <= '1';
inst_wen_a <= '1'; inst_write_data_a <= std_logic_vector(inst_latch_data.ignore_deadline(1));
end if;
-- If nothing else to update if ((inst_latch_data.update_flags and WRITER_BITMAP_FLAG) = WRITER_BITMAP_FLAG) then
if ((inst_latch_data.update_flags and (WRITER_BITMAP_FLAG)) = (inst_latch_data.update_flags'range => '0')) then inst_addr_a_next <= inst_addr_base_a + IMF_WRITER_BITMAP_OFFSET;
-- DONE inst_stage_a_next <= SET_WRITER_BITMAP;
inst_stage_a_next <= IDLE; inst_cnt_a_next <= 0;
else else
inst_stage_a_next <= SET_WRITER_BITMAP; -- DONE
inst_cnt_a_next <= 0; inst_stage_a_next <= IDLE;
end if;
end if; end if;
when others => when others =>
null; null;

36
src/rtps_endpoint.vhd
View File

@ -941,30 +941,34 @@ begin
hc_data_in <= status_info; hc_data_in <= status_info;
hc_data_in(KEY_HASH_FLAG) <= key_hash_rcvd; hc_data_in(KEY_HASH_FLAG) <= key_hash_rcvd;
hc_data_in(PAYLOAD_FLAG) <= data_flag; hc_data_in(PAYLOAD_FLAG) <= data_flag;
-- Key hash 1/4
when 1 =>
hc_data_in <= key_hash(0);
-- Key Hash 2/4
when 2 =>
hc_data_in <= key_hash(1);
-- Key Hash 3/4
when 3 =>
hc_data_in <= key_hash(2);
-- Key hash 4/4
when 4 =>
hc_data_in <= key_hash(3);
-- Timestamp 1/2 -- Timestamp 1/2
when 5 => when 1 =>
hc_data_in <= ts(0); hc_data_in <= ts(0);
-- Timestamp 2/2 -- Timestamp 2/2
when 6 => when 2 =>
hc_data_in <= ts(1); hc_data_in <= ts(1);
-- Lifespan Deadline 1/2 -- Lifespan Deadline 1/2
when 7 => when 3 =>
hc_data_in <= deadline(0); hc_data_in <= deadline(0);
-- Lifespan Deadline 2/2 -- Lifespan Deadline 2/2
when 8 => when 4 =>
hc_data_in <= deadline(1); hc_data_in <= deadline(1);
-- Skip Key Hash, if not received
if (key_hash_rcvd = '0') then
cnt_next <= 9;
end if;
-- Key hash 1/4
when 5 =>
hc_data_in <= key_hash(0);
-- Key Hash 2/4
when 6 =>
hc_data_in <= key_hash(1);
-- Key Hash 3/4
when 7 =>
hc_data_in <= key_hash(2);
-- Key hash 4/4
when 8 =>
hc_data_in <= key_hash(3);
-- Endpoint Memory Position -- Endpoint Memory Position
when 9 => when 9 =>
-- Wait for Endpoint Search -- Wait for Endpoint Search