greek64/rtps-fpga
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32fd1ac31e
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6 Commits

Author SHA1 Message Date
Greek
32fd1ac31e * Add modelsim.ini File in gitignore 
* Small change in rtps_builtin_endpoint_test1
	- Empty Signal was not toggling
* Added rtps_builtin_endpoint_test2
	- Compiling and Passing
* Update rtps_test_package
* Various bug Fixes in rtps_builtin_endpoint
 2020-11-26 18:04:59 +01:00
Greek
9c95e58e32 * Added OSVVM Library as Submodule 
* Merged stimulus generation procedures to one single procedure
* Integrated OSVVM into testbench
* Generated OSVVM Project Script File
* Various Bug Fixes to compile testbench
 2020-11-15 20:34:39 +01:00
Greek
9acd98b32e * Update .gitignore 
* Split rtps_package
 2020-11-02 14:39:27 +01:00
Greek
721d03ac8b * Project Restructure 
- SYN Directory divided onto subdirectories depending on target
	  Board
* Added DE10-Nano Project
 2020-05-29 12:10:07 +02:00
Greek
10cda546bf * Add documentation 
- IPv4 RFC
	- FPGA Network Stack Master Thesis
* Updated .gitignore
* Added Single Port RAM
	- Xillinx Specific
* Added IPv4 Parser
	- Dynamic Re-assembly Buffer selection
	- Main entity documentation missing
	- Synthesized, but not tested or simulated
* Added Vivado (Zedboard) project for synthesis testing
 2020-05-13 13:37:23 +02:00
Greek
b118482e63 * Added DDS/RTPS Documentation 
* Added initial constant package
 2020-05-10 19:31:49 +02:00