8 Commits

Author	SHA1	Message	Date
Greek	46ca2228b6	Add and Redefine existing Dual Port RAM Implementations ... Simple Dual Port (Read and Write Port), and True Dual Port RAM implementations, together with their respective Altera implementations were added. The 'arch' Architectures should have the same behaviour as the Altera Implementations (single_port_ram was modified to achieve that)	2021-12-09 19:44:40 +01:00
Greek64	5d9acb6f41	Add directive to allow QSYS Compilation ... QSYS does not allow to change the VHDL version of processed files. All respective files have to have a comment directive forcing the VHDL version.	2021-12-09 19:44:38 +01:00
Greek	0ede0537b7	Add test entities to test PL-PS communication	2021-12-09 19:44:37 +01:00
Greek	6e20b8958d	Add VHDL configuration for single_port_ram and FWFT_FIFO ... Allow single_port_ram and FWFT_FIFO to have Altera specific architectures.	2021-12-09 19:43:56 +01:00
Greek	7244fffacd	Memory Size of rtps_builtin_endpoint made Generic ... Each Entity that contains a memory will have an independent size generic. The testbench was modified to accomodate different RAM memory sizes. This in effect makes all Memory related stuff pre-entity dependant. The rtps_test_package needs updated Frame Sizes for the Tests to work properly.	2021-02-17 10:51:57 +01:00
Greek	d61b9dc80a	* rtps_builtin_endpoint compiles ... * Single port RAM implementation for Altera * Added Altera doc	2020-10-26 23:43:54 +01:00
Greek64	e6e4094583	* Endoint Match/Unmatch	2020-10-04 08:25:35 +02:00
Greek	10cda546bf	* Add documentation ... - IPv4 RFC - FPGA Network Stack Master Thesis * Updated .gitignore * Added Single Port RAM - Xillinx Specific * Added IPv4 Parser - Dynamic Re-assembly Buffer selection - Main entity documentation missing - Synthesized, but not tested or simulated * Added Vivado (Zedboard) project for synthesis testing	2020-05-13 13:37:23 +02:00