3 Commits

Author	SHA1	Message	Date
Greek	46ca2228b6	Add and Redefine existing Dual Port RAM Implementations ... Simple Dual Port (Read and Write Port), and True Dual Port RAM implementations, together with their respective Altera implementations were added. The 'arch' Architectures should have the same behaviour as the Altera Implementations (single_port_ram was modified to achieve that)	2021-12-09 19:44:40 +01:00
Greek64	5d9acb6f41	Add directive to allow QSYS Compilation ... QSYS does not allow to change the VHDL version of processed files. All respective files have to have a comment directive forcing the VHDL version.	2021-12-09 19:44:38 +01:00
Greek	349db19edd	Add True Dual Port RAM Implementation	2021-01-11 12:16:37 +01:00