Commit Graph

3 Commits

Author SHA1 Message Date
Greek
721d03ac8b * Project Restructure
- SYN Directory divided onto subdirectories depending on target
	  Board
* Added DE10-Nano Project
2020-05-29 12:10:07 +02:00
Greek
10cda546bf * Add documentation
- IPv4 RFC
	- FPGA Network Stack Master Thesis
* Updated .gitignore
* Added Single Port RAM
	- Xillinx Specific
* Added IPv4 Parser
	- Dynamic Re-assembly Buffer selection
	- Main entity documentation missing
	- Synthesized, but not tested or simulated
* Added Vivado (Zedboard) project for synthesis testing
2020-05-13 13:37:23 +02:00
Greek
b118482e63 * Added DDS/RTPS Documentation
* Added initial constant package
2020-05-10 19:31:49 +02:00