74af242bcc
code refactoring
2022-04-05 17:20:32 +02:00
ad03ae6ecd
Remove RTPS_OUT_DATA_TYPE and modify rtps_out with generic
2022-03-20 11:49:41 +01:00
Greek
c88d4ccf07
Modify rtps_out to use Dual Port RAM
2021-12-09 19:44:40 +01:00
Greek
70549853d5
code refactoring
2021-12-09 19:44:39 +01:00
5d9acb6f41
Add directive to allow QSYS Compilation
...
QSYS does not allow to change the VHDL version of processed files.
All respective files have to have a comment directive forcing the VHDL version.
2021-12-09 19:44:38 +01:00
Greek
cffaafb284
Code refactoring
2021-11-20 16:01:57 +01:00
Greek
63465e8e30
Remove default signal initialization from entire codebase
2021-11-19 18:50:18 +01:00
Greek
e87d84ba24
Modify ports of rtps_builtin_endpoint according to port naming convention
...
The ports to rtps_out from the rtps_reader and rtps_writer entities were
also modified to apply a uniform naming.
2021-11-18 16:44:42 +01:00
Greek
9cc4907a2f
Add complete Level2 System Test
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Using seperately compiled Libraries we interconnect two systems, and
test their communication and interaction.
A bug in rtps_builtin_endpoint was fixed (were if only the SUB data was
to be sent, it was never actually sent).
2021-11-17 14:23:53 +01:00
Greek
f8debfb086
* Add rtps_out Entity
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- Use round robin to select output from endpoints and generate the expected uniform RTPS system output
* Add rtps_out_test1
- Compiling and Passing
2020-12-02 14:21:27 +01:00
Greek
c1bb9a7bd2
* Re-design rtps_handler
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- Input format is now a decoded UDP Packet (Documented in REF.txt)
This allows the whole RTPS system to use universal input and output.
2020-11-30 15:48:47 +01:00
