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02f0fbfb98
rtps-fpga/src
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Greek 02f0fbfb98 Add PREFER_MULTICAST generic in rtps_buildin_endpoint 
Until now the rtps_builtin_endpoint was using the last parsed Locator as
the Locator of choice.
The rtps_builtin_endpoint was extended with a PREFER_MULTICAST boolean
generic that allows to influence which locators are used.
Test1 of rtps_builtin_endpoint was split in two, to test both settings
of the generic.
2021-12-13 14:31:33 +01:00
..
OSVVM@6b81053596 * Added OSVVM Library as Submodule 2020-11-15 20:34:39 +01:00
Tests Add PREFER_MULTICAST generic in rtps_buildin_endpoint 2021-12-13 14:31:33 +01:00
addsub.vhd Add directive to allow QSYS Compilation 2021-12-09 19:44:38 +01:00
ASCII.txt Add documentation 2021-11-17 14:27:30 +01:00
Avalon_MM_wrapper.vhd Add directive to allow QSYS Compilation 2021-12-09 19:44:38 +01:00
checksum.vhd Add directive to allow QSYS Compilation 2021-12-09 19:44:38 +01:00
dds_reader.vhd TIMING CLOSURE: Further Sub-Split FIND_NEXT_INSTANCE in dds_reader 2021-12-09 23:32:18 +01:00
dds_writer.vhd code refactoring 2021-12-09 19:44:39 +01:00
dp_mem_ctrl.vhd Add Dual Port Memory Controller 2021-12-09 19:44:40 +01:00
dual_port_ram_Altera.vhd Add and Redefine existing Dual Port RAM Implementations 2021-12-09 19:44:40 +01:00
dual_port_ram_cfg.vhd Add and Redefine existing Dual Port RAM Implementations 2021-12-09 19:44:40 +01:00
dual_port_ram.vhd Add and Redefine existing Dual Port RAM Implementations 2021-12-09 19:44:40 +01:00
FWFT_FIFO_Altera.vhd Add directive to allow QSYS Compilation 2021-12-09 19:44:38 +01:00
FWFT_FIFO_cfg.vhd Add directive to allow QSYS Compilation 2021-12-09 19:44:38 +01:00
FWFT_FIFO.vhd code refactoring 2021-12-09 19:44:39 +01:00
history_cache.vhd Add directive to allow QSYS Compilation 2021-12-09 19:44:38 +01:00
IDL-VHDL_Ref.txt Bug Fix and Redesign of TEMPLATE_key_holder 2021-12-09 19:44:38 +01:00
ip_package.vhd Add directive to allow QSYS Compilation 2021-12-09 19:44:38 +01:00
ipv4_in_handler.vhd Add directive to allow QSYS Compilation 2021-12-09 19:44:38 +01:00
key_hash_generator.vhd Add directive to allow QSYS Compilation 2021-12-09 19:44:38 +01:00
key_holder.vhd Bug Fix and Redesign of TEMPLATE_key_holder 2021-12-09 19:44:38 +01:00
math_pkg.vhd Add directive to allow QSYS Compilation 2021-12-09 19:44:38 +01:00
mem_ctrl.vhd code refactoring 2021-12-09 19:44:40 +01:00
PID_Ref.txt Add test 2 of RTPS Reader 2021-02-21 00:02:22 +01:00
REF.txt Minor declaration & documentation fixes 2021-11-03 20:07:14 +01:00
rtps_builtin_endpoint.vhd Add PREFER_MULTICAST generic in rtps_buildin_endpoint 2021-12-13 14:31:33 +01:00
rtps_config_package.vhd code refactoring 2021-12-09 19:44:39 +01:00
rtps_handler.vhd BUG FIX: PID is affected by endianness 2021-12-11 12:20:52 +01:00
rtps_out.vhd Modify rtps_out to use Dual Port RAM 2021-12-09 19:44:40 +01:00
rtps_package.vhd BUG FIX: PID is affected by endianness 2021-12-11 12:20:52 +01:00
rtps_reader.vhd BUG FIX: PID is affected by endianness 2021-12-11 12:20:52 +01:00
rtps_test_package.vhd Add PREFER_MULTICAST generic in rtps_buildin_endpoint 2021-12-13 14:31:33 +01:00
rtps_writer.vhd code refactoring 2021-12-09 19:44:39 +01:00
single_port_ram_Altera.vhd Add directive to allow QSYS Compilation 2021-12-09 19:44:38 +01:00
single_port_ram_cfg.vhd Add directive to allow QSYS Compilation 2021-12-09 19:44:38 +01:00
single_port_ram.vhd Add and Redefine existing Dual Port RAM Implementations 2021-12-09 19:44:40 +01:00
TEMPLATE_dds_top.vhd Add dds_top TEMPLATE 2021-12-09 19:44:39 +01:00
TEMPLATE_key_holder.vhd Fix Bug in Key Holder 2021-12-09 19:44:39 +01:00
TEMPLATE_reader_wrapper.vhd code refactoring 2021-12-09 19:44:39 +01:00
TEMPLATE_user_config.vhd Add PREFER_MULTICAST generic in rtps_buildin_endpoint 2021-12-13 14:31:33 +01:00
TEMPLATE_writer_wrapper.vhd Bug Fix in TYPENAME_writer_wrapper 2021-12-09 19:44:40 +01:00
TODO.txt Bug Fix and Redesign of TEMPLATE_key_holder 2021-12-09 19:44:38 +01:00
top.xdc * Add documentation 2020-05-13 13:37:23 +02:00
true_dual_port_ram_Altera.vhd Add and Redefine existing Dual Port RAM Implementations 2021-12-09 19:44:40 +01:00
true_dual_port_ram_cfg.vhd Add and Redefine existing Dual Port RAM Implementations 2021-12-09 19:44:40 +01:00
true_dual_port_ram.vhd Add and Redefine existing Dual Port RAM Implementations 2021-12-09 19:44:40 +01:00
Type_CDR_ref.txt Define Type2 IDL and implement TYPE2_READER_WRAPPER 2021-11-04 14:16:32 +01:00
verbatim_key_hash_generator.vhd Add/Modify synthesis entities to synthesize test_loopback 2021-12-09 23:32:08 +01:00