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5d9acb6f41
QSYS does not allow to change the VHDL version of processed files. All respective files have to have a comment directive forcing the VHDL version.
80 lines
2.6 KiB
VHDL
80 lines
2.6 KiB
VHDL
-- altera vhdl_input_version vhdl_2008
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-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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Library UNISIM;
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use UNISIM.vcomponents.all;
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Library UNIMACRO;
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use UNIMACRO.vcomponents.all;
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-- Add/Sub
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-- This entity adds or subtracts inputs 'A' and 'B', depending on 'mode' (1 = add, 0 = sub).
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-- If 'cap' is high, on Overfolw/Underflow conditions the result is capped at max/min value.
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entity addsub is
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generic (
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PIPELINE_STAGES : integer := 1;
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DATA_WIDTH : integer := 16
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);
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port (
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clk : in std_logic;
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reset : in std_logic;
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mode : in std_logic;
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cap : in std_logic;
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A : in std_logic_vector(DATA_WIDTH-1 downto 0);
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B : in std_logic_vector(DATA_WIDTH-1 downto 0);
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RES : out std_logic_vector(DATA_WIDTH-1 downto 0)
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);
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end entity;
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architecture arch of addsub is
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--*****SIGNAl DECLARATION
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signal result : std_logic_vector(DATA_WIDTH-1 downto 0);
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signal carry : std_logic;
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begin
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ADDSUB_MACRO_inst : ADDSUB_MACRO
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generic map (
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DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "7SERIES", "SPARTAN6"
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LATENCY => PIPELINE_STAGES, -- Desired clock cycle latency, 0-2
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WIDTH => DATA_WIDTH -- Input / Output bus width, 1-48
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)
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port map (
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CARRYOUT => open, -- 1-bit carry-out output signal
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RESULT => result, -- Add/sub result output, width defined by WIDTH generic
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A => A, -- Input A bus, width defined by WIDTH generic
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ADD_SUB => mode, -- 1-bit add/sub input, high selects add, low selects subtract
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B => B, -- Input B bus, width defined by WIDTH generic
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CARRYIN => '0', -- 1-bit carry-in input
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CE => '1', -- 1-bit clock enable input
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CLK => clk, -- 1-bit clock input
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RST => reset -- 1-bit active high synchronous reset
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);
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clamp : process(all)
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begin
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--DEFAULT VALUE
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RES <= result;
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--Overflow/Underflow
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if(carry = '1' and cap = '1') then
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--ADD
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if(mode = '1') then
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--CAP AT MAX VALUE
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RES <= (others => '1');
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--SUB
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else
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--CAP AT ZERO
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RES <= (others => '0');
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end if;
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end if;
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end process;
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end architecture;
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