100 lines
6.6 KiB
Plaintext
100 lines
6.6 KiB
Plaintext
# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 2020 Intel Corporation. All rights reserved.
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# Your use of Intel Corporation's design tools, logic functions
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# and other software and tools, and any partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Intel Program License
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# Subscription Agreement, the Intel Quartus Prime License Agreement,
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# the Intel FPGA IP License Agreement, or other applicable license
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# agreement, including, without limitation, that your use is for
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# the sole purpose of programming logic devices manufactured by
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# Intel and sold by Intel or its authorized distributors. Please
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# refer to the applicable agreement for further details, at
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# https://fpgasoftware.intel.com/eula.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus Prime
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# Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition
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# Date created = 13:33:09 November 02, 2020
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# top_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus Prime software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "Cyclone V"
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set_global_assignment -name DEVICE 5CSEBA6U23I7
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set_global_assignment -name TOP_LEVEL_ENTITY test_top
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:33:09 NOVEMBER 02, 2020"
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set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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set_global_assignment -name VHDL_FILE ../test6.vhd -hdl_version VHDL_2008
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set_global_assignment -name SDC_FILE ../top.sdc
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set_global_assignment -name VHDL_FILE ../test_top.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/Avalon_MM_wrapper.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/Tests/Level_2/L2_testbench_Lib4.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/Tests/test_loopback.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../test_fpga.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../dds_reader_syn.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/dds_reader.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../dds_writer_syn.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/dds_writer.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/Tests/Type1_config.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/Tests/Type1_writer_wrapper.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/Tests/Type1_reader_wrapper.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/Tests/Type1_key_holder.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/Tests/Type1_package.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/verbatim_key_hash_generator.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/key_hash_generator.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/key_holder.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../rtps_reader_syn.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/rtps_reader.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../rtps_writer_syn.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/rtps_writer.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/rtps_builtin_endpoint.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/rtps_handler.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/rtps_out.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../test5.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../test4.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../test3.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../test2.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../test.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../test_package.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/dp_mem_ctrl.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/mem_ctrl.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/FWFT_FIFO_cfg.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/FWFT_FIFO_Altera.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/FWFT_FIFO.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/dual_port_ram_cfg.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/dual_port_ram_Altera.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/dual_port_ram.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/single_port_ram_cfg.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/single_port_ram_Altera.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/single_port_ram.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/rtps_config_package.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../syn_config.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/rtps_package.vhd -hdl_version VHDL_2008
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set_global_assignment -name VHDL_FILE ../../src/math_pkg.vhd -hdl_version VHDL_2008
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top |