806 lines
36 KiB
VHDL
806 lines
36 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library osvvm; -- Utility Library
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context osvvm.OsvvmContext;
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use work.rtps_package.all;
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use work.user_config.all;
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use work.rtps_config_package.all;
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use work.rtps_test_package.all;
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-- This testbench tests the Deadline Handling of the DDS Writer, and more specifically the GET_OFFERED_DEADLINE_MISSED_STATUS DDS Operation.
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entity L0_dds_writer_test3 is
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end entity;
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architecture testbench of L0_dds_writer_test3 is
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-- *CONSTANT DECLARATION*
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constant MAX_REMOTE_ENDPOINTS : natural := 3;
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constant NUM_WRITERS : natural := 3;
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impure function gen_test_config return CONFIG_ARRAY_TYPE is
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variable ret : CONFIG_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => DEFAULT_WRITER_CONFIG);
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begin
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-- aik
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ret(0).HISTORY_QOS := KEEP_ALL_HISTORY_QOS;
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ret(0).DEADLINE_QOS := gen_duration(1 sec);
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ret(0).LIFESPAN_QOS := DURATION_INFINITE;
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ret(0).LEASE_DURATION := DURATION_INFINITE;
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ret(0).WITH_KEY := TRUE;
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ret(0).MAX_SAMPLES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH));
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ret(0).MAX_INSTANCES := std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH));
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ret(0).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH));
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ret(0).MAX_PAYLOAD_SIZE := 40;
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-- ain
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ret(1).HISTORY_QOS := KEEP_ALL_HISTORY_QOS;
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ret(1).DEADLINE_QOS := gen_duration(1 sec);
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ret(1).LIFESPAN_QOS := DURATION_INFINITE;
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ret(1).LEASE_DURATION := DURATION_INFINITE;
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ret(1).WITH_KEY := FALSE;
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ret(1).MAX_SAMPLES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH));
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ret(1).MAX_INSTANCES := std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH));
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ret(1).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH));
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ret(1).MAX_PAYLOAD_SIZE := 40;
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-- aik
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ret(2).HISTORY_QOS := KEEP_ALL_HISTORY_QOS;
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ret(2).DEADLINE_QOS := gen_duration(2 sec);
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ret(2).LIFESPAN_QOS := DURATION_INFINITE;
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ret(2).LEASE_DURATION := DURATION_INFINITE;
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ret(2).WITH_KEY := TRUE;
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ret(2).MAX_SAMPLES := std_logic_vector(to_unsigned(4,CDR_LONG_WIDTH));
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ret(2).MAX_INSTANCES := std_logic_vector(to_unsigned(3,CDR_LONG_WIDTH));
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ret(2).MAX_SAMPLES_PER_INSTANCE := std_logic_vector(to_unsigned(2,CDR_LONG_WIDTH));
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ret(2).MAX_PAYLOAD_SIZE := 40;
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return ret;
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end function;
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constant TEST_CONFIG : CONFIG_ARRAY_TYPE := gen_test_config;
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-- *TYPE DECLARATION*
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type DDS_STAGE_TYPE is (IDLE, START, PUSH, DONE, CHECK_DEADLINE);
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type RTPS_STAGE_TYPE is (IDLE, START, DONE, CHECK);
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-- *SIGNAL DECLARATION*
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signal clk : std_logic := '0';
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signal reset : std_logic := '1';
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signal check_time : TIME_TYPE := TIME_ZERO;
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signal start_rtps, start_dds, ack_rtps, ack_dds, done_rtps, done_dds, w_map : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0');
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signal opcode_rtps : HISTORY_CACHE_OPCODE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => NOP);
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signal opcode_dds : DDS_WRITER_OPCODE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => NOP);
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signal ret_rtps : HISTORY_CACHE_RESPONSE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => ERROR);
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signal seq_nr_rtps, cc_seq_nr : SEQUENCENUMBER_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => SEQUENCENUMBER_UNKNOWN);
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signal ready_out_rtps, valid_out_rtps, last_word_out_rtps : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0');
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signal ready_in_dds, ready_out_dds, valid_in_dds, valid_out_dds, last_word_in_dds, last_word_out_dds : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0');
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signal data_out_rtps, data_in_dds, data_out_dds : WORD_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => (others => '0'));
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signal get_data_rtps, liveliness_assertion, data_available : std_logic_vector(0 to NUM_WRITERS-1) := (others => '0');
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signal cc_source_timestamp, source_ts_dds : TIME_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => TIME_INVALID);
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signal cc_kind : CACHE_CHANGE_KIND_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => ALIVE);
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signal cc_instance_handle, instance_handle_in_dds, instance_handle_out_dds : INSTANCE_HANDLE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => HANDLE_NIL);
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signal max_wait_dds : DURATION_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => DURATION_INFINITE);
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signal return_code_dds : RETURN_CODE_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => (others => '0'));
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signal status : STATUS_KIND_ARRAY_TYPE(0 to NUM_WRITERS-1) := (others => (others => '0'));
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signal ind : natural := 0;
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signal dds_start, dds_done, rtps_start, rtps_done : std_logic := '0';
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signal dds_cnt, rtps_cnt : natural := 0;
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signal dds_stage : DDS_STAGE_TYPE := IDLE;
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signal rtps_stage : RTPS_STAGE_TYPE := IDLE;
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shared variable dds : DDS_WRITER_TEST_TYPE := DEFAULT_DDS_WRITER_TEST;
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shared variable rtps : RTPS_WRITER_TEST_TYPE := DEFAULT_RTPS_WRITER_TEST;
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signal inst_id, kind_id, sn_id, ts_id, data_id, ret_id, status_id, ih_id : AlertLogIDType;
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-- *FUNCTION DECLARATION*
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function extract_key_hash (payload : TEST_PACKET_TYPE) return INSTANCE_HANDLE_TYPE is
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variable ret : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
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begin
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for i in 0 to 3 loop
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ret(i) := not payload.data(i);
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end loop;
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return ret;
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end function;
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function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is
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variable ret : SEQUENCENUMBER_TYPE;
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begin
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ret(0) := (others => '0');
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ret(1) := unsigned(int(input, WORD_WIDTH));
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return ret;
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end function;
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procedure wait_on_sig(signal sig : std_logic) is
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begin
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if (sig /= '1') then
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wait on sig until sig = '1';
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end if;
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end procedure;
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begin
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-- Unit Under Test
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uut : entity work.dds_writer(arch)
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generic map(
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NUM_WRITERS => NUM_WRITERS,
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CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(TEST_CONFIG)
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)
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port map (
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clk => clk,
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reset => reset,
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time => check_time,
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start_rtps => start_rtps,
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opcode_rtps => opcode_rtps,
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ack_rtps => ack_rtps,
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done_rtps => done_rtps,
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ret_rtps => ret_rtps,
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seq_nr_rtps => seq_nr_rtps,
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get_data_rtps => get_data_rtps,
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data_out_rtps => data_out_rtps,
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valid_out_rtps => valid_out_rtps,
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ready_out_rtps => ready_out_rtps,
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last_word_out_rtps => last_word_out_rtps,
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liveliness_assertion => liveliness_assertion,
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data_available => data_available,
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cc_instance_handle => cc_instance_handle,
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cc_kind => cc_kind,
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cc_source_timestamp => cc_source_timestamp,
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cc_seq_nr => cc_seq_nr,
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start_dds => start_dds,
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ack_dds => ack_dds,
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opcode_dds => opcode_dds,
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instance_handle_in_dds => instance_handle_in_dds,
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source_ts_dds => source_ts_dds,
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max_wait_dds => max_wait_dds,
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done_dds => done_dds,
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return_code_dds => return_code_dds,
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instance_handle_out_dds => instance_handle_out_dds,
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ready_in_dds => ready_in_dds,
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valid_in_dds => valid_in_dds,
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data_in_dds => data_in_dds,
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last_word_in_dds => last_word_in_dds,
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ready_out_dds => ready_out_dds,
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valid_out_dds => valid_out_dds,
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data_out_dds => data_out_dds,
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last_word_out_dds => last_word_out_dds,
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status => status
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);
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stimulus_prc : process
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variable RV : RandomPType;
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variable kh1, kh2, kh3, kh4 : INSTANCE_HANDLE_TYPE := HANDLE_NIL;
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variable cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE;
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alias idle_sig is <<signal uut.idle_sig : std_logic>>;
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impure function gen_payload(key_hash : INSTANCE_HANDLE_TYPE; len : natural) return TEST_PACKET_TYPE is
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variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
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begin
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assert (len >= 4) report "Payload length has to be at least 16 Bytes long" severity FAILURE;
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for i in 0 to len-1 loop
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if (i < 4) then
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-- NOTE: Beginning of payload is negated key to allow deterministic Key Hash generation from the kh_prc
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ret.data(ret.length) := not key_hash(i);
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else
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ret.data(ret.length) := RV.RandSlv(WORD_WIDTH);
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end if;
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ret.length := ret.length + 1;
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end loop;
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ret.last(ret.length-1) := '1';
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return ret;
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end function;
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impure function gen_key_hash return KEY_HASH_TYPE is
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variable ret : KEY_HASH_TYPE := KEY_HASH_NIL;
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begin
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for i in 0 to KEY_HASH_TYPE'length-1 loop
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ret(i) := RV.RandSlv(WORD_WIDTH);
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end loop;
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return ret;
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end function;
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procedure start_dds is
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begin
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dds_start <= '1';
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wait until rising_edge(clk);
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dds_start <= '0';
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wait until rising_edge(clk);
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end procedure;
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procedure start_rtps is
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begin
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rtps_start <= '1';
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wait until rising_edge(clk);
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rtps_start <= '0';
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wait until rising_edge(clk);
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end procedure;
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procedure wait_on_completion is
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begin
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if (rtps_done /= '1' or dds_done /= '1') then
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wait until rtps_done = '1' and dds_done = '1';
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end if;
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end procedure;
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-- NOTE: This procedure waits until the idle_sig is high for at least
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-- two consecutive clock cycles.
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procedure wait_on_idle is
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variable first : boolean := TRUE;
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begin
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loop
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if (idle_sig /= '1') then
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wait until idle_sig = '1';
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elsif (not first) then
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exit;
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end if;
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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first := FALSE;
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end loop;
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end procedure;
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begin
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SetAlertLogName("L0_dds_writer_test3 - Deadline Handling");
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SetAlertEnable(FAILURE, TRUE);
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SetAlertEnable(ERROR, TRUE);
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SetAlertEnable(WARNING, TRUE);
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SetLogEnable(DEBUG, FALSE);
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SetLogEnable(PASSED, FALSE);
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SetLogEnable(INFO, TRUE);
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RV.InitSeed(RV'instance_name);
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inst_id <= GetAlertLogID("Instance", ALERTLOG_BASE_ID);
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kind_id <= GetAlertLogID("Cache Change Kind", ALERTLOG_BASE_ID);
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sn_id <= GetAlertLogID("SequenceNumber", ALERTLOG_BASE_ID);
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ts_id <= GetAlertLogID("TimeStamp", ALERTLOG_BASE_ID);
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ih_id <= GetAlertLogID("Instance Handle", ALERTLOG_BASE_ID);
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data_id <= GetAlertLogID("Data Out", ALERTLOG_BASE_ID);
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ret_id <= GetAlertLogID("Return Code", ALERTLOG_BASE_ID);
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status_id <= GetAlertLogID("Communication Status", ALERTLOG_BASE_ID);
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-- Key Hashes
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kh1 := gen_key_hash;
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kh2 := gen_key_hash;
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kh3 := gen_key_hash;
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kh4 := gen_key_hash;
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Log("Initiating Test", INFO);
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Log("Current Time: 0s", INFO);
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check_time <= TIME_ZERO;
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reset <= '1';
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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reset <= '0';
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wait_on_idle;
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AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
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AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
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AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
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Log("Current Time: 1s", INFO);
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check_time <= gen_duration(1 sec);
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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wait_on_idle;
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AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
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AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
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AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
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cc := DEFAULT_CACHE_CHANGE;
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cc.serialized_key := FALSE;
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cc.kind := ALIVE;
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cc.instance := kh1;
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cc.payload := gen_payload(kh1,10);
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Log("W0,W1,W2: DDS Operation WRITE [Instance 1, HANDLE_NIL, Aligned Payload]", INFO);
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Log("W0,W1,W2: ACCEPTED", DEBUG);
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dds := DEFAULT_DDS_WRITER_TEST;
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dds.opcode := WRITE;
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dds.cc := cc;
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dds.cc.instance:= HANDLE_NIL;
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dds.ret_code := RETCODE_OK;
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-- WRITER 0
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ind <= 0;
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start_dds;
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wait_on_sig(dds_done);
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-- WRITER 1
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ind <= 1;
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start_dds;
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wait_on_sig(dds_done);
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-- WRITER 2
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ind <= 2;
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start_dds;
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wait_on_sig(dds_done);
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wait_on_idle;
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cc := DEFAULT_CACHE_CHANGE;
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cc.serialized_key := FALSE;
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cc.kind := ALIVE;
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cc.instance := kh2;
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cc.payload := gen_payload(kh2,10);
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Log("W0,W2: DDS Operation WRITE [Instance 2, HANDLE_NIL, Aligned Payload]", INFO);
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Log("W0,W2: ACCEPTED", DEBUG);
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dds := DEFAULT_DDS_WRITER_TEST;
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dds.opcode := WRITE;
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dds.cc := cc;
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dds.cc.instance:= HANDLE_NIL;
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dds.ret_code := RETCODE_OK;
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-- WRITER 0
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ind <= 0;
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start_dds;
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wait_on_sig(dds_done);
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-- WRITER 2
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ind <= 2;
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start_dds;
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wait_on_sig(dds_done);
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wait_on_idle;
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Log("Current Time: 2s", INFO);
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check_time <= gen_duration(2 sec);
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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wait_on_idle;
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AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
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AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
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AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
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cc := DEFAULT_CACHE_CHANGE;
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cc.serialized_key := FALSE;
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cc.kind := ALIVE;
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cc.instance := kh1;
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cc.payload := gen_payload(kh1,10);
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Log("W0,W2: DDS Operation WRITE [Instance 1, Aligned Payload]", INFO);
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Log("W0,W2: ACCEPTED", DEBUG);
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dds := DEFAULT_DDS_WRITER_TEST;
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dds.opcode := WRITE;
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dds.cc := cc;
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dds.cc.instance:= HANDLE_NIL;
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dds.ret_code := RETCODE_OK;
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-- WRITER 0
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ind <= 0;
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start_dds;
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wait_on_sig(dds_done);
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-- WRITER 2
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ind <= 2;
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start_dds;
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wait_on_sig(dds_done);
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wait_on_idle;
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Log("Current Time: 3s", INFO);
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check_time <= gen_duration(3 sec);
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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wait_on_idle;
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AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
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AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
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AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
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Log("W0: DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS", INFO);
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Log("W0: Expected [count 1, change 1, Instance 2]", DEBUG);
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dds := DEFAULT_DDS_WRITER_TEST;
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dds.opcode := GET_OFFERED_DEADLINE_MISSED_STATUS;
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dds.ret_code := RETCODE_OK;
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dds.count := 1;
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dds.change := 1;
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dds.inst := kh2;
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-- WRITER 0
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ind <= 0;
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start_dds;
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wait_on_sig(dds_done);
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wait_on_idle;
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AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
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AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
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AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
|
|
|
Log("W1: DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS", INFO);
|
|
Log("W1: Expected [count 1, change 1]", DEBUG);
|
|
dds := DEFAULT_DDS_WRITER_TEST;
|
|
dds.opcode := GET_OFFERED_DEADLINE_MISSED_STATUS;
|
|
dds.ret_code := RETCODE_OK;
|
|
dds.count := 1;
|
|
dds.change := 1;
|
|
dds.inst := HANDLE_NIL;
|
|
-- WRITER 1
|
|
ind <= 1;
|
|
start_dds;
|
|
wait_on_sig(dds_done);
|
|
wait_on_idle;
|
|
|
|
AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
|
AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
|
AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
|
|
|
Log("W2: DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS", INFO);
|
|
Log("W2: Expected [count 0, change 0, HANDLE_NIL]", DEBUG);
|
|
dds := DEFAULT_DDS_WRITER_TEST;
|
|
dds.opcode := GET_OFFERED_DEADLINE_MISSED_STATUS;
|
|
dds.ret_code := RETCODE_OK;
|
|
dds.count := 0;
|
|
dds.change := 0;
|
|
dds.inst := HANDLE_NIL;
|
|
-- WRITER 2
|
|
ind <= 2;
|
|
start_dds;
|
|
wait_on_sig(dds_done);
|
|
wait_on_idle;
|
|
|
|
AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
|
AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
|
AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
|
|
|
cc := DEFAULT_CACHE_CHANGE;
|
|
cc.serialized_key := FALSE;
|
|
cc.kind := ALIVE;
|
|
cc.instance := kh3;
|
|
cc.payload := gen_payload(kh3,10);
|
|
|
|
Log("W0,W2: DDS Operation WRITE [Instance 3, Aligned Payload]", INFO);
|
|
Log("W0,W2: ACCEPTED", DEBUG);
|
|
dds := DEFAULT_DDS_WRITER_TEST;
|
|
dds.opcode := WRITE;
|
|
dds.cc := cc;
|
|
dds.cc.instance:= HANDLE_NIL;
|
|
dds.ret_code := RETCODE_OK;
|
|
-- WRITER 0
|
|
ind <= 0;
|
|
start_dds;
|
|
wait_on_sig(dds_done);
|
|
-- WRITER 2
|
|
ind <= 2;
|
|
start_dds;
|
|
wait_on_sig(dds_done);
|
|
wait_on_idle;
|
|
|
|
Log("Current Time: 4s", INFO);
|
|
check_time <= gen_duration(4 sec);
|
|
wait until rising_edge(clk);
|
|
wait until rising_edge(clk);
|
|
wait_on_idle;
|
|
|
|
AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
|
|
AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
|
|
AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
|
|
|
|
Log("W0: DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS", INFO);
|
|
Log("W0: Expected [count 3, change 2, Instance 1]", DEBUG);
|
|
dds := DEFAULT_DDS_WRITER_TEST;
|
|
dds.opcode := GET_OFFERED_DEADLINE_MISSED_STATUS;
|
|
dds.ret_code := RETCODE_OK;
|
|
dds.count := 3;
|
|
dds.change := 2;
|
|
dds.inst := kh1;
|
|
-- WRITER 0
|
|
ind <= 0;
|
|
start_dds;
|
|
wait_on_sig(dds_done);
|
|
wait_on_idle;
|
|
|
|
AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
|
AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
|
|
AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
|
|
|
|
Log("W2: DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS", INFO);
|
|
Log("W2: Expected [count 1, change 1, Instance 2]", DEBUG);
|
|
dds := DEFAULT_DDS_WRITER_TEST;
|
|
dds.opcode := GET_OFFERED_DEADLINE_MISSED_STATUS;
|
|
dds.ret_code := RETCODE_OK;
|
|
dds.count := 1;
|
|
dds.change := 1;
|
|
dds.inst := kh2;
|
|
-- WRITER 2
|
|
ind <= 2;
|
|
start_dds;
|
|
wait_on_sig(dds_done);
|
|
wait_on_idle;
|
|
|
|
AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
|
AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
|
|
AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
|
|
|
Log("Current Time: 5s", INFO);
|
|
check_time <= gen_duration(5 sec);
|
|
wait until rising_edge(clk);
|
|
wait until rising_edge(clk);
|
|
wait_on_idle;
|
|
|
|
AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
|
|
AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
|
|
AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
|
|
|
cc := DEFAULT_CACHE_CHANGE;
|
|
cc.serialized_key := FALSE;
|
|
cc.kind := ALIVE;
|
|
cc.instance := kh1;
|
|
cc.payload := gen_payload(kh1,10);
|
|
|
|
Log("W1: DDS Operation WRITE [Instance 1, Aligned Payload]", INFO);
|
|
Log("W1: ACCEPTED", DEBUG);
|
|
dds := DEFAULT_DDS_WRITER_TEST;
|
|
dds.opcode := WRITE;
|
|
dds.cc := cc;
|
|
dds.cc.instance:= HANDLE_NIL;
|
|
dds.ret_code := RETCODE_OK;
|
|
-- WRITER 1
|
|
ind <= 1;
|
|
start_dds;
|
|
wait_on_sig(dds_done);
|
|
wait_on_idle;
|
|
|
|
Log("Current Time: 6s", INFO);
|
|
check_time <= gen_duration(6 sec);
|
|
wait until rising_edge(clk);
|
|
wait until rising_edge(clk);
|
|
wait_on_idle;
|
|
|
|
AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
|
|
AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
|
|
AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
|
|
|
|
Log("W0: DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS", INFO);
|
|
Log("W0: Expected [count 9, change 6, Instance 1]", DEBUG);
|
|
dds := DEFAULT_DDS_WRITER_TEST;
|
|
dds.opcode := GET_OFFERED_DEADLINE_MISSED_STATUS;
|
|
dds.ret_code := RETCODE_OK;
|
|
dds.count := 9;
|
|
dds.change := 6;
|
|
dds.inst := kh1;
|
|
-- WRITER 0
|
|
ind <= 0;
|
|
start_dds;
|
|
wait_on_sig(dds_done);
|
|
wait_on_idle;
|
|
|
|
AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
|
AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
|
|
AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
|
|
|
|
Log("W1: DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS", INFO);
|
|
Log("W1: Expected [count 3, change 2]", DEBUG);
|
|
dds := DEFAULT_DDS_WRITER_TEST;
|
|
dds.opcode := GET_OFFERED_DEADLINE_MISSED_STATUS;
|
|
dds.ret_code := RETCODE_OK;
|
|
dds.count := 3;
|
|
dds.change := 2;
|
|
dds.inst := HANDLE_NIL;
|
|
-- WRITER 1
|
|
ind <= 1;
|
|
start_dds;
|
|
wait_on_sig(dds_done);
|
|
wait_on_idle;
|
|
|
|
AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
|
AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
|
AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) = OFFERED_DEADLINE_MISSED_STATUS, "Expected: 1", "Received: 0");
|
|
|
|
Log("W2: DDS Operation GET_OFFERED_DEADLINE_MISSED_STATUS", INFO);
|
|
Log("W2: Expected [count 4, change 3, Instance 1]", DEBUG);
|
|
dds := DEFAULT_DDS_WRITER_TEST;
|
|
dds.opcode := GET_OFFERED_DEADLINE_MISSED_STATUS;
|
|
dds.ret_code := RETCODE_OK;
|
|
dds.count := 4;
|
|
dds.change := 3;
|
|
dds.inst := kh1;
|
|
-- WRITER 2
|
|
ind <= 2;
|
|
start_dds;
|
|
wait_on_sig(dds_done);
|
|
wait_on_idle;
|
|
|
|
AffirmIf(status_id,(status(0) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
|
AffirmIf(status_id,(status(1) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
|
AffirmIf(status_id,(status(2) and OFFERED_DEADLINE_MISSED_STATUS) /= OFFERED_DEADLINE_MISSED_STATUS, "Expected: 0", "Received: 1");
|
|
|
|
wait_on_completion;
|
|
TranscriptOpen(RESULTS_FILE, APPEND_MODE);
|
|
SetTranscriptMirror;
|
|
ReportAlerts;
|
|
TranscriptClose;
|
|
std.env.stop;
|
|
wait;
|
|
end process;
|
|
|
|
clock_prc : process
|
|
begin
|
|
clk <= '0';
|
|
wait for 25 ns;
|
|
clk <= '1';
|
|
wait for 25 ns;
|
|
end process;
|
|
|
|
dds_prc : process(all)
|
|
begin
|
|
if rising_edge(clk) then
|
|
dds_done <= '0';
|
|
case (dds_stage) is
|
|
when IDLE =>
|
|
if (dds_start = '1') then
|
|
dds_stage <= START;
|
|
else
|
|
dds_done <= '1';
|
|
end if;
|
|
when START =>
|
|
if (ack_dds(ind) = '1') then
|
|
case (dds.opcode) is
|
|
when GET_OFFERED_DEADLINE_MISSED_STATUS =>
|
|
dds_stage <= DONE;
|
|
dds_cnt <= 0;
|
|
when others =>
|
|
dds_stage <= PUSH;
|
|
dds_cnt <= 0;
|
|
end case;
|
|
end if;
|
|
when PUSH =>
|
|
if (ready_in_dds(ind) = '1') then
|
|
dds_cnt <= dds_cnt + 1;
|
|
if (dds_cnt = dds.cc.payload.length-1) then
|
|
-- DEFAULT
|
|
dds_stage <= DONE;
|
|
end if;
|
|
end if;
|
|
when DONE =>
|
|
if (done_dds(ind) = '1') then
|
|
if (dds.opcode = REGISTER_INSTANCE or dds.opcode = LOOKUP_INSTANCE) then
|
|
AffirmIfEqual(ih_id, to_unsigned(instance_handle_out_dds(ind)), to_unsigned(dds.cc.instance));
|
|
else
|
|
AffirmIfEqual(ret_id, return_code_dds(ind), dds.ret_code);
|
|
case (dds.opcode) is
|
|
when GET_OFFERED_DEADLINE_MISSED_STATUS =>
|
|
if (dds.ret_code = RETCODE_OK) then
|
|
dds_stage <= CHECK_DEADLINE;
|
|
dds_cnt <= 0;
|
|
else
|
|
dds_stage <= IDLE;
|
|
end if;
|
|
when others =>
|
|
dds_stage <= IDLE;
|
|
end case;
|
|
end if;
|
|
end if;
|
|
when CHECK_DEADLINE =>
|
|
if (valid_out_dds(ind) = '1') then
|
|
dds_cnt <= dds_cnt + 1;
|
|
case (dds_cnt) is
|
|
when 0 =>
|
|
AffirmIfEqual(data_id, data_out_dds(ind), std_logic_vector(to_unsigned(dds.count,CDR_LONG_WIDTH)));
|
|
when 1 =>
|
|
AffirmIfEqual(data_id, data_out_dds(ind), std_logic_vector(to_unsigned(dds.change,CDR_LONG_WIDTH)));
|
|
when 2 =>
|
|
AffirmIfEqual(data_id, data_out_dds(ind), std_logic_vector(dds.inst(0)));
|
|
when 3 =>
|
|
AffirmIfEqual(data_id, data_out_dds(ind), std_logic_vector(dds.inst(1)));
|
|
when 4 =>
|
|
AffirmIfEqual(data_id, data_out_dds(ind), std_logic_vector(dds.inst(2)));
|
|
when 5 =>
|
|
AffirmIfEqual(data_id, data_out_dds(ind), std_logic_vector(dds.inst(3)));
|
|
AlertIf(data_id, last_word_out_dds(ind) /= '1', "Last Word Signal not pulled High", ERROR);
|
|
dds_stage <= IDLE;
|
|
when others =>
|
|
null;
|
|
end case;
|
|
end if;
|
|
end case;
|
|
end if;
|
|
|
|
-- DEFAULT
|
|
start_dds <= (others => '0');
|
|
opcode_dds <= (others => NOP);
|
|
valid_in_dds <= (others => '0');
|
|
last_word_in_dds <= (others => '0');
|
|
data_in_dds <= (others => (others => '0'));
|
|
instance_handle_in_dds <= (others => HANDLE_NIL);
|
|
source_ts_dds <= (others => TIME_INVALID);
|
|
ready_out_dds <= (others => '0');
|
|
|
|
case (dds_stage) is
|
|
when START =>
|
|
start_dds(ind) <= '1';
|
|
opcode_dds(ind) <= dds.opcode;
|
|
instance_handle_in_dds(ind) <= dds.cc.instance;
|
|
source_ts_dds(ind) <= dds.cc.src_timestamp;
|
|
when PUSH =>
|
|
valid_in_dds(ind) <= '1';
|
|
data_in_dds(ind) <= dds.cc.payload.data(dds_cnt);
|
|
last_word_in_dds(ind) <= dds.cc.payload.last(dds_cnt);
|
|
when CHECK_DEADLINE =>
|
|
ready_out_dds(ind) <= '1';
|
|
when others =>
|
|
null;
|
|
end case;
|
|
end process;
|
|
|
|
rtps_prc : process(all)
|
|
begin
|
|
if rising_edge(clk) then
|
|
rtps_done <= '0';
|
|
case (rtps_stage) is
|
|
when IDLE =>
|
|
if (rtps_start = '1') then
|
|
rtps_stage <= START;
|
|
else
|
|
rtps_done <= '1';
|
|
end if;
|
|
when START =>
|
|
if (ack_rtps(ind) = '1') then
|
|
rtps_stage <= DONE;
|
|
end if;
|
|
when DONE =>
|
|
if (done_rtps(ind) = '1') then
|
|
-- DEFAULT
|
|
rtps_stage <= IDLE;
|
|
|
|
AffirmIfEqual(ret_id, HISTORY_CACHE_RESPONSE_TYPE'pos(ret_rtps(ind)), HISTORY_CACHE_RESPONSE_TYPE'pos(rtps.ret_code));
|
|
case (rtps.opcode) is
|
|
when GET_CACHE_CHANGE =>
|
|
if (rtps.ret_code = OK) then
|
|
AffirmIfEqual(inst_id, to_unsigned(cc_instance_handle(ind)), to_unsigned(rtps.cc.instance));
|
|
AffirmIfEqual(kind_id, CACHE_CHANGE_KIND_TYPE'pos(cc_kind(ind)), CACHE_CHANGE_KIND_TYPE'pos(rtps.cc.kind));
|
|
AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr(ind)), to_unsigned(rtps.cc.seq_nr));
|
|
AffirmIfEqual(ts_id, to_unsigned(cc_source_timestamp(ind)), to_unsigned(rtps.cc.src_timestamp));
|
|
rtps_stage <= CHECK;
|
|
rtps_cnt <= 0;
|
|
end if;
|
|
when GET_MIN_SN =>
|
|
AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr(ind)), to_unsigned(rtps.cc.seq_nr));
|
|
when GET_MAX_SN =>
|
|
AffirmIfEqual(sn_id, to_unsigned(cc_seq_nr(ind)), to_unsigned(rtps.cc.seq_nr));
|
|
when others =>
|
|
null;
|
|
end case;
|
|
end if;
|
|
when CHECK =>
|
|
if (valid_out_rtps(ind) = '1') then
|
|
AffirmIfEqual(data_id, last_word_out_rtps(ind) & data_out_rtps(ind), rtps.cc.payload.last(rtps_cnt) & rtps.cc.payload.data(rtps_cnt));
|
|
rtps_cnt <= rtps_cnt + 1;
|
|
if (rtps_cnt = rtps.cc.payload.length-1) then
|
|
rtps_stage <= IDLE;
|
|
end if;
|
|
end if;
|
|
end case;
|
|
end if;
|
|
|
|
-- DEFAULT
|
|
start_rtps <= (others => '0');
|
|
opcode_rtps <= (others => NOP);
|
|
seq_nr_rtps <= (others => SEQUENCENUMBER_UNKNOWN);
|
|
get_data_rtps <= (others => '0');
|
|
ready_out_rtps <= (others => '0');
|
|
|
|
case (rtps_stage) is
|
|
when START =>
|
|
start_rtps(ind) <= '1';
|
|
opcode_rtps(ind) <= rtps.opcode;
|
|
seq_nr_rtps(ind) <= rtps.cc.seq_nr;
|
|
when DONE =>
|
|
if (done_rtps(ind) = '1') then
|
|
case (rtps.opcode) is
|
|
when GET_CACHE_CHANGE =>
|
|
get_data_rtps(ind) <= '1';
|
|
when others =>
|
|
null;
|
|
end case;
|
|
end if;
|
|
when CHECK =>
|
|
ready_out_rtps(ind) <= '1';
|
|
when others =>
|
|
null;
|
|
end case;
|
|
end process;
|
|
|
|
watchdog : process
|
|
begin
|
|
wait for 1 ms;
|
|
Alert("Test timeout", FAILURE);
|
|
std.env.stop;
|
|
end process;
|
|
|
|
end architecture; |