Greek64 6724156e72 TIMING CLOSURE: Split main FSM in dds_reader ... The sequential logic of the main FSM in dds_reader was just to big to pass the timing requirement of 50 MHz. All the DDS READ/TAKE relevant states were removed from the main FSM, and added to a seperate read FSM. This reduces the state numberes and state tarnsition logic of the main FSM, allowing it to pass the timing requirements.		2022-04-14 14:27:09 +02:00
doc	Add documentation	2021-11-17 14:27:30 +01:00
sim	Convert dds_reader to Vector Endpoint	2022-04-10 11:04:59 +02:00
src	TIMING CLOSURE: Split main FSM in dds_reader	2022-04-14 14:27:09 +02:00
syn	TIMING CLOSURE: Split main FSM in dds_reader	2022-04-14 14:27:09 +02:00
.gitattributes	* Added DDS/RTPS Documentation	2020-05-10 19:31:49 +02:00
.gitignore	code refactoring	2021-12-09 19:44:39 +01:00
.gitmodules	* Added OSVVM Library as Submodule	2020-11-15 20:34:39 +01:00
READ.txt	Add complete Level2 System Test	2021-11-17 14:23:53 +01:00
Report.txt	* Added Documentation	2020-05-24 13:08:03 +02:00
ros_action_Fibonacci_with_feedback2.rpt	Convert rtps_writer to Vector Endpoint	2022-04-05 17:18:07 +02:00
ros_action_Fibonacci_with_feedback3.rpt	Convert rtps_writer to Vector Endpoint	2022-04-05 17:18:07 +02:00
ros_action_Fibonacci_with_feedback4.rpt	Convert rtps_reader to Vector Endpoint	2022-04-05 17:20:22 +02:00
ros_action_Fibonacci_with_feedback5.rpt	Convert dds_writer to Vector Endpoint	2022-04-10 11:04:02 +02:00
ros_action_Fibonacci_with_feedback6.rpt	TIMING CLOSURE: Split main FSM in dds_reader	2022-04-14 14:27:09 +02:00
ros_action_Fibonacci_with_feedback.rpt	Add/Modify synthesis entities to synthesize Fibonacci_ros_action_server	2022-03-13 12:43:12 +01:00
ros_action_Fibonacci_with_feedback.txt	TIMING CLOSURE: Split main FSM in dds_reader	2022-04-14 14:27:09 +02:00
ros_action_Fibonacci_without_feedback.rpt	Add/Modify synthesis entities to synthesize Fibonacci_ros_action_server	2022-03-13 12:43:12 +01:00
VHDL-2008.txt	Code Refactor	2021-05-15 20:39:56 +02:00